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Advanced Electronic Materials
先进电子材料

The synthesis of two-dimensional materials for post-Moore integrated circuits
面向后摩尔集成电路的二维材料合成

–Manuscript Draft–  –手稿草稿–
Manuscript Number:  手稿编号: aelm. 202500218
Article Type:  文章类型: Review  综述
Corresponding Author:  通讯作者:

何军,教授,武汉大学,武汉,中国
Jun He, Prof.
Wuhan University
Wuhan, CHINA
Jun He, Prof. Wuhan University Wuhan, CHINA| Jun He, Prof. | | :--- | | Wuhan University | | Wuhan, CHINA |
Order of Authors:  作者顺序: Jun He, Prof.  何军,教授
Ziren Xiong  熊子仁
Hao Zhu  朱浩
Yao Wen  文尧
Zhengyang Long  龙正阳
Hao Wang  王浩
Lizhikun Gong  龚立志坤
Chuanyang Cai  蔡传阳
Hui Zeng  曾辉
Yangyuan Tu  涂扬元
Shoufeng Yang  杨守峰
Lei Yin  尹磊
Ruiqing Cheng  程瑞清
Keywords:  关键词: two-dimensional transistors , synthesis 2D semiconductor materials, synthesis 2D dielectric layers, Low-temperature growth of two-dimensional materials ,
二维晶体管,二维半导体材料合成,二维介电层合成,二维材料的低温生长,
Abstract:  摘要: With the continuous scaling down of channel dimensions, the relentless miniaturization of CMOS-based integrated circuits is increasingly constrained by short-channel effects, leakage currents, and quantum tunneling phenomena, suggesting that Moore's Law is approaching its physical limits. two-dimensional (2D) materials, distinguished by their ultrathin nature, exceptional carrier mobility, and intrinsic passivation characteristics, offer a promising solution to mitigation short-channel effects while maintaining ultra-low leakage currents. Consequently, they are considered a viable pathway for further device miniaturization. In this review, we focus on 2D transistors, elaborating on recent advancements in synthesizing wafer-scale single-crystal 2D semiconductor materials, with particular emphasis on low-temperature ( < 450 C ) < 450 C ( < 450^(@)C)\left(<450^{\circ} \mathrm{C}\right) synthesis techniques. Additionally, we summarize innovative strategies for synthesizing 2D dielectric layers that exhibit superior compatible with 2D semiconductor materials. Subsequently, we discuss strategies to optimize the contact between 2D semiconductor materials and metal electrodes. Crucial advancements in 2D transistor technology, encompassing large-scale integration and unconventional device architectures, are also highlighted. Finally, we delineate the major technical challenges and potential optimization directions for 2D transistors. We are confident that resolving these bottlenecks will catalyze unprecedented advancements in post-Moore integrated circuit technology.
随着通道尺寸的不断缩小,基于 CMOS 的集成电路的持续微型化越来越受到短沟道效应、漏电流和量子隧穿现象的限制,表明摩尔定律正接近其物理极限。二维(2D)材料以其超薄特性、卓越的载流子迁移率和固有的钝化特性,提供了一种有前景的解决方案,以缓解短沟道效应,同时保持超低漏电流。因此,它们被认为是进一步器件微型化的可行途径。在本综述中,我们聚焦于 2D 晶体管,详细介绍了晶圆级单晶 2D 半导体材料合成的最新进展,特别强调低温 ( < 450 C ) < 450 C ( < 450^(@)C)\left(<450^{\circ} \mathrm{C}\right) 合成技术。此外,我们总结了合成与 2D 半导体材料高度兼容的 2D 介电层的创新策略。随后,我们讨论了优化 2D 半导体材料与金属电极接触的策略。 文章还重点介绍了二维晶体管技术的关键进展,包括大规模集成和非常规器件架构。最后,我们阐述了二维晶体管面临的主要技术挑战及潜在的优化方向。我们相信,解决这些瓶颈将推动后摩尔集成电路技术的前所未有的发展。
Manuscript Number: aelm. 202500218 Article Type: Review Corresponding Author: "Jun He, Prof. Wuhan University Wuhan, CHINA" Order of Authors: Jun He, Prof. Ziren Xiong Hao Zhu Yao Wen Zhengyang Long Hao Wang Lizhikun Gong Chuanyang Cai Hui Zeng Yangyuan Tu Shoufeng Yang Lei Yin Ruiqing Cheng Keywords: two-dimensional transistors , synthesis 2D semiconductor materials, synthesis 2D dielectric layers, Low-temperature growth of two-dimensional materials , Abstract: With the continuous scaling down of channel dimensions, the relentless miniaturization of CMOS-based integrated circuits is increasingly constrained by short-channel effects, leakage currents, and quantum tunneling phenomena, suggesting that Moore's Law is approaching its physical limits. two-dimensional (2D) materials, distinguished by their ultrathin nature, exceptional carrier mobility, and intrinsic passivation characteristics, offer a promising solution to mitigation short-channel effects while maintaining ultra-low leakage currents. Consequently, they are considered a viable pathway for further device miniaturization. In this review, we focus on 2D transistors, elaborating on recent advancements in synthesizing wafer-scale single-crystal 2D semiconductor materials, with particular emphasis on low-temperature ( < 450^(@)C) synthesis techniques. Additionally, we summarize innovative strategies for synthesizing 2D dielectric layers that exhibit superior compatible with 2D semiconductor materials. Subsequently, we discuss strategies to optimize the contact between 2D semiconductor materials and metal electrodes. Crucial advancements in 2D transistor technology, encompassing large-scale integration and unconventional device architectures, are also highlighted. Finally, we delineate the major technical challenges and potential optimization directions for 2D transistors. We are confident that resolving these bottlenecks will catalyze unprecedented advancements in post-Moore integrated circuit technology.| Manuscript Number: | aelm. 202500218 | | :--- | :--- | | Article Type: | Review | | Corresponding Author: | Jun He, Prof. <br> Wuhan University <br> Wuhan, CHINA | | Order of Authors: | Jun He, Prof. | | | Ziren Xiong | | | Hao Zhu | | | Yao Wen | | | Zhengyang Long | | | Hao Wang | | | Lizhikun Gong | | | Chuanyang Cai | | | Hui Zeng | | | Yangyuan Tu | | | Shoufeng Yang | | | Lei Yin | | | Ruiqing Cheng | | Keywords: | two-dimensional transistors , synthesis 2D semiconductor materials, synthesis 2D dielectric layers, Low-temperature growth of two-dimensional materials , | | Abstract: | With the continuous scaling down of channel dimensions, the relentless miniaturization of CMOS-based integrated circuits is increasingly constrained by short-channel effects, leakage currents, and quantum tunneling phenomena, suggesting that Moore's Law is approaching its physical limits. two-dimensional (2D) materials, distinguished by their ultrathin nature, exceptional carrier mobility, and intrinsic passivation characteristics, offer a promising solution to mitigation short-channel effects while maintaining ultra-low leakage currents. Consequently, they are considered a viable pathway for further device miniaturization. In this review, we focus on 2D transistors, elaborating on recent advancements in synthesizing wafer-scale single-crystal 2D semiconductor materials, with particular emphasis on low-temperature $\left(<450^{\circ} \mathrm{C}\right)$ synthesis techniques. Additionally, we summarize innovative strategies for synthesizing 2D dielectric layers that exhibit superior compatible with 2D semiconductor materials. Subsequently, we discuss strategies to optimize the contact between 2D semiconductor materials and metal electrodes. Crucial advancements in 2D transistor technology, encompassing large-scale integration and unconventional device architectures, are also highlighted. Finally, we delineate the major technical challenges and potential optimization directions for 2D transistors. We are confident that resolving these bottlenecks will catalyze unprecedented advancements in post-Moore integrated circuit technology. |

The synthesis of two-dimensional materials for post-Moore
用于后摩尔时代的二维材料合成

integrated circuits  集成电路

Ziren Xiong 1 , 1 , ^(1,†){ }^{1, \dagger}, Hao Zhu 1 , 1 , ^(1,†){ }^{1, \dagger}, Yao Wen 1 , 1 , ^(1,†){ }^{1, \dagger}, Zhengyang Long 1 , 1 , ^(1,†){ }^{1, \dagger}, Hao Wang 1 1 ^(1){ }^{1}, Lizhikun Gong 1 1 ^(1){ }^{1}, Chuanyang Cai 1 1 ^(1){ }^{1}, Hui Zeng 1 1 ^(1){ }^{1}, Yangyuan Tu 1 1 ^(1){ }^{1}, Shoufeng Yang 1 1 ^(1){ }^{1}, Lei Yin 1 1 ^(1){ }^{1}, Ruiqing Cheng 1 1 ^(1){ }^{1}, Jun He 1 , 2 , 3 He 1 , 2 , 3 He^(1,2,3**)\mathrm{He}^{1,2,3 *}
熊子仁 1 , 1 , ^(1,†){ }^{1, \dagger} ,朱昊 1 , 1 , ^(1,†){ }^{1, \dagger} ,文尧 1 , 1 , ^(1,†){ }^{1, \dagger} ,龙正阳 1 , 1 , ^(1,†){ }^{1, \dagger} ,王昊 1 1 ^(1){ }^{1} ,龚立志坤 1 1 ^(1){ }^{1} ,蔡传阳 1 1 ^(1){ }^{1} ,曾辉 1 1 ^(1){ }^{1} ,涂阳远 1 1 ^(1){ }^{1} ,杨守锋 1 1 ^(1){ }^{1} ,尹磊 1 1 ^(1){ }^{1} ,程锐清 1 1 ^(1){ }^{1} ,君 He 1 , 2 , 3 He 1 , 2 , 3 He^(1,2,3**)\mathrm{He}^{1,2,3 *}
1 1 ^(1){ }^{1} Key Laboratory of Artificial Micro- and Nano-structures of Ministry of Education and School of Physics and Technology, Wuhan University, Wuhan 430072, China.
1 1 ^(1){ }^{1} 教育部人工微纳结构重点实验室及武汉大学物理与技术学院,中国武汉 430072。
2 2 ^(2){ }^{2} Wuhan Institute of Quantum Technology, Wuhan 430206, China
2 2 ^(2){ }^{2} 武汉量子技术研究院,中国武汉 430206。
3 3 ^(3){ }^{3} Center of Materials Science and Optoelectronics Engineering, University of Chinese Academy of Sciences, Beijing 100190, China
3 3 ^(3){ }^{3} 中国科学院大学材料科学与光电子工程中心,北京 100190,中国。
^(†){ }^{\dagger} These authors contribute equally to this work,
^(†){ }^{\dagger} 这些作者对本工作贡献相同,
*Emails: hej@nanoctr.cn  *电子邮件:hej@nanoctr.cn

Abstract  摘要

With the continuous scaling down of channel dimensions, the relentless miniaturization of CMOS-based integrated circuits is increasingly constrained by short-channel effects, leakage currents, and quantum tunneling phenomena, suggesting that Moore’s Law is approaching its physical limits. two-dimensional (2D) materials, distinguished by their ultrathin nature, exceptional carrier mobility, and intrinsic passivation characteristics, offer a promising solution to mitigation short-channel effects while maintaining ultra-low leakage currents. Consequently, they are considered a viable pathway for further device miniaturization. In this review, we focus on 2D transistors, elaborating on recent advancements in synthesizing wafer-scale single-crystal 2D semiconductor materials, with particular emphasis on low-temperature ( < 450 C ) < 450 C ( < 450^(@)C)\left(<450^{\circ} \mathrm{C}\right) synthesis techniques. Additionally, this review summarize innovative strategies for synthesizing 2D dielectric layers that exhibit superior compatible with 2D semiconductor materials. Subsequently, this review discuss strategies to optimize the contact between 2D semiconductor materials and metal electrodes. Crucial advancements in 2D transistor technology, encompassing large-scale integration and unconventional device architectures, are also highlighted. Finally, this review delineate the major technical challenges and potential optimization directions for 2D transistors. This review are confident that resolving these bottlenecks will catalyze unprecedented advancements in post-Moore integrated circuit technology.
随着通道尺寸的不断缩小,基于 CMOS 的集成电路的持续微型化正日益受到短沟道效应、漏电流和量子隧穿现象的限制,表明摩尔定律正接近其物理极限。二维(2D)材料以其超薄特性、卓越的载流子迁移率和固有的钝化特性,提供了一种有希望的解决方案,以缓解短沟道效应,同时保持超低漏电流。因此,它们被认为是进一步器件微型化的可行途径。在本综述中,我们聚焦于二维晶体管,详细介绍了晶圆级单晶二维半导体材料的最新合成进展,特别强调低温 ( < 450 C ) < 450 C ( < 450^(@)C)\left(<450^{\circ} \mathrm{C}\right) 合成技术。此外,本文总结了合成与二维半导体材料高度兼容的二维介电层的创新策略。随后,本文讨论了优化二维半导体材料与金属电极接触的策略。 本文还重点介绍了二维晶体管技术的关键进展,包括大规模集成和非常规器件架构。最后,本文阐述了二维晶体管面临的主要技术挑战和潜在的优化方向。我们相信,解决这些瓶颈将推动后摩尔集成电路技术的前所未有的发展。

1.Introduction  1. 引言

Centered on Complementary Metal-Oxide-Semiconductor (CMOS) technology,
以互补金属氧化物半导体(CMOS)技术为中心,

integrated circuits have become essential components in microprocessors, Static Random-Access Memory (SRAM), and various digital logic circuits [ 1 , 2 ] [ 1 , 2 ] ^([1,2]){ }^{[1,2]}. However, as channel lengths approach the 5 -nm regime, traditional three-dimensional stacked chip architectures exhibit unit-area thermal densities that surpass silicon’s transient thermal capacitance limit, thereby destabilizing channel materials. Furthermore, with continued scaling of channel dimensions, short-channel effects and quantum tunneling phenomena become pronounced, leading to elevated leakage currents in semiconductor devices and a significant increase in power consumption [ 3 6 ] [ 3 6 ] ^([3-6]){ }^{[3-6]}. As a result, Moore’s Law faces imminent limitations, posing severe challenges to the future advancement of integrated circuits [ 7 ] [ 7 ] ^([7]){ }^{[7]}.
集成电路已成为微处理器、静态随机存取存储器(SRAM)和各种数字逻辑电路中的关键组件 [ 1 , 2 ] [ 1 , 2 ] ^([1,2]){ }^{[1,2]} 。然而,随着沟道长度接近 5 纳米级别,传统的三维堆叠芯片架构表现出超过硅瞬态热容极限的单位面积热密度,从而导致沟道材料不稳定。此外,随着沟道尺寸的持续缩小,短沟道效应和量子隧穿现象变得显著,导致半导体器件的漏电流增加,功耗显著上升 [ 3 6 ] [ 3 6 ] ^([3-6]){ }^{[3-6]} 。因此,摩尔定律面临迫在眉睫的限制,对集成电路的未来发展构成严峻挑战 [ 7 ] [ 7 ] ^([7]){ }^{[7]}
In recent years, 2D materials have garnered significant attention from researchers due to their unique properties and ultrathin thickness [ 8 11 ] [ 8 11 ] ^([8-11]){ }^{[8-11]}. 2D semiconductor materials, including transition metal sulfur compounds (TMDCs) and black phosphorus, have seen remarkable advancements in high-frequency electronic devices [ 12 , 13 ] [ 12 , 13 ] ^([12,)^(13]){ }^{[12,}{ }^{13]}, and optoelectronic integration [ 14 16 ] [ 14 16 ] ^([14-16]){ }^{[14-16]}, leveraging their atomic-scale thickness to exhibit quantum confinement effect, ultra-high carrier mobility, and in-surface anisotropy [ 17 [ 17 ^([17){ }^{[17}, 18 ] 18 ] ^(18]){ }^{18]}. Unlike conventional semiconductor devices, the naturally passivated surface of 2D semiconductor eliminates dangling bonds, thereby significantly reducing interfacial scattering and impurity trap scattering [ 19 ] [ 19 ] ^([19]){ }^{[19]}. Moreover, 2D semiconductors possess sub-threshold swing (SS) values approaching the Boltzmann limit, offering a transformative technological pathway for achieving ultra-low power consumption and high integration density in the post-Moore era [ 20 22 ] [ 20 22 ] ^([20-22]){ }^{[20-22]}. Additionally, their ultrathin nature effectively suppress the short-channel effect, enhancing switching speed and minimizing power consumption [ 23 , 24 ] [ 23 , 24 ] ^([23,24]){ }^{[23,24]}. The compatibility of 2D materials with flexible substrates further promotes the development of flexible electronics and enables opportunities for 3D heterogeneous integration [ 25 , 26 ] [ 25 , 26 ] ^([25,26]){ }^{[25,26]}. Furthermore, the bandgap of certain 2D semiconductor materials is tunable, which is important for optimizing the performance of logic circuits, holding great potential for ultra-high-density 3D integration [ 27 ] [ 27 ] ^([27]){ }^{[27]}. In this context, 2D materials emerge as promising candidates for overcoming the limitations of Moore’s law.
近年来,二维材料因其独特的性质和超薄厚度受到研究人员的广泛关注 [ 8 11 ] [ 8 11 ] ^([8-11]){ }^{[8-11]} 。二维半导体材料,包括过渡金属硫化物(TMDCs)和黑磷,在高频电子器件 [ 12 , 13 ] [ 12 , 13 ] ^([12,)^(13]){ }^{[12,}{ }^{13]} 和光电子集成 [ 14 16 ] [ 14 16 ] ^([14-16]){ }^{[14-16]} 方面取得了显著进展,利用其原子级厚度展现出量子限域效应、超高载流子迁移率和面内各向异性 [ 17 [ 17 ^([17){ }^{[17} 18 ] 18 ] ^(18]){ }^{18]} 。与传统半导体器件不同,二维半导体的自然钝化表面消除了悬挂键,从而显著减少了界面散射和杂质陷阱散射 [ 19 ] [ 19 ] ^([19]){ }^{[19]} 。此外,二维半导体具有接近玻尔兹曼极限的亚阈值摆幅(SS)值,为实现后摩尔时代的超低功耗和高集成度提供了变革性的技术路径 [ 20 22 ] [ 20 22 ] ^([20-22]){ }^{[20-22]} 。另外,其超薄特性有效抑制了短沟道效应,提高了开关速度并最小化了功耗 [ 23 , 24 ] [ 23 , 24 ] ^([23,24]){ }^{[23,24]} 。 二维材料与柔性基板的兼容性进一步促进了柔性电子的发展,并为三维异质集成提供了机会 [ 25 , 26 ] [ 25 , 26 ] ^([25,26]){ }^{[25,26]} 。此外,某些二维半导体材料的带隙是可调的,这对于优化逻辑电路的性能非常重要,具有超高密度三维集成的巨大潜力 [ 27 ] [ 27 ] ^([27]){ }^{[27]} 。在此背景下,二维材料成为克服摩尔定律限制的有前景的候选材料。
2D transistors continue to evolve, yet numerous challenges remain to be addressed. For the post-Moore-era transistor technology of 2D semiconductor materials, the growth of high-quality, large-area 2D semiconductor materials is a critical aspect [ 28 , 29 ] [ 28 , 29 ] ^([28,29]){ }^{[28,29]}. However, 2D materials exhibit randomly distributed nucleation points and equivalence between antiparallel islands during growth. Additionally, their growth modes are highly susceptible to perturbations from various factors, including temperature gradients and airflow, which significantly hinder the continuous growth of high-quality thin films [ 30 , 31 ] [ 30 , 31 ] ^([30,)^(31]){ }^{[30,}{ }^{31]}. Currently, integrated devices based on 2D semiconductors necessitate high dielectric constant and wide bandgap gate insulators to reduce the gate leakage and enhance the overall gate controllability, and provide high interface quality and dielectric reliability. Moreover, the integration of traditional 3D dielectric materials often results in a significant number of dangling bonds at the interface, which can degrade the carrier mobility of semiconductor material [ 32 , 33 ] [ 32 , 33 ] ^([32,33]){ }^{[32,33]}. Achieving optimal contact between 2D semiconductor materials and metal electrodes at the nanoscale remains a substantial challenge. Specifically, Fermi level pinning and pronounced Schottky barriers adversely impact the electrical properties and contact resistance of 2D semiconductor materials, thus hindering their industrial applications [ 34 , 35 ] [ 34 , 35 ] ^([34,35]){ }^{[34,35]}. In this review, we focus on 2D transistors, and presenting the latest advancements in the growth of 2D semiconductor materials and 2D dielectric materials. We then explore strategies for enhancing the contact between 2D semiconductors and metal electrodes. Subsequently, we highlight the progress of 2D transistors in large-scale integration and advanced applications. Finally, we offer conclusions and outlooks on 2D transistors.
二维晶体管持续发展,但仍有许多挑战需要解决。对于后摩尔时代的二维半导体材料晶体管技术,高质量、大面积二维半导体材料的生长是关键方面 [ 28 , 29 ] [ 28 , 29 ] ^([28,29]){ }^{[28,29]} 。然而,二维材料在生长过程中表现出随机分布的成核点和反平行岛屿之间的等效性。此外,其生长模式极易受到温度梯度和气流等多种因素的扰动,这显著阻碍了高质量薄膜的连续生长 [ 30 , 31 ] [ 30 , 31 ] ^([30,)^(31]){ }^{[30,}{ }^{31]} 。目前,基于二维半导体的集成器件需要高介电常数和宽带隙的栅极绝缘体,以减少栅极泄漏并增强整体栅极控制能力,同时提供高界面质量和介电可靠性。此外,传统三维介电材料的集成通常会在界面产生大量悬挂键,可能降低半导体材料的载流子迁移率 [ 32 , 33 ] [ 32 , 33 ] ^([32,33]){ }^{[32,33]} 。 在纳米尺度上实现二维半导体材料与金属电极之间的最佳接触仍然是一个重大挑战。具体来说,费米能级钉扎和显著的肖特基势垒对二维半导体材料的电学性能和接触电阻产生不利影响,从而阻碍了其工业应用 [ 34 , 35 ] [ 34 , 35 ] ^([34,35]){ }^{[34,35]} 。在本综述中,我们聚焦于二维晶体管,介绍二维半导体材料和二维介电材料生长的最新进展。随后,我们探讨了增强二维半导体与金属电极接触的策略。接着,我们重点介绍了二维晶体管在大规模集成和先进应用中的进展。最后,我们对二维晶体管的发展进行了总结和展望。

2. Synthesis of channel materials
2. 通道材料的合成

2.1 Unidirectional alignment epitaxial growth via substrate engineering
2.1 通过基底工程实现单向排列外延生长

Based on the mechanistic analysis of the chemical vapor deposition (CVD) process, in which the thermodynamic driving force is regulated by the temperature field, the enhanced atomic diffusion capability can significantly improve the growth rate at higher growth temperatures. The kinetic limitation mainly originates from the
基于对化学气相沉积(CVD)工艺的机理分析,其中热力学驱动力由温度场调控,增强的原子扩散能力可以显著提高较高生长温度下的生长速率。动力学限制主要来源于

substrate surface interface characteristics, which is manifested as the competitive relationship between the mean free range of adsorbed atoms ( λ ) ( λ ) (lambda)(\lambda) and the substrate step spacing ( L ): when λ > L λ > L lambda > L\lambda>\mathrm{L}, most adsorbed atoms desorb before migrating to the step edge, resulting in a significant reduction of the growth rate; when λ < L λ < L lambda < L\lambda<\mathrm{L}, the adsorbed atoms can efficiently arrive at the edge of the nucleus and realize the growth rate close to the theoretical limit. It is worth noting that under fixed thermodynamic parameters, λ λ lambda\lambda and L are completely determined by the substrate properties, and thus the interfacial interactions between the substrate and precursor atoms become a key parameter in regulating the nucleation kinetics. Based on this, substrate engineering has been shown to be an effective strategy to achieve controlled preparation of 2D materials at the water level, especially for single-crystal thin film growth by constructing seamless splicing structures. In this section, we take atomic surface smoothness, lattice matching, and space group symmetry as typical systems, and systematically review the research progress of substrate engineering in wafer-scale 2D materials preparation in recent years, and deeply analyze the design principles and implementation paths of different substrate engineering strategies, from the atomic-scale interface regulation mechanism to the macroscopic-scale experimental validation [ 36 38 ] [ 36 38 ] ^([36-38]){ }^{[36-38]}.
基底表面界面特性表现为吸附原子平均自由程 ( λ ) ( λ ) (lambda)(\lambda) 与基底台阶间距 (L) 之间的竞争关系:当 λ > L λ > L lambda > L\lambda>\mathrm{L} 时,大多数吸附原子在迁移到台阶边缘之前脱附,导致生长速率显著降低;当 λ < L λ < L lambda < L\lambda<\mathrm{L} 时,吸附原子能够高效到达成核边缘,实现接近理论极限的生长速率。值得注意的是,在固定热力学参数下, λ λ lambda\lambda 和 L 完全由基底性质决定,因此基底与前驱体原子之间的界面相互作用成为调控成核动力学的关键参数。基于此,基底工程已被证明是一种实现二维材料水准受控制备的有效策略,尤其是通过构建无缝拼接结构实现单晶薄膜生长。 在本节中,我们以原子表面光滑度、晶格匹配和空间群对称性作为典型体系,系统回顾了近年来基底工程在晶圆级二维材料制备中的研究进展,深入分析了不同基底工程策略的设计原则和实施路径,从原子尺度的界面调控机制到宏观尺度的实验验证 [ 36 38 ] [ 36 38 ] ^([36-38]){ }^{[36-38]}
While CVD technology on transition metal-catalyzed substrates allows for the controlled preparation of wafer-scale single-crystal 2D materials, its industrial application requires the transfer of 2D materials to dielectric substrates for electrical functionalization. However, the mechanical transfer process inevitably introduces defects such as folds, cracks and interfacial contamination, leading to significant degradation of electrical properties. Therefore, the development of direct epitaxy of 2D materials on insulating substrates has become a key path to break through the bottleneck of industrialization. The Fang team has successfully realized the highly oriented epitaxial growth of 2D semiconductor single crystals on c-surface sapphire substrates (Figure 1a). By rotating the crystal orientation by 30 30 30^(@)30^{\circ}, the compressive and tensile stresses are effectively regulated, and strain tolerance is realized, resulting in a controlled interfacial strain between the heterogeneous epitaxial single crystal with different lattice constants and the sapphire substrate. Photodetectors based on this
虽然基于过渡金属催化基底的 CVD 技术可以实现晶圆级单晶二维材料的可控制备,但其工业应用需要将二维材料转移到介电基底上以实现电功能化。然而,机械转移过程不可避免地引入折叠、裂纹和界面污染等缺陷,导致电学性能显著下降。因此,开发二维材料在绝缘基底上的直接外延成为突破工业化瓶颈的关键路径。Fang 团队成功实现了二维半导体单晶在 c 面蓝宝石基底上的高度定向外延生长(图 1a)。通过将晶体取向旋转 30 30 30^(@)30^{\circ} ,有效调节了压缩和拉伸应力,实现了应变容忍,从而控制了具有不同晶格常数的异质外延单晶与蓝宝石基底之间的界面应变。基于此的光电探测器

heterogeneous epitaxial material show better photodetection performance than non-epitaxial devices [ 39 ] [ 39 ] ^([39]){ }^{[39]}. A similar strategy has also been validated in the system of TMDCs: Lo’s group utilized the ultra-low surface energy property of molten glass to successfully prepare 2.5 mm -scale single-crystal MoSe 2 MoSe 2 MoSe_(2)\mathrm{MoSe}_{2} triangular flakes (Figure 1b), which showed a 40 % 40 % 40%40 \% enhancement of photoluminescence intensity compared with mechanically exfoliated samples [ 40 ] [ 40 ] ^([40]){ }^{[40]}. liu et al. proposed a double-coupled synergistic tuning of the two-dimensional material with the intra-insulating substrate surface by van der Waals’ coupling interaction and step interactions in a new mechanism of dual-coupling synergistic regulation, realizing the epitaxial preparation of 2 -inch single-layer monocrystalline WS 2 [ 41 ] WS 2 [ 41 ] WS_(2)^([41])\mathrm{WS}_{2}{ }^{[41]}. kong et al. proposed a new strategy to realize the epitaxial growth of 2D semiconductor monocrystalline wafers represented by molybdenum disulfide on commercial insulator substrates, which provides a solid material foundation for the large-scale industrial application of 2D semiconductor-based semiconductors [ 42 ] [ 42 ] ^([42]){ }^{[42]}. These advances demonstrate that insulator substrate engineering offers innovative solutions for device-level integration of 2D materials with both interface quality and process compatibility.
异质外延材料表现出比非外延器件更好的光电探测性能 [ 39 ] [ 39 ] ^([39]){ }^{[39]} 。类似的策略也在 TMDCs 系统中得到了验证:Lo 团队利用熔融玻璃的超低表面能成功制备了 2.5 mm 级单晶 MoSe 2 MoSe 2 MoSe_(2)\mathrm{MoSe}_{2} 三角形薄片(图 1b),其光致发光强度相比机械剥离样品表现出 40 % 40 % 40%40 \% 倍的增强 [ 40 ] [ 40 ] ^([40]){ }^{[40]} 。刘等人提出了一种通过范德华耦合相互作用和阶梯相互作用对二维材料与绝缘基底表面进行双耦合协同调控的新机制,实现了 2 英寸单层单晶 WS 2 [ 41 ] WS 2 [ 41 ] WS_(2)^([41])\mathrm{WS}_{2}{ }^{[41]} 的外延制备。孔等人提出了一种新策略,实现了以二硫化钼为代表的二维半导体单晶晶圆在商业绝缘基底上的外延生长,为基于二维半导体的半导体器件的大规模工业应用提供了坚实的材料基础 [ 42 ] [ 42 ] ^([42]){ }^{[42]} 。 这些进展表明,绝缘体基板工程为二维材料的器件级集成提供了创新的解决方案,兼顾了界面质量和工艺兼容性。
The epitaxial growth mechanisms of 2D materials and 3D bulk thin films are fundamentally different, although both are based on heterogeneous nucleation on the substrate surface. In the 3D thin-film system, the material is strongly coupled to the substrate through oriented chemical bonding, and the epitaxy process has stringent requirements for lattice symmetry matching and lattice constant agreement (typically Δ a / a < 5 % ) Δ a / a < 5 % ) Deltaa//a < 5%)\Delta \mathrm{a} / \mathrm{a}<5 \%). In contrast, the growth mechanism of 2D layered materials exhibits unique cross-dimensional properties: atoms within the layers build a stable 2D lattice through strong covalent/ionic bonds (binding energy 2 8 eV / 2 8 eV / ∼2-8eV//\sim 2-8 \mathrm{eV} / atom), while interlayer and layer-substrate interactions are dominated by weak van der Waals (vdW) forces, which are 1-2 orders of magnitude lower than the energy scale of chemical bonds. The energy scale is 1-2 orders of magnitude lower than that of chemical bonding. This weak interfacial coupling property allows the epitaxial growth of 2D materials to break through the rigid constraints of conventional lattice matching and exhibit significant non-strict lattice matching dependence [ 43 45 ] [ 43 45 ] ^([43-45]){ }^{[43-45]}. The Bi 2 Te 3 Bi 2 Te 3 Bi_(2)Te_(3)\mathrm{Bi}_{2} \mathrm{Te}_{3} can even form
二维材料和三维体薄膜的外延生长机制从根本上不同,尽管两者都基于基底表面的异质成核。在三维薄膜系统中,材料通过定向化学键与基底强耦合,外延过程对晶格对称性匹配和晶格常数一致性有严格要求(通常为 Δ a / a < 5 % ) Δ a / a < 5 % ) Deltaa//a < 5%)\Delta \mathrm{a} / \mathrm{a}<5 \%) )。相比之下,二维层状材料的生长机制表现出独特的跨维性质:层内原子通过强共价/离子键(结合能 2 8 eV / 2 8 eV / ∼2-8eV//\sim 2-8 \mathrm{eV} / 原子)构建稳定的二维晶格,而层间及层-基底相互作用主要由弱范德华(vdW)力主导,其能量尺度比化学键低 1-2 个数量级。这种弱界面耦合特性使二维材料的外延生长能够突破传统晶格匹配的刚性限制,表现出显著的非严格晶格匹配依赖性 [ 43 45 ] [ 43 45 ] ^([43-45]){ }^{[43-45]} Bi 2 Te 3 Bi 2 Te 3 Bi_(2)Te_(3)\mathrm{Bi}_{2} \mathrm{Te}_{3} 甚至可以形成

high-quality heterogeneous epitaxial structures on FeTe substrates with very different lattice structures (Figure 1c) [ 46 ] [ 46 ] ^([46]){ }^{[46]}. Controlling the thickness of two-dimensional materials is crucial for regulating the properties of two-dimensional materials, so the ability to grow large-area two-dimensional channel materials with different layers is of great significance for the development of two-dimensional semiconductors, and most of the current growth methods are unable to achieve stable growth of large-area, multilayer two-dimensional channel materials. Liu et al. proposed an edge-aligned double-layer nucleation strategy based on an edge nucleation mechanism. By employing a CVD method, they achieved uniform nucleation and epitaxial growth of bilayer MoS 2 MoS 2 MoS_(2)\mathrm{MoS}_{2} on a sapphire substrate with step height precisely controlled through high-temperature annealing. Furthermore, compared to traditional single-layer MoS 2 MoS 2 MoS_(2)\mathrm{MoS}_{2} thin films, the bilayer MoS 2 MoS 2 MoS_(2)\mathrm{MoS}_{2} devices synthesized by this method exhibit significantly enhanced mobility and improved short-channel current density, demonstrating superior performance characteristics [ 47 ] [ 47 ] ^([47]){ }^{[47]}. It is worth noting that although the energy scale of the vdW interaction is low, its spatial distribution characteristics are decisive for the growth morphology of the 2D material: by tuning the lattice symmetry, step density, and other parameters on the substrate surface, the crystal orientation, domain size, and layer distribution of the 2D epitaxial layer can be precisely manipulated. This weak coupling-strong regulation dialectic provides a unique physical basis for heterogeneous integration of 2D materials.
在晶格结构差异很大的 FeTe 基底上实现高质量的异质外延结构(图 1c) [ 46 ] [ 46 ] ^([46]){ }^{[46]} 。控制二维材料的厚度对于调节二维材料的性质至关重要,因此能够生长不同层数的大面积二维通道材料对于二维半导体的发展具有重要意义,而目前大多数生长方法无法实现大面积、多层二维通道材料的稳定生长。Liu 等人提出了一种基于边缘成核机制的边缘对齐双层成核策略。通过采用 CVD 方法,他们在通过高温退火精确控制台阶高度的蓝宝石基底上实现了双层 MoS 2 MoS 2 MoS_(2)\mathrm{MoS}_{2} 的均匀成核和外延生长。此外,与传统的单层 MoS 2 MoS 2 MoS_(2)\mathrm{MoS}_{2} 薄膜相比,该方法合成的双层 MoS 2 MoS 2 MoS_(2)\mathrm{MoS}_{2} 器件表现出显著增强的迁移率和改进的短沟道电流密度,展示了优越的性能特征 [ 47 ] [ 47 ] ^([47]){ }^{[47]} 。 值得注意的是,尽管范德华相互作用的能量尺度较低,但其空间分布特性决定了二维材料的生长形貌:通过调节基底表面的晶格对称性、台阶密度等参数,可以精确控制二维外延层的晶体取向、晶域大小和层分布。这种弱耦合-强调控的辩证关系为二维材料的异质集成提供了独特的物理基础。

Figure 1. Two-dimensional material epitaxial growth technology based on precise regulation of nucleation orientation, interface strain, and defect density. a) Schematic illustration of the procedure to fabricate Cs 3 Bi 2 X 9 [ 39 ] Cs 3 Bi 2 X 9 [ 39 ] Cs_(3)Bi_(2)X_(9)^([39])\mathrm{Cs}_{3} \mathrm{Bi}_{2} \mathrm{X}_{9}{ }^{[39]}. b) Synthesis process and morphology of MoSe 2 MoSe 2 MoSe_(2)\mathrm{MoSe}_{2} monolayers. Scheme showing CVD process for the synthesis of MoSe 2 MoSe 2 MoSe_(2)\mathrm{MoSe}_{2} crystalson molten glass. Photograph of MoSe 2 MoSe 2 MoSe_(2)\mathrm{MoSe}_{2} crystals grown on moltenglass [ 40 ] [ 40 ] ^([40]){ }^{[40]}. c) Scanning transmission electron microscope micrographs of a Bi 2 Te 3 / FeTe Bi 2 Te 3 / FeTe Bi_(2)Te_(3)//FeTe\mathrm{Bi}_{2} \mathrm{Te}_{3} / \mathrm{FeTe} heterostructure. HADDF image. Annular bright field image. Higher-magnification HADDF image shows atomically sharp interface between Bi 2 Te 3 Bi 2 Te 3 Bi_(2)Te_(3)\mathrm{Bi}_{2} \mathrm{Te}_{3} and FeTe [ 46 ] FeTe [ 46 ] FeTe^([46])\mathrm{FeTe}^{[46]}. d) Thermodynamic analysis of monolayer and bilayer MoS 2 MoS 2 MoS_(2)\mathrm{MoS}_{2} growth in C-surface sapphire, as well as optical maps of large-area growth of monolayers and bilayers of MoS 2 MoS 2 MoS_(2)\mathrm{MoS}_{2} and optical maps of the initial nucleation stage of bilayer MoS 2 MoS 2 MoS_(2)\mathrm{MoS}_{2} domains with Atomic Force Microscope (AFM) images [ 47 ] [ 47 ] ^([47]){ }^{[47]}. a) Reproduced with permission [ 39 ] [ 39 ] ^([39]){ }^{[39]}.
图 1. 基于对成核取向、界面应变和缺陷密度的精确调控的二维材料外延生长技术。a) 制备 Cs 3 Bi 2 X 9 [ 39 ] Cs 3 Bi 2 X 9 [ 39 ] Cs_(3)Bi_(2)X_(9)^([39])\mathrm{Cs}_{3} \mathrm{Bi}_{2} \mathrm{X}_{9}{ }^{[39]} 的工艺示意图。b) MoSe 2 MoSe 2 MoSe_(2)\mathrm{MoSe}_{2} 单层的合成过程及形貌。展示在熔融玻璃上合成 MoSe 2 MoSe 2 MoSe_(2)\mathrm{MoSe}_{2} 晶体的 CVD 工艺示意图。 MoSe 2 MoSe 2 MoSe_(2)\mathrm{MoSe}_{2} 晶体在熔融玻璃 [ 40 ] [ 40 ] ^([40]){ }^{[40]} 上的照片。c) Bi 2 Te 3 / FeTe Bi 2 Te 3 / FeTe Bi_(2)Te_(3)//FeTe\mathrm{Bi}_{2} \mathrm{Te}_{3} / \mathrm{FeTe} 异质结构的扫描透射电子显微镜图像。HADDF 图像。环形明场图像。高倍放大 HADDF 图像显示 Bi 2 Te 3 Bi 2 Te 3 Bi_(2)Te_(3)\mathrm{Bi}_{2} \mathrm{Te}_{3} FeTe [ 46 ] FeTe [ 46 ] FeTe^([46])\mathrm{FeTe}^{[46]} 之间的原子级锐利界面。d) C 面蓝宝石上单层和双层 MoS 2 MoS 2 MoS_(2)\mathrm{MoS}_{2} 生长的热力学分析,以及 MoS 2 MoS 2 MoS_(2)\mathrm{MoS}_{2} 单层和双层大面积生长的光学图谱和双层 MoS 2 MoS 2 MoS_(2)\mathrm{MoS}_{2} 域初始成核阶段的光学图谱及原子力显微镜(AFM)图像 [ 47 ] [ 47 ] ^([47]){ }^{[47]} 。a) 经许可转载 [ 39 ] [ 39 ] ^([39]){ }^{[39]}
Although the heterogeneous epitaxial growth of 2D materials can be realized in a
尽管二维材料的异质外延生长可以实现于一个...

variety of substrate systems, the evolution of its crystallographic orientation is strictly limited by the symmetry matching principle at the substrate-film interface. Analyzed from the thermodynamic perspective of interfacial energy optimization, the 2D epitaxial process is essentially a dynamic selection mechanism of the coupling of adsorbed atoms with the potential field on the substrate surface, and the 2D crystal core edges tend to extend along the direction of low interfacial energies determined by the substrate lattice symmetry, resulting in the formation of a stable domain structure with a specific crystallographic orientation [ 48 ] [ 48 ] ^([48]){ }^{[48]}. Based on the principle of lattice symmetry subgroup matching, Ma demonstrates a versatile method for the growth of dense, aligned arrays of MoS 2 MoS 2 MoS_(2)\mathrm{MoS}_{2} nanoribbons by CVD on anisotropic sapphire substrates without the need for customized surface steps. This method is capable of synthesizing nanoribbons with widths below 10 nm and longitudinal axes parallel to the sawtooth direction, and can be extended to the growth of WS 2 WS 2 WS_(2)\mathrm{WS}_{2} nanoribbons and MoS 2 WS 2 MoS 2 WS 2 MoS_(2)-WS_(2)\mathrm{MoS}_{2}-\mathrm{WS}_{2} heterogeneous nanoribbons, as shown in Figure 2a [ 49 ] [ 49 ] ^([49]){ }^{[49]}. The mechanism is also validated in the tetragonal symmetric system, where the lattice orientation of the quadruple-symmetric Bi 2 O 2 Se Bi 2 O 2 Se Bi_(2)O_(2)Se\mathrm{Bi}_{2} \mathrm{O}_{2} \mathrm{Se} film is confined to be aligned along the [100]/[010] direction of the substrate when the film is grown on a cubic-symmetric SrTiO 3 ( 001 ) SrTiO 3 ( 001 ) SrTiO_(3)(001)\mathrm{SrTiO}_{3}(001) substrate, as shown in Figure 2b. This stems from the uniaxial orientation-locking effect due to the interfacial energy anisotropy of tetragonal-phase films with cubic substrates [ 50 ] [ 50 ] ^([50]){ }^{[50]}. It is worth noting that although the symmetry matching strategy exhibits universality in centrosymmetric material systems, the epitaxial orientation regulation mechanism for complex interfacial systems with asymmetric surface reconstruction or mirror-symmetry breaking requires further decoupling of the nonlinear correlation between the interfacial potential field distribution and the dynamic growth process.
在各种基底系统中,其晶体取向的演变严格受限于基底-薄膜界面处的对称性匹配原则。从界面能优化的热力学角度分析,二维外延过程本质上是吸附原子与基底表面势场耦合的动态选择机制,二维晶体核边缘倾向于沿基底晶格对称性决定的低界面能方向延伸,形成具有特定晶体取向的稳定晶域结构 [ 48 ] [ 48 ] ^([48]){ }^{[48]} 。基于晶格对称子群匹配原理,Ma 展示了一种通过 CVD 在各向异性蓝宝石基底上生长致密、排列整齐的 MoS 2 MoS 2 MoS_(2)\mathrm{MoS}_{2} 纳米带阵列的通用方法,无需定制表面台阶。该方法能够合成宽度低于 10 纳米且纵轴平行于锯齿方向的纳米带,并可扩展至 WS 2 WS 2 WS_(2)\mathrm{WS}_{2} 纳米带和 MoS 2 WS 2 MoS 2 WS 2 MoS_(2)-WS_(2)\mathrm{MoS}_{2}-\mathrm{WS}_{2} 异质纳米带的生长,如图 2a 所示 [ 49 ] [ 49 ] ^([49]){ }^{[49]} 。 该机制也在四方对称系统中得到了验证,当薄膜生长在立方对称的 SrTiO 3 ( 001 ) SrTiO 3 ( 001 ) SrTiO_(3)(001)\mathrm{SrTiO}_{3}(001) 基底上时,四重对称 Bi 2 O 2 Se Bi 2 O 2 Se Bi_(2)O_(2)Se\mathrm{Bi}_{2} \mathrm{O}_{2} \mathrm{Se} 薄膜的晶格取向被限制为沿基底的[100]/[010]方向排列,如图 2b 所示。这源于四方相薄膜与立方基底界面能各向异性引起的单轴取向锁定效应 [ 50 ] [ 50 ] ^([50]){ }^{[50]} 。值得注意的是,尽管对称中心材料系统中的对称匹配策略表现出普适性,但对于具有非对称表面重构或镜像对称破缺的复杂界面系统,其外延取向调控机制仍需进一步解耦界面势场分布与动态生长过程之间的非线性关联。
Preparation of TMDCs with non-centrosymmetric lattice structures faces the key challenge of compatibility between symmetric substrates and catalytic substrates, which has prompted researchers to explore novel substrate design strategies from an energy-modulation perspective. Crystal nucleation tends to occur at step edges rather than flat surfaces, which stems from the fact that step sites have the lowest interface
制备具有非中心对称晶格结构的 TMDCs 面临的关键挑战是对称基底与催化基底之间的兼容性,这促使研究人员从能量调控的角度探索新型基底设计策略。晶体成核倾向于发生在阶梯边缘而非平坦表面,这源于阶梯位点具有最低的界面能。

formation energy. By designing and processing substrates with controllable step structures, the unidirectional orientation of two-dimensional crystal domains can be effectively guided. kim et al. obtained Au (111), (110), and (100) crystal faces, providing a universal platform for the growth of materials with different symmetries [ 51 ] [ 51 ] ^([51]){ }^{[51]}. Liu et al. grew wafer-scale single-crystal monolayers of WS 2 WS 2 WS_(2)\mathrm{WS}_{2} with dual symmetry as shown in Figure 2 c [ 41 ] 2 c [ 41 ] 2c^([41])2 \mathrm{c}^{[41]}. Wang et al. optimized the direction of miscutting of c-face sapphire to the a-axis, and successfully grew 2-inch single-crystalline MoS 2 MoS 2 MoS_(2)\mathrm{MoS}_{2} thin films, whose crystalline quality and electrical properties meet the standards for industrial applications, as shown in Figure 2 d [ 52 ] 2 d [ 52 ] 2d^([52])2 \mathrm{~d}^{[52]}. Together, these results show that the step-edge-induced nucleation control and symmetry-breaking design based on step edges can break through the limitations of traditional centrosymmetric substrates on the intrinsic physical properties of materials.
形成能。通过设计和加工具有可控阶梯结构的衬底,可以有效引导二维晶体域的单向取向。Kim 等人获得了 Au (111)、(110) 和 (100) 晶面,提供了一个适用于不同对称性材料生长的通用平台 [ 51 ] [ 51 ] ^([51]){ }^{[51]} 。Liu 等人如图 2 c [ 41 ] 2 c [ 41 ] 2c^([41])2 \mathrm{c}^{[41]} 所示,生长了具有双重对称性的 WS 2 WS 2 WS_(2)\mathrm{WS}_{2} 晶圆级单晶单层。Wang 等人优化了 c 面蓝宝石相对于 a 轴的错切方向,成功生长了 2 英寸单晶 MoS 2 MoS 2 MoS_(2)\mathrm{MoS}_{2} 薄膜,其晶体质量和电学性能达到工业应用标准,如图 2 d [ 52 ] 2 d [ 52 ] 2d^([52])2 \mathrm{~d}^{[52]} 所示。这些结果表明,基于阶梯边缘的阶梯边缘诱导成核控制和对称性破缺设计,可以突破传统中心对称衬底对材料内在物理性质的限制。
This paper systematically describes the key role of substrate-assisted growth in CVD technology for the controlled preparation of two-dimensional materials at the wafer level. These advances not only reveal the mechanisms of substrate-material interface interactions on the regulation of nucleation kinetics at the atomic scale, but also promote the device-level integration of 2D semiconductors with topological insulators and other materials at the macroscopic scale. Through the synergistic thermodynamic optimal orientation and kinetic path design, substrate engineering provides innovative solutions for breaking through the mechanical transfer defects and realizing the large-scale preparation of high-performance 2D materials, which lays the foundation for its application in the future electronics and optoelectronics fields.
本文系统地描述了基底辅助生长在化学气相沉积(CVD)技术中对二维材料晶圆级可控制备的关键作用。这些进展不仅揭示了基底-材料界面相互作用在原子尺度上调控成核动力学的机制,还促进了二维半导体与拓扑绝缘体及其他材料在宏观尺度上的器件级集成。通过协同的热力学最优取向和动力学路径设计,基底工程为突破机械转移缺陷和实现高性能二维材料的大规模制备提供了创新解决方案,为其在未来电子学和光电子学领域的应用奠定了基础。

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(b)  (b)

(d)  (d)
Figure 2. Two-dimensional material epitaxial growth technology via substrate symmetry matching, interface energy optimization, and symmetry-breaking design. a) Lattice-guided growth of MoS 2 MoS 2 MoS_(2)\mathrm{MoS}_{2} NRs. Model of the aligned MoS 2 MoS 2 MoS_(2)\mathrm{MoS}_{2} NRs on a-sapphire. scanning electron microscope (SEM) image of the as-grown NRs. Distribution of the width versus the length of 150 150 ∼150\sim 150 NRs, measured by SEM. The color of the markers indicates the aspect ratio (L/W) of the given NR. AFM image of the as-grown NRs. High magnification AFM images of isolated narrow NRs, with widths down to 24 24 ∼24\sim 24 nm . Scale bar, 500 nm . SEM image [ 49 ] [ 49 ] ^([49]){ }^{[49]}. b) Characterization of single-crystal Cu (110) obtained by annealing an industrial Cu foil [ 53 ] [ 53 ] ^([53]){ }^{[53]}. c) Growth and characterization of single-crystal WS 2 WS 2 WS_(2)\mathrm{WS}_{2} monolayer on vicinal a-plane sapphire [ 41 ] [ 41 ] ^([41]){ }^{[41]}. d) Sapphire (0001) substrate and epitaxial relationship. Four possible edge configurations during the nucleation stage on the C / A C / A C//A\mathrm{C} / \mathrm{A} and C / M C / M C//M\mathrm{C} / \mathrm{M} substrates. Inset: AFM image of a sample at the early growth stage, showing that the nucleation is along the step edges. Scale bar, 500 nm [ 52 ] 500 nm [ 52 ] 500nm^([52])500 \mathrm{~nm}^{[52]}.
图 2. 通过基底对称匹配、界面能量优化和破对称设计实现的二维材料外延生长技术。a) MoS 2 MoS 2 MoS_(2)\mathrm{MoS}_{2} 纳米线的晶格引导生长。在 a-蓝宝石上的对齐 MoS 2 MoS 2 MoS_(2)\mathrm{MoS}_{2} 纳米线模型。生长后纳米线的扫描电子显微镜(SEM)图像。通过 SEM 测量的 150 150 ∼150\sim 150 纳米线宽度与长度的分布。标记颜色表示给定纳米线的长宽比(L/W)。生长后纳米线的原子力显微镜(AFM)图像。孤立窄纳米线的高倍 AFM 图像,宽度低至 24 24 ∼24\sim 24 纳米。比例尺,500 纳米。SEM 图像 [ 49 ] [ 49 ] ^([49]){ }^{[49]} 。b) 通过退火工业铜箔获得的单晶 Cu(110)表征 [ 53 ] [ 53 ] ^([53]){ }^{[53]} 。c) 在斜切 a 面蓝宝石上生长和表征单晶 WS 2 WS 2 WS_(2)\mathrm{WS}_{2} 单层 [ 41 ] [ 41 ] ^([41]){ }^{[41]} 。d) 蓝宝石(0001)基底及外延关系。成核阶段在 C / A C / A C//A\mathrm{C} / \mathrm{A} C / M C / M C//M\mathrm{C} / \mathrm{M} 基底上的四种可能边缘构型。插图:早期生长阶段样品的 AFM 图像,显示成核沿阶梯边缘进行。比例尺, 500 nm [ 52 ] 500 nm [ 52 ] 500nm^([52])500 \mathrm{~nm}^{[52]}

2.2 Seed-induced epitaxy growth
2.2 种子诱导外延生长

Although step-guided epitaxy growth provides a promising approach for the synthesis of wafer-scale single-crystalline 2D materials with a single orientation, the need for meticulous substrate and inevitable transfer process pose challenges for
尽管阶梯引导外延生长为合成具有单一取向的晶圆级单晶二维材料提供了一种有前景的方法,但对基底的精细处理和不可避免的转移过程带来了挑战

commercial integrate circuits. To overcome these problems, a seed assisted technique was used for homogeneous epitaxial growth of large area 2D materials [ 54 ] [ 54 ] ^([54]){ }^{[54]}. Xu et al. successfully prepared 1 -inch single crystal 2 H MoTe 2 2 H MoTe 2 2H-MoTe_(2)2 \mathrm{H}-\mathrm{MoTe}_{2} films by pre-implanting small area single crystal 2 H MoTe 2 2 H MoTe 2 2H-MoTe_(2)2 \mathrm{H}-\mathrm{MoTe}_{2} seeds on the surface of polycrystalline 1 T MoTe 2 [ 55 ] 1 T MoTe 2 [ 55 ] 1T^(')-MoTe_(2)^([55])1 \mathrm{~T}^{\prime}-\mathrm{MoTe}_{2}{ }^{[55]}. Figure 3a shows the schematic diagram of in-plane seed-induced epitaxy growth of wafer-scale single-crystalline 2 H MoTe 2 . Due to the abundance of Te vacancies in 1 T MoTe 2 1 T MoTe 2 1T^(')-MoTe_(2)1 \mathrm{~T}^{\prime}-\mathrm{MoTe}_{2}, the continuous introduction of external Te atoms induces the phase transition and recrystallization of MoTe 2 MoTe 2 MoTe_(2)\mathrm{MoTe}_{2} from 1 T ’ to 2 H . Meanwhile, a dense Al 2 O 3 Al 2 O 3 Al_(2)O_(3)\mathrm{Al}_{2} \mathrm{O}_{3} film covers the wafer surface, with a small hole created in the seed area as the sole channel for Te atoms, preventing the spontaneous disorderly nucleation of 2 H MoTe 2 2 H MoTe 2 2H-MoTe_(2)2 \mathrm{H}-\mathrm{MoTe}_{2} (Figure 3b). As the epitaxial growth of 2 H MoTe 2 2 H MoTe 2 2H-MoTe_(2)2 \mathrm{H}-\mathrm{MoTe}_{2} is triggered by a pre-implanted single-crystal seed as the template and the growth process does not rely on the substrate structure, large-scale device arrays can be directly fabricated on the target substrate without an additional transfer process, thereby ensuring the integrity and electrical performance of the channel material. In addition, scalable single-crystalline 2D p-type 2 H MoTe 2 2 H MoTe 2 2H-MoTe_(2)2 \mathrm{H}-\mathrm{MoTe}_{2} transistor arrays were fabricated using the similar epitaxial strategy, achieving high on-state currents ( 7.8 μ A / μ m ) ( 7.8 μ A / μ m ) (∼7.8 muA//mum)(\sim 7.8 \mu \mathrm{~A} / \mu \mathrm{m}) and on/off ratio ( 10 5 ) 10 5 (∼10^(5))\left(\sim 10^{5}\right), promoting the development of next-generation 2D electronics for both front and back-end applications [ 56 ] [ 56 ] ^([56]){ }^{[56]}. The traditional CVD preparation of large-area MoS 2 MoS 2 MoS_(2)\mathrm{MoS}_{2} typically requires prolonged processing times, posing significant barriers for industrial applications. Liu et al. have developed a novel two-dimensional Czochralski (2DCZ) growth method that enables seamless growth of centimeter-scale single-crystal MoS 2 MoS 2 MoS_(2)\mathrm{MoS}_{2} domains by constructing a two-dimensional liquid precursor film on a molten glass substrate and combining it with a rapid sulfidation process. This approach exploits the molten glass’s low nucleation barrier and surface tension to inhibit polycrystalline nucleation while promoting lateral crystallization, thereby achieving a grain-boundary-free single-crystal structure. Notably, the method achieves an ultrafast growth rate of up to 75 μ m / s 75 μ m / s 75 mum//s75 \mu \mathrm{~m} / \mathrm{s} through rapid diffusion of the liquid-phase precursor, overcoming the critical limitation of conventional techniques in terms of processing efficiency (Figure 3c,d) [ 57 ] [ 57 ] ^([57]){ }^{[57]}. Han et. al fabricated centimeter-scale 2D β 6 β 6 beta^(6)\beta^{6} - In 2 Se 3 In 2 Se 3 In_(2)Se_(3)\mathrm{In}_{2} \mathrm{Se}_{3} films
商业集成电路。为了解决这些问题,采用了种子辅助技术进行大面积二维材料的均匀外延生长 [ 54 ] [ 54 ] ^([54]){ }^{[54]} 。Xu 等人通过在多晶 1 T MoTe 2 [ 55 ] 1 T MoTe 2 [ 55 ] 1T^(')-MoTe_(2)^([55])1 \mathrm{~T}^{\prime}-\mathrm{MoTe}_{2}{ }^{[55]} 表面预植入小面积单晶 2 H MoTe 2 2 H MoTe 2 2H-MoTe_(2)2 \mathrm{H}-\mathrm{MoTe}_{2} 种子,成功制备了 1 英寸单晶 2 H MoTe 2 2 H MoTe 2 2H-MoTe_(2)2 \mathrm{H}-\mathrm{MoTe}_{2} 薄膜。图 3a 显示了晶圆级单晶 2H MoTe2 的面内种子诱导外延生长示意图。由于 1 T MoTe 2 1 T MoTe 2 1T^(')-MoTe_(2)1 \mathrm{~T}^{\prime}-\mathrm{MoTe}_{2} 中 Te 空位丰富,持续引入外部 Te 原子诱导 MoTe 2 MoTe 2 MoTe_(2)\mathrm{MoTe}_{2} 从 1T’相向 2H 相的相变和再结晶。同时,一层致密的 Al 2 O 3 Al 2 O 3 Al_(2)O_(3)\mathrm{Al}_{2} \mathrm{O}_{3} 薄膜覆盖晶圆表面,种子区域形成一个小孔作为 Te 原子的唯一通道,防止了 2 H MoTe 2 2 H MoTe 2 2H-MoTe_(2)2 \mathrm{H}-\mathrm{MoTe}_{2} 的自发无序成核(图 3b)。由于 2 H MoTe 2 2 H MoTe 2 2H-MoTe_(2)2 \mathrm{H}-\mathrm{MoTe}_{2} 的外延生长是由预植入的单晶种子作为模板触发,且生长过程不依赖于衬底结构,因此可以直接在目标衬底上制造大规模器件阵列,无需额外的转移工艺,从而保证了通道材料的完整性和电性能。 此外,利用类似的外延策略制备了可扩展的单晶二维 p 型 2 H MoTe 2 2 H MoTe 2 2H-MoTe_(2)2 \mathrm{H}-\mathrm{MoTe}_{2} 晶体管阵列,实现了高开态电流 ( 7.8 μ A / μ m ) ( 7.8 μ A / μ m ) (∼7.8 muA//mum)(\sim 7.8 \mu \mathrm{~A} / \mu \mathrm{m}) 和开关比 ( 10 5 ) 10 5 (∼10^(5))\left(\sim 10^{5}\right) ,推动了下一代二维电子器件在前端和后端应用中的发展 [ 56 ] [ 56 ] ^([56]){ }^{[56]} 。传统的 CVD 制备大面积 MoS 2 MoS 2 MoS_(2)\mathrm{MoS}_{2} 通常需要较长的处理时间,这对工业应用构成了重大障碍。Liu 等人开发了一种新颖的二维 Czochralski(2DCZ)生长方法,通过在熔融玻璃基底上构建二维液态前驱体薄膜并结合快速硫化工艺,实现了厘米级单晶 MoS 2 MoS 2 MoS_(2)\mathrm{MoS}_{2} 区域的无缝生长。该方法利用熔融玻璃的低成核势垒和表面张力抑制多晶成核,同时促进横向结晶,从而实现了无晶界的单晶结构。 值得注意的是,该方法通过液相前驱体的快速扩散,实现了高达 75 μ m / s 75 μ m / s 75 mum//s75 \mu \mathrm{~m} / \mathrm{s} 的超快生长速率,克服了传统技术在加工效率方面的关键限制(图 3c,d) [ 57 ] [ 57 ] ^([57]){ }^{[57]} 。Han 等人制造了厘米级的 2D β 6 β 6 beta^(6)\beta^{6} - In 2 Se 3 In 2 Se 3 In_(2)Se_(3)\mathrm{In}_{2} \mathrm{Se}_{3} 薄膜。

by introducing InSe seed crystals [ 58 ] [ 58 ] ^([58]){ }^{[58]}. Density functional theory (DFT) calculations reveal that when atoms are fully relaxed, the energy difference between β β beta\beta-phase and β β beta^(')\beta^{\prime}-phase monolayer In 2 Se 3 In 2 Se 3 In_(2)Se_(3)\mathrm{In}_{2} \mathrm{Se}_{3} monotonically increases with the rise in selenium vacancy concentration (Figure 3e). This indicates the β β beta^(')\beta^{\prime}-phase is more stable under selenium-deficient conditions. Consequently, at elevated temperatures, β β beta\beta-InSe acts as a seed crystal, facilitating the nucleation of β In 2 Se 3 β In 2 Se 3 beta^(')-In_(2)Se_(3)\beta^{\prime}-\mathrm{In}_{2} \mathrm{Se}_{3}. Benefited from controllable seed-induced epitaxy growth and phase-transition transfer methods, large -area synthesis of three phases of In 2 Se 3 In 2 Se 3 In_(2)Se_(3)\mathrm{In}_{2} \mathrm{Se}_{3} was achieved (Figure 3f), rendering 2D In 2 Se 3 In 2 Se 3 In_(2)Se_(3)\operatorname{In}_{2} \mathrm{Se}_{3} a promising candidate for memory transistors and heterophase junctions. Due to independence from highly modulated substrates, seed-induced epitaxy growth provides a promising way for integration of 2D materials with other function materials or architectures for the fabrication of integrated devices. In 2022, Pan et. al achieved a direct synthesis of heteroepitaxy of single-crystal 2 D MoTe 2 on highly lattice-mismatched substrates and 3D architectures [ 59 ] [ 59 ] ^([59]){ }^{[59]} (Figure 3g). As shown in Figure 1 h , 2 H MoTe 2 1 h , 2 H MoTe 2 1h,2H-MoTe_(2)1 \mathrm{~h}, 2 \mathrm{H}-\mathrm{MoTe}_{2} single-crystal domains nucleated in the continuous polycrystalline 1 T ’ background and grew through in-plane seed-induced epitaxy process and across the 3D fin structures. Meanwhile, a wafer-scale p-n heterojunction array was fabricated on an n-type silicon substrate (Figure 3i), showing spatial uniformity of the electrical performance of the devices on a large scale.
通过引入 InSe 种子晶体 [ 58 ] [ 58 ] ^([58]){ }^{[58]} 。密度泛函理论(DFT)计算表明,当原子完全弛豫时, β β beta\beta 相和 β β beta^(')\beta^{\prime} 相单层 In 2 Se 3 In 2 Se 3 In_(2)Se_(3)\mathrm{In}_{2} \mathrm{Se}_{3} 之间的能量差随着硒空位浓度的增加单调上升(图 3e)。这表明 β β beta^(')\beta^{\prime} 相在缺硒条件下更稳定。因此,在高温下, β β beta\beta -InSe 作为种子晶体,促进了 β In 2 Se 3 β In 2 Se 3 beta^(')-In_(2)Se_(3)\beta^{\prime}-\mathrm{In}_{2} \mathrm{Se}_{3} 的成核。得益于可控的种子诱导外延生长和相变转移方法,实现了 In 2 Se 3 In 2 Se 3 In_(2)Se_(3)\mathrm{In}_{2} \mathrm{Se}_{3} 三相的大面积合成(图 3f),使二维 In 2 Se 3 In 2 Se 3 In_(2)Se_(3)\operatorname{In}_{2} \mathrm{Se}_{3} 成为存储晶体管和异相结的有前景候选材料。由于不依赖高度调制的衬底,种子诱导外延生长为二维材料与其他功能材料或结构的集成提供了有希望的途径,用于集成器件的制造。2022 年,Pan 等人实现了在高度晶格失配的衬底和三维结构 [ 59 ] [ 59 ] ^([59]){ }^{[59]} 上直接合成单晶二维 MoTe2 的异质外延(图 3g)。 如图 1 h , 2 H MoTe 2 1 h , 2 H MoTe 2 1h,2H-MoTe_(2)1 \mathrm{~h}, 2 \mathrm{H}-\mathrm{MoTe}_{2} 所示,单晶域在连续的多晶 1T'背景中成核,并通过面内种子诱导外延过程穿过三维鳍结构生长。同时,在 n 型硅衬底上制备了晶圆级 p-n 异质结阵列(图 3i),显示出器件电性能在大尺度上的空间均匀性。
Seed-induced epitaxy growth brings a platform to synthesis large-scale 2D single crystals on arbitrary substrates for CMOS integration. However, the growth dynamics are still unclear, and the types of 2D materials that can be grown by this method are still few.
种子诱导外延生长为在任意衬底上合成大规模二维单晶提供了平台,适用于 CMOS 集成。然而,生长动力学仍不清楚,且通过该方法可生长的二维材料类型仍然较少。

Figure 3. Seed-induced epitaxy growth. a) The schematic diagram for in-plane seed-induced epitaxy growth of wafer-scale single-crystalline 2 H MoTe 2 . b) Optical images of 2 H MoTe 2 seed assembled in the center of 1 T MoTe 2 1 T MoTe 2 1T^(')MoTe_(2)1 \mathrm{~T}^{\prime} \mathrm{MoTe}_{2} wafer before growth and 2 H MoTe 2 2 H MoTe 2 2HMoTe_(2)2 \mathrm{H} \mathrm{MoTe}_{2} circle centered on the seed region after intermediate growth for 2 hours. c) Schematic representation of the conventional synthesis of MOS 2 MOS 2 MOS_(2)\mathrm{MOS}_{2} by CVD and the synthesis of MoS 2 MoS 2 MoS_(2)\mathrm{MoS}_{2} by the 2 DCZ method. d) Optical map of ultrafast large-scale MoS 2 MoS 2 MoS_(2)\mathrm{MoS}_{2} film growth. e) Sketch map of the role of InSe seed in the phase-control growth process. f) Photograph of large-area In 2 Se 3 In 2 Se 3 In_(2)Se_(3)\operatorname{In}_{2} \mathrm{Se}_{3} films of β , β β , β beta,beta^(')\beta, \beta^{\prime} and α α alpha\alpha phases. g) Schematic diagrams of an integrated optoelectronic chip by direct 2 D 2 H MoTe 2 2 D 2 H MoTe 2 2D2H-MoTe_(2)2 \mathrm{D} 2 \mathrm{H}-\mathrm{MoTe}_{2} synthesis on planar and 3D architecture. h) Time-evolution optical images of 2 H MoTe 2 2 H MoTe 2 2H-MoTe_(2)2 \mathrm{H}-\mathrm{MoTe}_{2} single-crystal domains grown on 3D fin architectures. i) Photograph and optical image of the wafer-scale 2 H MoTe 2 / Si p n 2 H MoTe 2 / Si p n 2H-MoTe_(2)//Sip-n2 \mathrm{H}-\mathrm{MoTe}_{2} / \mathrm{Si} \mathrm{p}-\mathrm{n} heterojunction array. a,b) Reproduced with permission [ 55 ] [ 55 ] ^([55]){ }^{[55]} Copyright 2021, The American Association for the Advancement of Science. c,d) Reproduced with permission [ 57 ] [ 57 ] ^([57]){ }^{[57]}. Copyright 2022, Springer Nature. e,f)
图 3. 种子诱导外延生长。a) 晶圆级单晶 2H MoTe2 的面内种子诱导外延生长示意图。b) 生长前组装在 1 T MoTe 2 1 T MoTe 2 1T^(')MoTe_(2)1 \mathrm{~T}^{\prime} \mathrm{MoTe}_{2} 晶圆中心的 2H MoTe2 种子光学图像及中间生长 2 小时后以种子区域为中心的 2 H MoTe 2 2 H MoTe 2 2HMoTe_(2)2 \mathrm{H} \mathrm{MoTe}_{2} 圆圈光学图像。c) 传统 CVD 合成 MOS 2 MOS 2 MOS_(2)\mathrm{MOS}_{2} 和 2DCZ 方法合成 MoS 2 MoS 2 MoS_(2)\mathrm{MoS}_{2} 的示意图。d) 超快大规模 MoS 2 MoS 2 MoS_(2)\mathrm{MoS}_{2} 薄膜生长的光学图。e) InSe 种子在相位控制生长过程中的作用示意图。f) β , β β , β beta,beta^(')\beta, \beta^{\prime} α α alpha\alpha 相大面积 In 2 Se 3 In 2 Se 3 In_(2)Se_(3)\operatorname{In}_{2} \mathrm{Se}_{3} 薄膜照片。g) 通过直接 2 D 2 H MoTe 2 2 D 2 H MoTe 2 2D2H-MoTe_(2)2 \mathrm{D} 2 \mathrm{H}-\mathrm{MoTe}_{2} 合成在平面和 3D 结构上的集成光电子芯片示意图。h) 在 3D 鳍结构上生长的 2 H MoTe 2 2 H MoTe 2 2H-MoTe_(2)2 \mathrm{H}-\mathrm{MoTe}_{2} 单晶域的时间演化光学图像。i) 晶圆级 2 H MoTe 2 / Si p n 2 H MoTe 2 / Si p n 2H-MoTe_(2)//Sip-n2 \mathrm{H}-\mathrm{MoTe}_{2} / \mathrm{Si} \mathrm{p}-\mathrm{n} 异质结阵列的照片和光学图像。a,b) 经许可转载 [ 55 ] [ 55 ] ^([55]){ }^{[55]} ,版权 2021,美国科学促进会。c,d) 经许可转载 [ 57 ] [ 57 ] ^([57]){ }^{[57]} ,版权 2022,施普林格自然。e,f)
Reproduced with permission [ 58 ] [ 58 ] ^([58]){ }^{[58]}. Copyright 2022, Springer Nature. g-i) Reproduced with permission [ 59 ] [ 59 ] ^([59]){ }^{[59]}. Copyright 2022, Springer Nature.
经许可转载 [ 58 ] [ 58 ] ^([58]){ }^{[58]} 。版权所有 2022,施普林格自然。g-i) 经许可转载 [ 59 ] [ 59 ] ^([59]){ }^{[59]} 。版权所有 2022,施普林格自然。

2.3 Confined growth.  2.3 限域生长。

To meet the demands of modern industry, it is imperative to achieve large-scale integration of 2D channel materials and their device manufacturing [ 8 , 25 , 60 62 ] [ 8 , 25 , 60 62 ] ^([8,25,60-62]){ }^{[8,25,60-62]}. Among the various methods for growing two-dimensional channel materials over large areas, it is difficult to precisely control the growth of materials in a specified area. And confined growth fulfills this requirement [ 63 65 ] [ 63 65 ] ^([63-65]){ }^{[63-65]}. By confined growth, this method effectively addresses challenges in conventional large-area growth, such as grain boundaries [ 14 , 66 ] [ 14 , 66 ] ^([14,)^(66]){ }^{[14,}{ }^{66]}, amorphization [ 67 , 68 ] [ 67 , 68 ] ^([67,)^(68]){ }^{[67,}{ }^{68]}, and mismatches between in-plane and out-of-plane growth rates [ 69 ] [ 69 ] ^([69]){ }^{[69]}, enabling the fabrication of large-area single-crystal 2D material arrays. In 2015, Zheng et al. [ 70 ] [ 70 ] ^([70]){ }^{[70]} employed a NaCl solution stamping method to synthesize Bi 2 Se 3 Bi 2 Se 3 Bi_(2)Se_(3)\mathrm{Bi}_{2} \mathrm{Se}_{3} and In 2 Se 3 In 2 Se 3 In_(2)Se_(3)\mathrm{In}_{2} \mathrm{Se}_{3} arrays. As shown in Figure 4a, similarly, In 2015, our group [ 71 ] [ 71 ] ^([71]){ }^{[71]} used standard mechanical exfoliation to transfer graphite onto SiO 2 / Si SiO 2 / Si SiO_(2)//Si\mathrm{SiO}_{2} / \mathrm{Si} substrates, followed by gravure printing of mica in NaCl solution using a polydimethylsiloxane (PDMS) stamp, and subsequent CVD growth of PbS on the NaCl NaCl NaCl-\mathrm{NaCl}- masked mica substrate yielded ordered PbS arrays (Figure 4e). In 2024, Zhang et al. [ 72 ] [ 72 ] ^([72]){ }^{[72]} developed hydrophilic square prism arrays via glass-etching observed in Figure 4 b , with hydrophobic modification of surrounding regions, and by exposing the droplet array to anti-solvent vapor in a sealed chamber, perovskite crystals nucleated and grew due to reduced solubility, ultimately forming precisely aligned perovskite arrays (PACAs) after solvent evaporation. Figure 4c shows that Kim et al. [ 73 ] [ 73 ] ^([73]){ }^{[73]} fabricated micron-scale trench arrays in a-SiO 2 2 _(2){ }_{2}-coated c Al 2 O 3 c Al 2 O 3 c-Al_(2)O_(3)\mathrm{c}-\mathrm{Al}_{2} \mathrm{O}_{3} or a HfO 2 / Si a HfO 2 / Si a-HfO_(2)//Si\mathrm{a}-\mathrm{HfO}_{2} / \mathrm{Si} wafers, where selective growth of WSe 2 WSe 2 WSe_(2)\mathrm{WSe}_{2} within the trenches allowed single-domain nucleation followed by lateral expansion, forming aligned WSe 2 WSe 2 WSe_(2)\mathrm{WSe}_{2} arrays in 2023(Figure 4f). In 2022, Zhang et al. [ 74 ] [ 74 ] ^([74]){ }^{[74]} introduced laser patterning and anisotropic thermal etching to create periodic triangular hole arrays in 2D crystals presented in Figure 4 d , enabling inside-out epitaxial growth of another 2D material and producing monolayer mosaic heterostructures (MHHs) with atomically sharp interfaces(Figure 4 g ). This process involved synthesizing large-area monolayer WS 2 WS 2 WS_(2)\mathrm{WS}_{2} single crystals via
为了满足现代工业的需求,实现二维通道材料及其器件制造的大规模集成势在必行 [ 8 , 25 , 60 62 ] [ 8 , 25 , 60 62 ] ^([8,25,60-62]){ }^{[8,25,60-62]} 。在各种大面积生长二维通道材料的方法中,精确控制材料在指定区域的生长较为困难。而受限生长满足了这一要求 [ 63 65 ] [ 63 65 ] ^([63-65]){ }^{[63-65]} 。通过受限生长,该方法有效解决了传统大面积生长中的晶界 [ 14 , 66 ] [ 14 , 66 ] ^([14,)^(66]){ }^{[14,}{ }^{66]} 、非晶化 [ 67 , 68 ] [ 67 , 68 ] ^([67,)^(68]){ }^{[67,}{ }^{68]} 以及面内与面外生长速率不匹配 [ 69 ] [ 69 ] ^([69]){ }^{[69]} 等挑战,实现了大面积单晶二维材料阵列的制备。2015 年,Zheng 等人 [ 70 ] [ 70 ] ^([70]){ }^{[70]} 采用 NaCl 溶液印章法合成了 Bi 2 Se 3 Bi 2 Se 3 Bi_(2)Se_(3)\mathrm{Bi}_{2} \mathrm{Se}_{3} In 2 Se 3 In 2 Se 3 In_(2)Se_(3)\mathrm{In}_{2} \mathrm{Se}_{3} 阵列。如图 4a 所示,同样在 2015 年,我们团队 [ 71 ] [ 71 ] ^([71]){ }^{[71]} 使用标准机械剥离法将石墨转移到 SiO 2 / Si SiO 2 / Si SiO_(2)//Si\mathrm{SiO}_{2} / \mathrm{Si} 基底上,随后利用聚二甲基硅氧烷(PDMS)印章在 NaCl 溶液中进行云母的凹版印刷,随后在 NaCl NaCl NaCl-\mathrm{NaCl}- 掩膜的云母基底上进行 PbS 的 CVD 生长,获得了有序的 PbS 阵列(图 4e)。2024 年,Zhang 等人 [ 72 ] [ 72 ] ^([72]){ }^{[72]} 通过玻璃蚀刻制备了亲水性方柱阵列,如图 4b 所示,并对周围区域进行了疏水性修饰,通过在密封腔室中将液滴阵列暴露于抗溶剂蒸气中,由于溶解度降低,钙钛矿晶体发生成核和生长,最终在溶剂蒸发后形成精确排列的钙钛矿阵列(PACA)。图 4c 显示 Kim 等人 [ 73 ] [ 73 ] ^([73]){ }^{[73]} 在 a-SiO 2 2 _(2){ }_{2} 涂层的 c Al 2 O 3 c Al 2 O 3 c-Al_(2)O_(3)\mathrm{c}-\mathrm{Al}_{2} \mathrm{O}_{3} a HfO 2 / Si a HfO 2 / Si a-HfO_(2)//Si\mathrm{a}-\mathrm{HfO}_{2} / \mathrm{Si} 晶片上制造了微米级沟槽阵列,其中沟槽内的 WSe 2 WSe 2 WSe_(2)\mathrm{WSe}_{2} 选择性生长实现了单域成核,随后横向扩展,形成了 2023 年对齐的 WSe 2 WSe 2 WSe_(2)\mathrm{WSe}_{2} 阵列(图 4f)。2022 年,Zhang 等人 [ 74 ] [ 74 ] ^([74]){ }^{[74]} 引入激光图案化和各向异性热蚀刻,在二维晶体中创建了周期性三角孔阵列(见图 4d),实现了另一种二维材料的由内向外外延生长,制备出具有原子级锐利界面的单层马赛克异质结构(MHHs)(图 4g)。该过程涉及通过合成大面积单层 WS 2 WS 2 WS_(2)\mathrm{WS}_{2} 单晶实现。
CVD, generating periodic point defect arrays using focused laser irradiation, thermally etching defects into triangular pores under controlled conditions, and growing WSe 2 WSe 2 WSe_(2)\mathrm{WSe}_{2} laterally within the patterned WS 2 WS 2 WS_(2)\mathrm{WS}_{2} template to form MHHs. Compared to traditional lithography and plasma etching, this approach offers advantages such as atomic-precision etching with high selectivity and avoids lithography-induced contamination, which can propagate through process steps, cause uncontrolled nucleation, and lead to heterogeneous multilayers.
CVD,利用聚焦激光照射生成周期性点缺陷阵列,在受控条件下通过热蚀刻将缺陷转化为三角形孔洞,并在图案化的 WS 2 WS 2 WS_(2)\mathrm{WS}_{2} 模板内横向生长 WSe 2 WSe 2 WSe_(2)\mathrm{WSe}_{2} 以形成 MHHs。与传统的光刻和等离子体蚀刻相比,该方法具有原子级精度的高选择性蚀刻优势,避免了光刻引起的污染,这种污染可能在工艺步骤中传播,导致不可控的成核并形成异质多层结构。
As discussed above, confined growth is crucial for the fabrication of large-area 2D channel materials. Various methods, including NaCl solution stamping, substrate patterning and etching, and heterostructure TMD layer etching, have been developed to achieve this goal. However, the size of individual regions within confined-growth arrays is often limited by factors such as material properties and substrate characteristics. To obtain arrays with larger individual areas and thinner thicknesses, further development of simple and effective strategies based on spatially confined methods is essential.
如上所述,受限生长对于大面积二维通道材料的制备至关重要。已经开发了多种方法,包括 NaCl 溶液印刷、基底图案化和蚀刻以及异质结构 TMD 层蚀刻,以实现这一目标。然而,受限生长阵列中单个区域的尺寸通常受材料性质和基底特性的限制。为了获得具有更大单个面积和更薄厚度的阵列,基于空间受限方法的简单有效策略的进一步发展是必不可少的。

Figure 4. Confined growth. a) Schematic representation of procedures for patterning of 2D PbS nanoplates arrays [ 70 ] [ 70 ] ^([70]){ }^{[70]}. b) Schematic diagram of the preparation process of PScAs. Formic acid (FAh) vapor-assisted crystallization was applied [ 72 ] [ 72 ] ^([72]){ }^{[72]}. c) Schematic of the selective single-domain synthesis strategy to address the limitations of conventional TMD growth. d)Schematic illustration of the lateral endoepitaxial
图 4. 限域生长。a) 2D PbS 纳米板阵列图案化工艺的示意图 [ 70 ] [ 70 ] ^([70]){ }^{[70]} 。b) PScAs 制备过程的示意图。采用了甲酸(FAh)蒸气辅助结晶 [ 72 ] [ 72 ] ^([72]){ }^{[72]} 。c) 选择性单域合成策略的示意图,以解决传统 TMD 生长的局限性。d) 侧向内外延的示意图

growth of WS 2 WSe 2 MMHs [ 73 ] WS 2 WSe 2 MMHs [ 73 ] WS_(2)-WSe_(2)MMHs^([73])\mathrm{WS}_{2}-\mathrm{WSe}_{2} \mathrm{MMHs}^{[73]}. e) The SEM images of the PbS nanoplates arrays under different reaction time 1 min and 2 min [ 71 ] 2 min [ 71 ] 2min[71]2 \min ^{[71]}. f) Single-domain WSe 2 WSe 2 WSe_(2)\mathrm{WSe}_{2} selectively synthesized in 2 μ m 2 μ m 2-mum2-\mu \mathrm{m} sapphire pockets fabricated with a SiO 2 a SiO 2 a-SiO_(2)\mathrm{a}-\mathrm{SiO}_{2} trenches. g) Optical microscopy images of the monolayer holey WS 2 WS 2 WS_(2)\mathrm{WS}_{2} templates fabricated by laser patterning and thermal etching with increasing etching durations of 20 s , 25 s , 30 s 20 s , 25 s , 30 s 20s,25s,30s20 \mathrm{~s}, 25 \mathrm{~s}, 30 \mathrm{~s} and 35 s at 1 , 100 C [ 74 ] 1 , 100 C [ 74 ] 1,100^(@)C^([74])1,100^{\circ} \mathrm{C}^{[74]}.
生长 WS 2 WSe 2 MMHs [ 73 ] WS 2 WSe 2 MMHs [ 73 ] WS_(2)-WSe_(2)MMHs^([73])\mathrm{WS}_{2}-\mathrm{WSe}_{2} \mathrm{MMHs}^{[73]} 。e) 不同反应时间 1 分钟和 2 min [ 71 ] 2 min [ 71 ] 2min[71]2 \min ^{[71]} 下 PbS 纳米板阵列的 SEM 图像。f) 在带有 a SiO 2 a SiO 2 a-SiO_(2)\mathrm{a}-\mathrm{SiO}_{2} 沟槽的 2 μ m 2 μ m 2-mum2-\mu \mathrm{m} 蓝宝石孔中选择性合成的单域 WSe 2 WSe 2 WSe_(2)\mathrm{WSe}_{2} 。g) 通过激光刻蚀和热蚀刻制备的单层多孔 WS 2 WS 2 WS_(2)\mathrm{WS}_{2} 模板的光学显微镜图像,蚀刻时间分别为 20 s , 25 s , 30 s 20 s , 25 s , 30 s 20s,25s,30s20 \mathrm{~s}, 25 \mathrm{~s}, 30 \mathrm{~s} 和 35 秒,温度为 1 , 100 C [ 74 ] 1 , 100 C [ 74 ] 1,100^(@)C^([74])1,100^{\circ} \mathrm{C}^{[74]}

2.4 low-temperature growth
2.4 低温生长

2.4.1 Low-temperature synthesis of 2D channel materials by Metal-organic Chemical Vapor Deposition (MOCVD).
2.4.1 通过金属有机化学气相沉积(MOCVD)低温合成二维通道材料。
With the advent of sub-5 nm semiconductor device technology, the thermal budget constraints of conventional high-temperature epitaxial processes have led to increasingly prominent issues such as interfacial misalignment, lattice distortion, and doping diffusion, which have emerged as critical bottlenecks restricting the further advancement of CMOS device performance. Notably, the integration of 2D semiconductor materials with existing CMOS back-end processes (BEOL) processes mandates temperatures below 450 C 450 C 450^(@)C450^{\circ} \mathrm{C} to ensure compatibility [ 75 , 76 ] [ 75 , 76 {:^([75,)76]\left.{ }^{[75,} 76\right]. In this context, low-temperature growth technologies represent a fundamental breakthrough to circumvent the physical and engineering limitations inherent in traditional high-temperature methodologies [ 77 , 78 ] [ 77 , 78 ] ^([77,78]){ }^{[77,78]}.
随着亚 5 纳米半导体器件技术的出现,传统高温外延工艺的热预算限制导致界面错位、晶格畸变和掺杂扩散等问题日益突出,成为限制 CMOS 器件性能进一步提升的关键瓶颈。值得注意的是,二维半导体材料与现有 CMOS 后端工艺(BEOL)集成必须保证温度低于 450 C 450 C 450^(@)C450^{\circ} \mathrm{C} 以确保兼容性 [ 75 , 76 ] [ 75 , 76 {:^([75,)76]\left.{ }^{[75,} 76\right] 。在此背景下,低温生长技术代表了一项根本性突破,能够规避传统高温方法固有的物理和工程限制 [ 77 , 78 ] [ 77 , 78 ] ^([77,78]){ }^{[77,78]}
In the growth methods of 2 D channel materials, MOCVD is a particularly promising approach and has become one of the mainstream techniques for low-temperature [ 79 ] [ 79 ] ^([79]){ }^{[79]}, large-area synthesis of 2 D semiconductor materials [ 80 82 ] [ 80 82 ] ^([80-82]){ }^{[80-82]}. MOCVD operates by decomposing metal-organic precursors to release metal atoms or nanoparticles, which then react on the surface of the target substrate to form semiconductor thin films. Compared to conventional CVD technologies, MOCVD exhibits higher precision control, superior uniformity, and enhanced low-temperature compatibility [ 83 , 84 ] [ 83 , 84 ] ^([83,84]){ }^{[83,84]}.
在二维通道材料的生长方法中,MOCVD 是一种特别有前景的方法,已成为低温 [ 79 ] [ 79 ] ^([79]){ }^{[79]} 、大面积合成二维半导体材料的主流技术之一 [ 80 82 ] [ 80 82 ] ^([80-82]){ }^{[80-82]} 。MOCVD 通过分解金属有机前驱体释放金属原子或纳米颗粒,然后在目标基底表面反应形成半导体薄膜。与传统的 CVD 技术相比,MOCVD 展现出更高的精确控制、更优的均匀性以及增强的低温兼容性 [ 83 , 84 ] [ 83 , 84 ] ^([83,84]){ }^{[83,84]}
In 2015, Kang et al. [ 76 ] [ 76 ] ^([76]){ }^{[76]} successfully achieved wafer-scale growth of 2 D MoS 2 2 D MoS 2 2DMoS_(2)2 \mathrm{D} \mathrm{MoS}{ }_{2} and WS2 films on SiO 2 SiO 2 SiO_(2)\mathrm{SiO}_{2} substrates using MOCVD, demonstrating exceptional electrical performance. The study employed molybdenum hexacarbonyl ( Mo ( CO ) 6 ) Mo ( CO ) 6 (Mo(CO)_(6))\left(\mathrm{Mo}(\mathrm{CO})_{6}\right) and
2015 年,Kang 等人 [ 76 ] [ 76 ] ^([76]){ }^{[76]} 成功实现了在 SiO 2 SiO 2 SiO_(2)\mathrm{SiO}_{2} 基底上利用 MOCVD 进行 2 D MoS 2 2 D MoS 2 2DMoS_(2)2 \mathrm{D} \mathrm{MoS}{ }_{2} 和 WS2 薄膜的晶圆级生长,展示了卓越的电学性能。该研究采用了六羰基钼 ( Mo ( CO ) 6 ) Mo ( CO ) 6 (Mo(CO)_(6))\left(\mathrm{Mo}(\mathrm{CO})_{6}\right)

tungsten hexacarbonyl ( W ( CO ) 6 ) W ( CO ) 6 (W(CO)_(6))\left(\mathrm{W}(\mathrm{CO})_{6}\right) as metal precursors, which thermally decompose to release metal atoms. Diethyl sulfide ( ( C 2 H 5 ) 2 S ) C 2 H 5 2 S ((C_(2)H_(5))_(2)(S))\left(\left(\mathrm{C}_{2} \mathrm{H}_{5}\right)_{2} \mathrm{~S}\right) was used as the sulfur source, releasing sulfur atoms via a hydrogen-assisted reduction reaction. All reactant gases were mixed in a hydrogen ( H 2 ) H 2 (H_(2))\left(\mathrm{H}_{2}\right) environment and transported to a high-temperature reaction chamber. Notably, the growth temperature for single-layer MoS 2 MoS 2 MoS_(2)\mathrm{MoS}_{2} and WS 2 WS 2 WS_(2)\mathrm{WS}_{2} was reduced to as low as 550 C 550 C 550^(@)C550^{\circ} \mathrm{C}, significantly lower than the 800 C 800 C ∼800^(@)C\sim 800^{\circ} \mathrm{C} required by traditional CVD methods. Mun et al. [ 85 ] [ 85 ] ^([85]){ }^{[85]} proposed a kinetics-controlled MOCVD method to directly grow high-quality monolayer MoS 2 MoS 2 MoS_(2)\mathrm{MoS}_{2} films on polyimide (PI) substrates at a low temperature of 250 C 250 C 250^(@)C250{ }^{\circ} \mathrm{C}. By precisely controlling the feeding rate and dosage of NaCl , this work introduced alkali-metal catalysts to suppress nucleation density and enhance surface atomic diffusion capability, achieving wafer-scale uniform growth. Additionally, the integration of silanized SiO 2 SiO 2 SiO_(2)\mathrm{SiO}_{2} buffer layers and glass-supported flexible PI substrates addressed issues of thermal deformation and surface contamination in polymers.
六羰基钨 ( W ( CO ) 6 ) W ( CO ) 6 (W(CO)_(6))\left(\mathrm{W}(\mathrm{CO})_{6}\right) 作为金属前驱体,通过热分解释放金属原子。二乙基硫醚 ( ( C 2 H 5 ) 2 S ) C 2 H 5 2 S ((C_(2)H_(5))_(2)(S))\left(\left(\mathrm{C}_{2} \mathrm{H}_{5}\right)_{2} \mathrm{~S}\right) 作为硫源,通过氢辅助还原反应释放硫原子。所有反应气体在氢气 ( H 2 ) H 2 (H_(2))\left(\mathrm{H}_{2}\right) 环境中混合并输送到高温反应室。值得注意的是,单层 MoS 2 MoS 2 MoS_(2)\mathrm{MoS}_{2} WS 2 WS 2 WS_(2)\mathrm{WS}_{2} 的生长温度降低至仅为 550 C 550 C 550^(@)C550^{\circ} \mathrm{C} ,显著低于传统 CVD 方法所需的 800 C 800 C ∼800^(@)C\sim 800^{\circ} \mathrm{C} 。Mun 等人 [ 85 ] [ 85 ] ^([85]){ }^{[85]} 提出了一种动力学控制的 MOCVD 方法,在低温 250 C 250 C 250^(@)C250{ }^{\circ} \mathrm{C} 下直接在聚酰亚胺(PI)基底上生长高质量单层 MoS 2 MoS 2 MoS_(2)\mathrm{MoS}_{2} 薄膜。通过精确控制 NaCl 的进料速率和用量,该工作引入了碱金属催化剂以抑制成核密度并增强表面原子扩散能力,实现了晶圆级均匀生长。此外,硅烷化 SiO 2 SiO 2 SiO_(2)\mathrm{SiO}_{2} 缓冲层与玻璃支撑的柔性 PI 基底的集成,解决了聚合物的热变形和表面污染问题。
Song et al. [ 86 ] [ 86 ] ^([86]){ }^{[86]} developed a pulsed-flow MOCVD method to achieve wafer-scale growth of 2D InSe films on c-plane sapphire substrates at temperatures as low as 350 350 350-350- 500 C 500 C 500^(@)C500{ }^{\circ} \mathrm{C}. By modulating the Se precursor flux through pulsed delivery, they dynamically controlled the Se / In Se / In Se//In\mathrm{Se} / \mathrm{In} ratio to suppress the formation of the In 2 Se 3 In 2 Se 3 In_(2)Se_(3)\mathrm{In}_{2} \mathrm{Se}_{3} phase and promote layer-by-layer growth of InSe. The pulsed-flow technique also prevented the formation of In-rich droplets, enabling lateral coalescence of InSe domains into continuous thin films with thickness controllability (from monolayer to few layers). A recent breakthrough by Zhu et al. [ 87 ] [ 87 ] ^([87]){ }^{[87]} has demonstrated a revolutionary low-temperature growth process that enables efficient, uniform wafer-scale monolayer MoS 2 MoS 2 MoS_(2)\mathrm{MoS}_{2} growth directly on silicon wafers in less than one hour, with temperatures below those required by current CMOS BEOL processes (Figure 5a,b). The researchers have developed a novel tubular furnace system custom-engineered for MOCVD, featuring two vertically separated chambers, a low-temperature ( 250 C ) 250 C (250^(@)C)\left(250{ }^{\circ} \mathrm{C}\right) front chamber for silicon wafer placement and Mo ( CO ) 6 Mo ( CO ) 6 Mo(CO)_(6)\mathrm{Mo}(\mathrm{CO})_{6} precursor, and a high-temperature ( 550 C ) 550 C (550^(@)C)\left(550{ }^{\circ} \mathrm{C}\right) rear chamber for pyrolyzing the sulfur precursor ( C 2 H 5 ) 2 S C 2 H 5 2 S (C_(2)H_(5))_(2)S\left(\mathrm{C}_{2} \mathrm{H}_{5}\right)_{2} \mathrm{~S} to generate reactive sulfur radicals. The silicon wafers are vertically positioned to
Song 等人 [ 86 ] [ 86 ] ^([86]){ }^{[86]} 开发了一种脉冲流 MOCVD 方法,实现了在 c 面蓝宝石衬底上低至 350 350 350-350- 500 C 500 C 500^(@)C500{ }^{\circ} \mathrm{C} 温度下的二维 InSe 薄膜晶圆级生长。通过脉冲输送调节 Se 前驱体通量,他们动态控制了 Se / In Se / In Se//In\mathrm{Se} / \mathrm{In} 比率,以抑制 In 2 Se 3 In 2 Se 3 In_(2)Se_(3)\mathrm{In}_{2} \mathrm{Se}_{3} 相的形成并促进 InSe 的逐层生长。脉冲流技术还防止了富铟液滴的形成,使 InSe 域能够横向合并成具有厚度可控性(从单层到少层)的连续薄膜。Zhu 等人 [ 87 ] [ 87 ] ^([87]){ }^{[87]} 最近的突破展示了一种革命性的低温生长工艺,能够在不到一小时内直接在硅晶圆上高效、均匀地实现晶圆级单层 MoS 2 MoS 2 MoS_(2)\mathrm{MoS}_{2} 生长,温度低于当前 CMOS BEOL 工艺所需的温度(图 5a,b)。 研究人员开发了一种新型管式炉系统,专为 MOCVD 定制,具有两个垂直分隔的腔室,一个低温 ( 250 C ) 250 C (250^(@)C)\left(250{ }^{\circ} \mathrm{C}\right) 前腔用于放置硅片和 Mo ( CO ) 6 Mo ( CO ) 6 Mo(CO)_(6)\mathrm{Mo}(\mathrm{CO})_{6} 前驱体,另一个高温 ( 550 C ) 550 C (550^(@)C)\left(550{ }^{\circ} \mathrm{C}\right) 后腔用于热解硫前驱体 ( C 2 H 5 ) 2 S C 2 H 5 2 S (C_(2)H_(5))_(2)S\left(\mathrm{C}_{2} \mathrm{H}_{5}\right)_{2} \mathrm{~S} 以生成活性硫自由基。硅片垂直放置以

avoid thermal damage from the high-temperature region, and ensuring uniform precursor delivery across the entire 200 mm wafer scale. In the high-temperature chamber, the sulfur precursor ( C 2 H 5 ) 2 S C 2 H 5 2 S (C_(2)H_(5))_(2)S\left(\mathrm{C}_{2} \mathrm{H}_{5}\right)_{2} \mathrm{~S} is thermally decomposed to generate reactive sulfur species, while the low-temperature chamber receives these sulfur species via heat conduction, this can preventing excessive decomposition of the Mo ( CO ) 6 Mo ( CO ) 6 Mo(CO)_(6)\mathrm{Mo}(\mathrm{CO})_{6} precursor. This dual-zone design allows directional MoS 2 MoS 2 MoS_(2)\mathrm{MoS}_{2} growth at low temperatures. By dynamically adjusting the pulse frequency and duty cycle of Mo ( CO ) 6 Mo ( CO ) 6 Mo(CO)_(6)\operatorname{Mo}(\mathrm{CO})_{6}, the team precisely controls the instantaneous Mo flux to balance nucleation density and grain growth rates, ultimately achieving wafer-scale uniform monolayer films. This method not only enables a short growth time but also operates at significantly lower temperatures, making it highly compatible with existing CMOS manufacturing processes and an ideal solution for large-scale integration of 2D materials into semiconductor devices (Figure 5C). Furthermore, they using this method, MoS 2 MoS 2 MoS_(2)\mathrm{MoS}_{2} transistors were successfully integrated directly onto silicon CMOS circuits at a growth temperature of 250 C 250 C 250^(@)C250^{\circ} \mathrm{C}. The directly integrated devices exhibited exceptional electrical performance (Figure 5d,e).
避免高温区域的热损伤,并确保整个 200 毫米晶圆尺度上前驱体的均匀输送。在高温腔室中,硫前驱体 ( C 2 H 5 ) 2 S C 2 H 5 2 S (C_(2)H_(5))_(2)S\left(\mathrm{C}_{2} \mathrm{H}_{5}\right)_{2} \mathrm{~S} 被热分解生成活性硫物种,而低温腔室通过热传导接收这些硫物种,从而防止 Mo ( CO ) 6 Mo ( CO ) 6 Mo(CO)_(6)\mathrm{Mo}(\mathrm{CO})_{6} 前驱体的过度分解。这种双区设计允许在低温下实现定向 MoS 2 MoS 2 MoS_(2)\mathrm{MoS}_{2} 生长。通过动态调整 Mo ( CO ) 6 Mo ( CO ) 6 Mo(CO)_(6)\operatorname{Mo}(\mathrm{CO})_{6} 的脉冲频率和占空比,团队精确控制瞬时 Mo 通量,以平衡成核密度和晶粒生长速率,最终实现晶圆级均匀单层薄膜。该方法不仅实现了短生长时间,还在显著较低的温度下运行,使其高度兼容现有 CMOS 制造工艺,是将二维材料大规模集成到半导体器件中的理想解决方案(图 5C)。此外,利用该方法, MoS 2 MoS 2 MoS_(2)\mathrm{MoS}_{2} 晶体管成功直接集成到硅 CMOS 电路中,生长温度为 250 C 250 C 250^(@)C250^{\circ} \mathrm{C} 。 直接集成的器件表现出卓越的电性能(图 5d,e)。
Hoang et al. [ 88 ] [ 88 ] ^([88]){ }^{[88]} successfully synthesized high-quality, highly crystalline monolayer MoS 2 MoS 2 MoS_(2)\mathrm{MoS}_{2} on PI and glass substrates using a similar method (Figure 5F-I). Notably, their work employed dimethyl sulfide (DMS, ( CH 3 ) 2 S CH 3 2 S (CH_(3))_(2)S\left(\mathrm{CH}_{3}\right)_{2} \mathrm{~S} ) as the sulfur source and positioned the high-temperature zone upstream while the low-temperature zone was downstream. The researchers developed a low-temperature ( 150 C ) 150 C (150^(@)C)\left(150^{\circ} \mathrm{C}\right) MOCVD process. First, a mixed precursor solution of Mo ( CO ) 6 Mo ( CO ) 6 Mo(CO)_(6)\operatorname{Mo}(\mathrm{CO})_{6} and DMS was prepared. Subsequently, deposition occurred in a thermally wall asymmetric three-zone MOCVD system with two-stage flow rate control-initial low flow for nucleation and subsequent high flow for film expansion. The system’s extended high-temperature zone ensured stable growth at 150 C 150 C 150^(@)C150^{\circ} \mathrm{C}, while slow cooling in an H 2 S H 2 S H_(2)S\mathrm{H}_{2} \mathrm{~S} environment suppressed sulfur vacancies. This method eliminated substrate transfer steps, directly achieving wafer-scale uniform MoS 2 MoS 2 MoS_(2)\mathrm{MoS}_{2} films (grain size up to 800 nm ) on flexible and glass substrates. The integrated devices demonstrated exceptional performance, including high electron mobility ( 9.1 cm 2 / V s ) 9.1 cm 2 / V s (9.1cm^(2)//V*s)\left(9.1 \mathrm{~cm}^{2} / \mathrm{V} \cdot \mathrm{s}\right), low power consumption, and robust mechanical
Hoang 等人 [ 88 ] [ 88 ] ^([88]){ }^{[88]} 成功合成了高质量、高结晶度的单层 MoS 2 MoS 2 MoS_(2)\mathrm{MoS}_{2} ,基底为 PI 和玻璃,采用了类似的方法(图 5F-I)。值得注意的是,他们的工作使用了二甲基硫醚(DMS, ( CH 3 ) 2 S CH 3 2 S (CH_(3))_(2)S\left(\mathrm{CH}_{3}\right)_{2} \mathrm{~S} )作为硫源,并将高温区设置在上游,低温区位于下游。研究人员开发了一种低温 ( 150 C ) 150 C (150^(@)C)\left(150^{\circ} \mathrm{C}\right) MOCVD 工艺。首先,制备了 Mo ( CO ) 6 Mo ( CO ) 6 Mo(CO)_(6)\operatorname{Mo}(\mathrm{CO})_{6} 和 DMS 的混合前驱体溶液。随后,在一个热壁非对称三区 MOCVD 系统中进行沉积,采用两阶段流量控制——初期低流量用于成核,随后高流量用于薄膜扩展。系统延长的高温区确保了在 150 C 150 C 150^(@)C150^{\circ} \mathrm{C} 的稳定生长,同时在 H 2 S H 2 S H_(2)S\mathrm{H}_{2} \mathrm{~S} 环境中缓慢冷却抑制了硫空位。该方法消除了基底转移步骤,直接实现了柔性和玻璃基底上的晶粒尺寸达 800 纳米的晶圆级均匀 MoS 2 MoS 2 MoS_(2)\mathrm{MoS}_{2} 薄膜。集成器件表现出卓越性能,包括高电子迁移率 ( 9.1 cm 2 / V s ) 9.1 cm 2 / V s (9.1cm^(2)//V*s)\left(9.1 \mathrm{~cm}^{2} / \mathrm{V} \cdot \mathrm{s}\right) 、低功耗和优异的机械性能。

flexibility (Figure 5J,K).
灵活性(图 5J,K)。

Figure 5. Low-temperature growth of 2 D semiconductor channel materials by the MOCVD method. a) Low-Temperature MOCVD Process for Wafer-Scale MoS 2 MoS 2 MoS_(2)\mathrm{MoS}_{2} Synthesis. b) Optical image of MoS 2 MoS 2 MoS_(2)\mathrm{MoS}_{2} synthesized on 300 nm SiO bare substrate. c) Growth time and thermal budget for Monolayer MoS 2 MoS 2 MoS_(2)\mathrm{MoS}_{2} synthesis via different methods. d) Transfer characteristics of 510 MoS 2 510 MoS 2 510MoS_(2)510 \mathrm{MoS}_{2} transistors. e) Subthreshold SS Characteristics of Back-Gated MoS 2 MoS 2 MoS_(2)\mathrm{MoS}_{2} Transistors Fabricated on a 200 mm Wafer. f) Ultrahigh crystalline quality wafer-scale MoS 2 MoS 2 MoS_(2)\mathrm{MoS}_{2} synthesis process.
图 5. 通过 MOCVD 方法低温生长二维半导体通道材料。a)晶圆级 MoS 2 MoS 2 MoS_(2)\mathrm{MoS}_{2} 合成的低温 MOCVD 工艺。b)在 300 nm SiO 裸基底上合成的 MoS 2 MoS 2 MoS_(2)\mathrm{MoS}_{2} 的光学图像。c)通过不同方法合成单层 MoS 2 MoS 2 MoS_(2)\mathrm{MoS}_{2} 的生长时间和热预算。d) 510 MoS 2 510 MoS 2 510MoS_(2)510 \mathrm{MoS}_{2} 晶体管的传输特性。e)在 200 mm 晶圆上制造的背栅 MoS 2 MoS 2 MoS_(2)\mathrm{MoS}_{2} 晶体管的亚阈值 SS 特性。f)超高晶体质量晶圆级 MoS 2 MoS 2 MoS_(2)\mathrm{MoS}_{2} 合成工艺。

g) Optical image of large-area MoS 2 MoS 2 MoS_(2)\mathrm{MoS}_{2} synthesized on ultrathin glass. h) AFM image of large-area MoS 2 MoS 2 MoS_(2)\mathrm{MoS}_{2} synthesized on ultrathin glass. i) An annular dark-field scanning transmission electron microscope (ADF-STEM) image and corresponding selected area electron diffraction (SAED) patterns (inset). j) ID-VG curves of HT- MoS 2 MoS 2 MoS_(2)\mathrm{MoS}_{2} (red), LT- MoS 2 / MoS 2 / MoS_(2)//\mathrm{MoS}_{2} / parylene C (green), and LT- MoS 2 / UTG MoS 2 / UTG MoS_(2)//UTG\mathrm{MoS}_{2} / \mathrm{UTG} (blue) in log log log\log (solid) and linear (dashed) scales. k ) Uniform performance of the LT- MoS 2 MoS 2 MoS_(2)\mathrm{MoS}_{2} TFT array across the entire substrate.
g)在超薄玻璃上合成的大面积 MoS 2 MoS 2 MoS_(2)\mathrm{MoS}_{2} 的光学图像。h)在超薄玻璃上合成的大面积 MoS 2 MoS 2 MoS_(2)\mathrm{MoS}_{2} 的 AFM 图像。i)环形暗场扫描透射电子显微镜(ADF-STEM)图像及相应的选区电子衍射(SAED)图案(插图)。j)HT- MoS 2 MoS 2 MoS_(2)\mathrm{MoS}_{2} (红色)、LT- MoS 2 / MoS 2 / MoS_(2)//\mathrm{MoS}_{2} / 聚对二甲苯 C(绿色)和 LT- MoS 2 / UTG MoS 2 / UTG MoS_(2)//UTG\mathrm{MoS}_{2} / \mathrm{UTG} (蓝色)在 log log log\log (实线)和线性(虚线)尺度下的 ID-VG 曲线。k)LT- MoS 2 MoS 2 MoS_(2)\mathrm{MoS}_{2} 薄膜晶体管阵列在整个基底上的均匀性能。

2.4.2 Low-temperature synthesis of 2D channel materials by other methods.
2.4.2 其他方法的二维通道材料低温合成。

In addition to MOCVD methods for low-temperature growth of 2D channel materials, researchers are now exploring alternative approaches such as low-melting-point precursors [ 89 91 ] [ 89 91 ] ^([89-91]){ }^{[89-91]}, plasma enhanced chemical vapor deposition
除了用于低温生长二维通道材料的 MOCVD 方法外,研究人员现在还在探索其他方法,如低熔点前驱体 [ 89 91 ] [ 89 91 ] ^([89-91]){ }^{[89-91]} 、等离子体增强化学气相沉积

(PECVD) ) [ 92 94 ] ) [ 92 94 ] )^([92-94]))^{[92-94]}, vdW epitaxial substrates [ 95 , 96 ] [ 95 , 96 ] ^([95,96]){ }^{[95,96]}, tellurium-assisted growth [ 97 ] [ 97 ] ^([97]){ }^{[97]}, and salt-assisted growth [ 88 100 ] [ 88 100 ] ^([88-100]){ }^{[88-100]}. Recently, Moon et al. [ 101 ] [ 101 ] ^([101]){ }^{[101]} proposed a novel hypotaxy growth method that enables direct wafer-scale synthesis of 2D channel materials on various substrates at 400 C 400 C 400^(@)C400^{\circ} \mathrm{C}, making it compatible with CMOS BEOL (Figure 6a-f). This graphene-assisted sulfidization/selenization technique realizes low-temperature epitaxial growth of single-crystal TMDs through metal film (e.g., Mo) sulfuration on non-crystalline or lattice-mismatched substrates. Initially, MoS 2 / MoSe 2 MoS 2 / MoSe 2 MoS_(2)//MoSe_(2)\mathrm{MoS}_{2} / \mathrm{MoSe}_{2} nuclei aligned with graphene are formed at 1000 C 1000 C 1000^(@)C1000^{\circ} \mathrm{C} via sulfurization, followed by vertical-oriented crystal growth as graphene is etched and sulfurizing gas penetrates. By oxygen plasma pretreatment of graphene to introduce nanopores, the growth temperature can be reduced to 400 C 400 C 400^(@)C400^{\circ} \mathrm{C}, overcoming traditional epitaxial limitations requiring high temperatures and specific substrates. This method demonstrates precise thickness control from monolayer to multilayer (up to 100 layers), producing MoS 2 MoS 2 MoS_(2)\mathrm{MoS}_{2} films with exceptional properties including 120 W / m K 120 W / m K 120W//m*K120 \mathrm{~W} / \mathrm{m} \cdot \mathrm{K} thermal conductivity and 87 cm 2 / ( V s ) 87 cm 2 / ( V s ) 87cm^(2)//(V*s)87 \mathrm{~cm}^{2} /(\mathrm{V} \cdot \mathrm{s}) electron mobility. It has been successfully extended to other TMD systems (MoSe 2 2 _(2){ }_{2}, WS 2 WS 2 WS_(2)\mathrm{WS}_{2} ) and holds great promise for 3D monolithic integration.
(PECVD) ) [ 92 94 ] ) [ 92 94 ] )^([92-94]))^{[92-94]} ,vdW 外延衬底 [ 95 , 96 ] [ 95 , 96 ] ^([95,96]){ }^{[95,96]} ,碲辅助生长 [ 97 ] [ 97 ] ^([97]){ }^{[97]} ,盐辅助生长 [ 88 100 ] [ 88 100 ] ^([88-100]){ }^{[88-100]} 。最近,Moon 等人 [ 101 ] [ 101 ] ^([101]){ }^{[101]} 提出了一种新颖的假外延生长方法,能够在 400 C 400 C 400^(@)C400^{\circ} \mathrm{C} 上实现二维通道材料在各种衬底上的直接晶圆级合成,使其兼容 CMOS BEOL(图 6a-f)。这种石墨烯辅助的硫化/硒化技术通过金属薄膜(如 Mo)在非晶或晶格失配衬底上的硫化,实现了单晶 TMDs 的低温外延生长。最初,在 1000 C 1000 C 1000^(@)C1000^{\circ} \mathrm{C} 通过硫化形成与石墨烯对齐的 MoS 2 / MoSe 2 MoS 2 / MoSe 2 MoS_(2)//MoSe_(2)\mathrm{MoS}_{2} / \mathrm{MoSe}_{2} 核,随后随着石墨烯被蚀刻和硫化气体渗透,晶体垂直生长。通过对石墨烯进行氧等离子体预处理以引入纳米孔,生长温度可降低至 400 C 400 C 400^(@)C400^{\circ} \mathrm{C} ,克服了传统外延需要高温和特定衬底的限制。该方法展示了从单层到多层(最多 100 层)的精确厚度控制,制备出具有卓越性能的 MoS 2 MoS 2 MoS_(2)\mathrm{MoS}_{2} 薄膜,包括 120 W / m K 120 W / m K 120W//m*K120 \mathrm{~W} / \mathrm{m} \cdot \mathrm{K} 热导率和 87 cm 2 / ( V s ) 87 cm 2 / ( V s ) 87cm^(2)//(V*s)87 \mathrm{~cm}^{2} /(\mathrm{V} \cdot \mathrm{s}) 电子迁移率。 它已成功扩展到其他 TMD 系统(MoSe 2 2 _(2){ }_{2} WS 2 WS 2 WS_(2)\mathrm{WS}_{2} ),并且对 3D 单片集成具有巨大潜力。
Kim et al. [ 102 ] [ 102 ] ^([102]){ }^{[102]} developed a low-temperature single-crystal 2D semiconductor growth technique based on geometrically constrained selective epitaxy by designing an array of silica mask microgrooves at specific edge angles on an amorphous hafnium oxide ( a HfO 2 a HfO 2 a-HfO_(2)\mathrm{a}-\mathrm{HfO}_{2} ) substrate, exploiting the chemical bonding enhancement effect and nucleation principle of the edge sites and combining with a dual-temperature CVD system to realize a single-crystal at 380 385 C MoS 2 / WSe 2 380 385 C MoS 2 / WSe 2 380-385^(@)CMoS2//WSe_(2)380-385{ }^{\circ} \mathrm{C} \mathrm{MoS} 2 / \mathrm{WSe}_{2} epitaxy(Figure 6 g k 6 g k 6g-k6 \mathrm{~g}-\mathrm{k} ). By regulating the microgroove dimensions to confine the lateral growth range, ensuring single - nucleus nucleation and lateral monolayer growth, high - quality single - crystal thin 2D semiconductor channel materials films with a mobility of > 50 cm 2 / V s > 50 cm 2 / V s > 50cm^(2)//V*s>50 \mathrm{~cm}^{2} / \mathrm{V} \cdot \mathrm{s} is obtained. Huang et al. [ 103 ] [ 103 ] ^([103]){ }^{[103]} recently developed a pressure-assisted liquid-metal printing technique to achieve controlled growth of β Ga 2 O 3 β Ga 2 O 3 beta-Ga_(2)O_(3)\beta-\mathrm{Ga}_{2} \mathrm{O}_{3} thin films at 150 C 150 C 150^(@)C150^{\circ} \mathrm{C} under solvent-free, ambient air conditions without vacuum (Figure 6i,m). By leveraging the oxide skin formed during liquid gallium oxidation as a precursor and tuning external pressures between 29 129 kPa 29 129 kPa 29-129kPa29-129 \mathrm{kPa}, they
Kim 等人 [ 102 ] [ 102 ] ^([102]){ }^{[102]} 通过在非晶氧化铪( a HfO 2 a HfO 2 a-HfO_(2)\mathrm{a}-\mathrm{HfO}_{2} )基底上设计具有特定边缘角度的二氧化硅掩膜微槽阵列,基于几何约束选择性外延,开发了一种低温单晶二维半导体生长技术,利用边缘位点的化学键增强效应和成核原理,结合双温度 CVD 系统,实现了 380 385 C MoS 2 / WSe 2 380 385 C MoS 2 / WSe 2 380-385^(@)CMoS2//WSe_(2)380-385{ }^{\circ} \mathrm{C} \mathrm{MoS} 2 / \mathrm{WSe}_{2} 的单晶外延(图 6 g k 6 g k 6g-k6 \mathrm{~g}-\mathrm{k} )。通过调节微槽尺寸以限制横向生长范围,确保单核成核和横向单层生长,获得了迁移率为 > 50 cm 2 / V s > 50 cm 2 / V s > 50cm^(2)//V*s>50 \mathrm{~cm}^{2} / \mathrm{V} \cdot \mathrm{s} 的高质量单晶薄二维半导体通道材料薄膜。Huang 等人 [ 103 ] [ 103 ] ^([103]){ }^{[103]} 最近开发了一种压力辅助液态金属印刷技术,在无溶剂、常温空气条件下无真空环境中,实现了 150 C 150 C 150^(@)C150^{\circ} \mathrm{C} β Ga 2 O 3 β Ga 2 O 3 beta-Ga_(2)O_(3)\beta-\mathrm{Ga}_{2} \mathrm{O}_{3} 薄膜的可控生长(图 6i,m)。通过利用液态镓氧化过程中形成的氧化皮作为前驱体,并调节 29 129 kPa 29 129 kPa 29-129kPa29-129 \mathrm{kPa} 之间的外部压力,他们...

successfully fabricated polycrystalline β Ga 2 O 3 β Ga 2 O 3 beta-Ga_(2)O_(3)\beta-\mathrm{Ga}_{2} \mathrm{O}_{3} nanosheets with a thickness of 3 nm 3 nm ∼3nm\sim 3 \mathrm{~nm}. The resulting n-type thin-film transistors (TFTs) exhibited exceptional performance: a saturation mobility of 11.7 cm 2 V 1 s 1 11.7 cm 2 V 1 s 1 11.7cm^(2)V^(-1)s^(-1)11.7 \mathrm{~cm}^{2} \mathrm{~V}^{-1} \mathrm{~s}^{-1}, on/off-current ratio of 10 8 10 8 10^(8)10^{8}, and subthreshold swing of 163 mV 1 163 mV 1 163mV^(-1)163 \mathrm{mV}^{-1} decade. Low-temperature growth is crucial for the development of 2D semiconductors, as traditional CVD techniques are severely limited by their high-temperature requirements. With continuous advancements in low-temperature growth technologies, industrial applications of 2D semiconductors are expected to be further propelled.
成功制备了厚度为 3 nm 3 nm ∼3nm\sim 3 \mathrm{~nm} 的多晶 β Ga 2 O 3 β Ga 2 O 3 beta-Ga_(2)O_(3)\beta-\mathrm{Ga}_{2} \mathrm{O}_{3} 纳米片。所得的 n 型薄膜晶体管(TFT)表现出优异的性能:饱和迁移率为 11.7 cm 2 V 1 s 1 11.7 cm 2 V 1 s 1 11.7cm^(2)V^(-1)s^(-1)11.7 \mathrm{~cm}^{2} \mathrm{~V}^{-1} \mathrm{~s}^{-1} ,开关电流比为 10 8 10 8 10^(8)10^{8} ,亚阈值摆幅为 163 mV 1 163 mV 1 163mV^(-1)163 \mathrm{mV}^{-1} 十倍。低温生长对于 2D 半导体的发展至关重要,因为传统的 CVD 技术受限于其高温要求。随着低温生长技术的不断进步,2D 半导体的工业应用有望进一步推动。

Figure 6. Alternative methods for low-temperature growth of 2D semiconductor channel materials. a) Schematic of traditional epitaxial growth mechanisms. b) Schematic of hypotaxy growth mechanisms. c-f) The TEM image of step-by-step process by hypotaxial growth. [ 101 ] g [ 101 ] g ^([101])g{ }^{[101]} \mathrm{g} ) Schematic of low-temperature growth of single-crystal TMD arrays. SEM images of the initial nucleation of WSe 2 WSe 2 WSe_(2)\mathrm{WSe}_{2} in patterned silicon dioxide pockets on an HfO 2 HfO 2 HfO_(2)\mathrm{HfO}_{2} substrate at different temperatures 700 C h 700 C h 700^(@)Ch700{ }^{\circ} \mathrm{C} \mathrm{h} ), 485 C 485 C 485^(@)C485^{\circ} \mathrm{C} i), and 385 C . j 385 C . j 385^(@)C.j385^{\circ} \mathrm{C} . \mathrm{j} ) respectively. k) SEM image of singlecrystalline WSe 2 WSe 2 WSe_(2)\mathrm{WSe}_{2} grown at 385 C . [ 102 ] 385 C . [ 102 ] 385^(@)C.^([102])385{ }^{\circ} \mathrm{C} .{ }^{[102]} 1) Schematic and optical images of the pressure-assisted liquid metal
图 6. 低温生长二维半导体通道材料的替代方法。a) 传统外延生长机制示意图。b) 假外延生长机制示意图。c-f) 假外延生长逐步过程的透射电子显微镜(TEM)图像。 [ 101 ] g [ 101 ] g ^([101])g{ }^{[101]} \mathrm{g} ) 单晶 TMD 阵列低温生长示意图。在不同温度下, WSe 2 WSe 2 WSe_(2)\mathrm{WSe}_{2} 在图案化二氧化硅凹槽中的初始成核的扫描电子显微镜(SEM)图像,分别为 HfO 2 HfO 2 HfO_(2)\mathrm{HfO}_{2} 基底的 700 C h 700 C h 700^(@)Ch700{ }^{\circ} \mathrm{C} \mathrm{h} )、 485 C 485 C 485^(@)C485^{\circ} \mathrm{C} i)和 385 C . j 385 C . j 385^(@)C.j385^{\circ} \mathrm{C} . \mathrm{j} )。k) 在 385 C . [ 102 ] 385 C . [ 102 ] 385^(@)C.^([102])385{ }^{\circ} \mathrm{C} .{ }^{[102]} 生长的单晶 WSe 2 WSe 2 WSe_(2)\mathrm{WSe}_{2} 的 SEM 图像。1) 压力辅助液态金属的示意图和光学图像

printing route for synthesizing Ga 2 O 3 Ga 2 O 3 Ga_(2)O_(3)\mathrm{Ga}_{2} \mathrm{O}_{3} nanosheets. m) AFM images of the cross-section and surface of the synthesized Ga 2 O 3 Ga 2 O 3 Ga_(2)O_(3)\mathrm{Ga}_{2} \mathrm{O}_{3} nanosheets. [ 103 ] [ 103 ] ^([103]){ }^{[103]}
合成 Ga 2 O 3 Ga 2 O 3 Ga_(2)O_(3)\mathrm{Ga}_{2} \mathrm{O}_{3} 纳米片的印刷路线。m) 合成的 Ga 2 O 3 Ga 2 O 3 Ga_(2)O_(3)\mathrm{Ga}_{2} \mathrm{O}_{3} 纳米片的截面和表面原子力显微镜(AFM)图像。 [ 103 ] [ 103 ] ^([103]){ }^{[103]}

3 Synthesis of Dielectric layers
3 介电层的合成

2D materials have great potential in device applications due to their unique properties. However, the conventional dielectrics used in current silicon-based processes are not compatible with 2D channel materials [ 47 ] [ 47 ] ^([47]){ }^{[47]}, as the vdW surface and ultra-thin thickness of 2D materials lead to severe performance degradation by the various dangling bonds on the conventional dielectrics, and it is also very difficult for the conventional processes to deposit high-quality dielectrics on the surface of 2D materials due to the inert surface of 2D materials. It is also very difficult to deposit high quality dielectrics on the surface of 2D materials by conventional processes due to the inert surface of 2D materials, so it is crucial to synthesis dielectric layers that is more compatible with 2D channel materials.
由于二维材料的独特性质,它们在器件应用中具有巨大潜力。然而,当前基于硅工艺中使用的传统介电材料与二维通道材料不兼容,因为二维材料的范德华表面和超薄厚度导致传统介电材料上的各种悬挂键引起严重的性能退化,而且由于二维材料表面的惰性,传统工艺也很难在二维材料表面沉积高质量的介电层。因此,合成与二维通道材料更兼容的介电层至关重要。

3.1 Synthesis of two-dimensional dielectric layers by CVD method
3.1 通过化学气相沉积(CVD)方法合成二维介电层

CVD is a widely utilized technique for synthesizing various high-quality dielectric materials as gate dielectrics in 2D electronic devices. Hexagonal boron nitride (hBN), as a 2D layered dielectric, has potential for scalable integration into the semiconductor industry. [ 104 , 105 ] [ 104 , 105 ] ^([104,)^(105]){ }^{[104,}{ }^{105]} In 2024, Li et al. [ 106 ] [ 106 ] ^([106]){ }^{[106]} successfully grow high-quality singlecrystal monolayer hBN films on Cu ( 111 ) Cu ( 111 ) Cu(111)\mathrm{Cu}(111) foils by merging the wellaligned, unconventional hexagonal-shaped hBN islands via CVD. The schematic process for preparation hBN was showed in Figure 7a. Trace oxygen during CVD growth modulates the energies of B / N B / N B-//N\mathrm{B}-/ \mathrm{N}-terminated edge, steering hBN island morphology toward hexagonal over triangular shape. Besides, layered 2D dielectrics with higher- κ κ kappa\kappa values above hBN ( κ = 2 4 κ = 2 4 kappa=2-4\kappa=2-4 ) have made great progress in recent years. In 2024, Xu ta al. [ 107 ] [ 107 ] ^([107]){ }^{[107]} reported the controllable synthesis of ultra-thin gadolinium oxychloride (GdOCl) nanosheets via a chloride hydrateassisted CVD method with high dielectric constant of 15.3 . Meanwhile, Shi et al. [ 108 ] [ 108 ] ^([108]){ }^{[108]} recently demonstrated synthesis of wafer-scale(2-inch) single-crystalline LaOCl / SmOCl LaOCl / SmOCl LaOCl//SmOCl\mathrm{LaOCl} / \mathrm{SmOCl} monolayers on c Al 2 O 3 c Al 2 O 3 c-Al_(2)O_(3)\mathrm{c}-\mathrm{Al}_{2} \mathrm{O}_{3} by flux-assisted CVD strategy. In 2023, Chen et al. [ 109 ] [ 109 ] ^([109]){ }^{[109]} demonstrated CVD-grown Bi 2 Bi 2 Bi_(2)\mathrm{Bi}_{2}
CVD 是一种广泛应用于合成各种高质量介电材料作为二维电子器件中栅介质的技术。六方氮化硼(hBN)作为一种二维层状介电材料,具有在半导体行业中实现可扩展集成的潜力。 [ 104 , 105 ] [ 104 , 105 ] ^([104,)^(105]){ }^{[104,}{ }^{105]} 2024 年,Li 等人 [ 106 ] [ 106 ] ^([106]){ }^{[106]} 通过 CVD 将排列良好的非常规六边形 hBN 岛合并,成功在 Cu ( 111 ) Cu ( 111 ) Cu(111)\mathrm{Cu}(111) 箔上生长出高质量的单晶单层 hBN 薄膜。hBN 制备的示意流程如图 7a 所示。CVD 生长过程中微量氧气调节了 B / N B / N B-//N\mathrm{B}-/ \mathrm{N} 端基边缘的能量,使 hBN 岛的形态从三角形转向六边形。此外,近年来,具有高于 hBN 的 κ κ kappa\kappa 值的层状二维介电材料( κ = 2 4 κ = 2 4 kappa=2-4\kappa=2-4 )取得了重大进展。2024 年,Xu 等人 [ 107 ] [ 107 ] ^([107]){ }^{[107]} 报道了一种通过氯化物水合物辅助 CVD 方法可控合成超薄氧氯化镧(GdOCl)纳米片,具有 15.3 的高介电常数。同时,Shi 等人 [ 108 ] [ 108 ] ^([108]){ }^{[108]} 最近通过助熔剂 CVD 策略在 c Al 2 O 3 c Al 2 O 3 c-Al_(2)O_(3)\mathrm{c}-\mathrm{Al}_{2} \mathrm{O}_{3} 上合成了晶圆级(2 英寸)单晶 LaOCl / SmOCl LaOCl / SmOCl LaOCl//SmOCl\mathrm{LaOCl} / \mathrm{SmOCl} 单层。2023 年,Chen 等人 [ 109 ] [ 109 ] ^([109]){ }^{[109]} 展示了 CVD 生长的 Bi 2 Bi 2 Bi_(2)\mathrm{Bi}_{2}

SiO 5 ( κ > 30 ) SiO 5 ( κ > 30 ) SiO_(5)(kappa > 30)\mathrm{SiO}_{5}(\kappa>30), while Tan et al. reported a FinFETs array based on Bi 2 O 2 Se 2 / Bi 2 SeO 5 Bi 2 O 2 Se 2 / Bi 2 SeO 5 Bi_(2)O_(2)Se_(2)//Bi_(2)SeO_(5)\mathrm{Bi}_{2} \mathrm{O}_{2} \mathrm{Se}_{2} / \mathrm{Bi}_{2} \mathrm{SeO}_{5} epitaxial heterostructures exhibiting an electron mobility of 270 cm 2 V 1 s 1 . [ 110 ] 270 cm 2 V 1 s 1 . [ 110 ] 270cm^(2)V^(-1)s^(-1).^([110])270 \mathrm{~cm}^{2} \mathrm{~V}^{-1} \mathrm{~s}^{-1} .{ }^{[110]}
SiO 5 ( κ > 30 ) SiO 5 ( κ > 30 ) SiO_(5)(kappa > 30)\mathrm{SiO}_{5}(\kappa>30) ,而 Tan 等人报道了一种基于 Bi 2 O 2 Se 2 / Bi 2 SeO 5 Bi 2 O 2 Se 2 / Bi 2 SeO 5 Bi_(2)O_(2)Se_(2)//Bi_(2)SeO_(5)\mathrm{Bi}_{2} \mathrm{O}_{2} \mathrm{Se}_{2} / \mathrm{Bi}_{2} \mathrm{SeO}_{5} 外延异质结构的 FinFET 阵列,表现出 270 cm 2 V 1 s 1 . [ 110 ] 270 cm 2 V 1 s 1 . [ 110 ] 270cm^(2)V^(-1)s^(-1).^([110])270 \mathrm{~cm}^{2} \mathrm{~V}^{-1} \mathrm{~s}^{-1} .{ }^{[110]} 的电子迁移率
Nonlayered oxides ( Al 2 O 3 , HfO 2 ) Al 2 O 3 , HfO 2 (Al_(2)O_(3),HfO_(2))\left(\mathrm{Al}_{2} \mathrm{O}_{3}, \mathrm{HfO}_{2}\right) are still an indispensable family in CMOS dielectric layer [ 111 ] [ 111 ] ^([111]){ }^{[111]}, while CVD growth of ultrathin high- κ κ kappa\kappa dielectric that can provide high interface quality and reduce electrically active traps is a significant direction. Very recently, our group demonstrated 2D monocrystalline gadolinium pentoxide ( Gd 2 O 5 ) Gd 2 O 5 (Gd_(2)O_(5))\left(\mathrm{Gd}_{2} \mathrm{O}_{5}\right) synthesized by van der Waals epitaxy on the mica, exhibiting high- κ κ kappa\kappa and wide-bandgap [ 112 ] [ 112 ] ^([112]){ }^{[112]}. Schematic of vdW epitaxial growth and OM image of Gd 2 O 5 Gd 2 O 5 Gd_(2)O_(5)\mathrm{Gd}_{2} \mathrm{O}_{5} nanosheets as shown in Figure 7b. Frequency-dependent capacitance-voltage (C-V) measurements reveal high effective dielectric constant ( ε ε epsi\varepsilon eff 25.5 25.5 ∼25.5\sim 25.5 at 50 kHz ) for 32 nm Gd O 2 O 5 32 nm Gd O 2 O 5 32nmGdO_(2)O_(5)32 \mathrm{~nm} \mathrm{Gd} \mathrm{O}_{2} \mathrm{O}_{5} and gradually decreases with the applied frequency until 0.5 MHz as shown in Figure 7c. The leakage current and breakdown field strength (EBD) in vertical graphite/7.2-nm Gd 2 O 5 / Gd 2 O 5 / Gd_(2)O_(5)//\mathrm{Gd}_{2} \mathrm{O}_{5} / metal device devices as shown in Figure 7d. In 2024, Zhu and colleagues realized ultrathin MgNb 2 O 6 MgNb 2 O 6 MgNb_(2)O_(6)\mathrm{MgNb}_{2} \mathrm{O}_{6} single crystals via buffer-controlled strategy in the nanoscopic space confined by vertically stacked mica nanosheets as shown in Figure 7e. [ 113 ] [ 113 ] ^([113]){ }^{[113]} They fabricated a top-gated monolayer MoS 2 MoS 2 MoS_(2)\mathrm{MoS}_{2} FET array consisting of 20 individual devices(Figure 7f) and exhibit both the average on/off ratio exceeding 10 7 10 7 10^(7)10^{7} and the field-effect mobility with values of 21.5 cm 2 V 1 s 1 21.5 cm 2 V 1 s 1 21.5cm^(2)V^(-1)s^(-1)21.5 \mathrm{~cm}^{2} \mathrm{~V}^{-1} \mathrm{~s}^{-1} as shown in Figure 7g. In 2024, Li et al. [ 114 ] [ 114 ] ^([114]){ }^{[114]} developed a novel elements slow-supply CVD method, wherein the substrate was sandwiched between precursors to grow ultrathin α CaCr 2 O 4 α CaCr 2 O 4 alpha-CaCr_(2)O_(4)\alpha-\mathrm{CaCr}_{2} \mathrm{O}_{4} crystals( 1.2 nm 1.2 nm ∼1.2nm\sim 1.2 \mathrm{~nm} ). Manganese oxide ( Mn 3 O 4 ) Mn 3 O 4 (Mn_(3)O_(4))\left(\mathrm{Mn}_{3} \mathrm{O}_{4}\right) single crystal nanosheets with dielectric constant of 135 was successfully fabricated by Yuan et al. [ 115 ] [ 115 ] ^([115]){ }^{[115]}
非层状氧化物 ( Al 2 O 3 , HfO 2 ) Al 2 O 3 , HfO 2 (Al_(2)O_(3),HfO_(2))\left(\mathrm{Al}_{2} \mathrm{O}_{3}, \mathrm{HfO}_{2}\right) 仍然是 CMOS 介电层 [ 111 ] [ 111 ] ^([111]){ }^{[111]} 中不可或缺的一类材料,而能够提供高界面质量并减少电活性陷阱的超薄高 κ κ kappa\kappa 介电材料的 CVD 生长是一个重要方向。最近,我们团队展示了通过范德华外延法在云母上合成的二维单晶钆五氧化物 ( Gd 2 O 5 ) Gd 2 O 5 (Gd_(2)O_(5))\left(\mathrm{Gd}_{2} \mathrm{O}_{5}\right) ,表现出高 κ κ kappa\kappa 和宽带隙 [ 112 ] [ 112 ] ^([112]){ }^{[112]} 。范德华外延生长示意图及 Gd 2 O 5 Gd 2 O 5 Gd_(2)O_(5)\mathrm{Gd}_{2} \mathrm{O}_{5} 纳米片的光学显微镜图如图 7b 所示。频率依赖的电容-电压(C-V)测量显示 32 nm Gd O 2 O 5 32 nm Gd O 2 O 5 32nmGdO_(2)O_(5)32 \mathrm{~nm} \mathrm{Gd} \mathrm{O}_{2} \mathrm{O}_{5} 的有效介电常数( ε ε epsi\varepsilon eff 25.5 25.5 ∼25.5\sim 25.5 ,50 kHz 时)较高,且随着施加频率增加至 0.5 MHz 逐渐降低,如图 7c 所示。垂直石墨/7.2 纳米 Gd 2 O 5 / Gd 2 O 5 / Gd_(2)O_(5)//\mathrm{Gd}_{2} \mathrm{O}_{5} / 金属器件的漏电流和击穿场强(EBD)如图 7d 所示。2024 年,Zhu 及其同事通过缓冲控制策略,在由垂直堆叠的云母纳米片限制的纳米空间内实现了超薄 MgNb 2 O 6 MgNb 2 O 6 MgNb_(2)O_(6)\mathrm{MgNb}_{2} \mathrm{O}_{6} 单晶体,如图 7e 所示。 [ 113 ] [ 113 ] ^([113]){ }^{[113]} 他们制造了一个由 20 个单独器件组成的顶栅单层 MoS 2 MoS 2 MoS_(2)\mathrm{MoS}_{2} FET 阵列(图 7f),并展示了平均开关比超过 10 7 10 7 10^(7)10^{7} 以及场效应迁移率达到 21.5 cm 2 V 1 s 1 21.5 cm 2 V 1 s 1 21.5cm^(2)V^(-1)s^(-1)21.5 \mathrm{~cm}^{2} \mathrm{~V}^{-1} \mathrm{~s}^{-1} 的性能,如图 7g 所示。2024 年,李等人 [ 114 ] [ 114 ] ^([114]){ }^{[114]} 开发了一种新颖的元素缓慢供应 CVD 方法,其中基底被夹在前驱体之间以生长超薄 α CaCr 2 O 4 α CaCr 2 O 4 alpha-CaCr_(2)O_(4)\alpha-\mathrm{CaCr}_{2} \mathrm{O}_{4} 晶体( 1.2 nm 1.2 nm ∼1.2nm\sim 1.2 \mathrm{~nm} )。袁等人成功制备了介电常数为 135 的锰氧化物 ( Mn 3 O 4 ) Mn 3 O 4 (Mn_(3)O_(4))\left(\mathrm{Mn}_{3} \mathrm{O}_{4}\right) 单晶纳米片 [ 115 ] [ 115 ] ^([115]){ }^{[115]}
Sb-based oxides exhibit molecular crystal structure. In 2020, Yang et al. [ 116 ] [ 116 ] ^([116]){ }^{[116]} synthesized high-quality SbO 1.93 SbO 1.93 SbO_(1.93)\mathrm{SbO}_{1.93} single crystals on re-solidified Ag substrates fabricated by annealing Ag wire-deposited Co foil, achieving uniform Ag diffusion across the surface as shown in Figure 7h. In contrast to conventional oxides, SbO 1.93 SbO 1.93 SbO_(1.93)\mathrm{SbO}_{1.93} exhibits superior electrical insulation performance, demonstrating both an enhanced dielectric constant ( 100 100 ∼100\sim 100 ) and an exceptional breakdown electric field ( 57 MV cm 1 57 MV cm 1 57MVcm^(-1)57 \mathrm{MV} \mathrm{cm}^{-1} ) as shown in Figure 7i. In 2024, Wang et al. [ 117 ] [ 117 ] ^([117]){ }^{[117]} synthesized α Sb 2 O 3 α Sb 2 O 3 alpha-Sb_(2)O_(3)\alpha-\mathrm{Sb}_{2} \mathrm{O}_{3}
Sb 基氧化物表现出分子晶体结构。2020 年,杨等人 [ 116 ] [ 116 ] ^([116]){ }^{[116]} 在通过退火银线沉积的钴箔上制备的再固化银基底上合成了高质量的 SbO 1.93 SbO 1.93 SbO_(1.93)\mathrm{SbO}_{1.93} 单晶,实现了表面均匀的银扩散,如图 7h 所示。与传统氧化物相比, SbO 1.93 SbO 1.93 SbO_(1.93)\mathrm{SbO}_{1.93} 展现出优异的电绝缘性能,表现出增强的介电常数( 100 100 ∼100\sim 100 )和卓越的击穿电场强度( 57 MV cm 1 57 MV cm 1 57MVcm^(-1)57 \mathrm{MV} \mathrm{cm}^{-1} ),如图 7i 所示。2024 年,王等人 [ 117 ] [ 117 ] ^([117]){ }^{[117]} 合成了 α Sb 2 O 3 α Sb 2 O 3 alpha-Sb_(2)O_(3)\alpha-\mathrm{Sb}_{2} \mathrm{O}_{3}

nanosheets( κ = 11.8 , Eg = 3.78 eV κ = 11.8 , Eg = 3.78 eV kappa=11.8,Eg=3.78eV\kappa=11.8, \mathrm{Eg}=3.78 \mathrm{eV} ) via a one-step CVD method, which enabled dual-gated MoS 2 MoS 2 MoS_(2)\mathrm{MoS}_{2} FETs to achieve > 10 8 > 10 8 > 10^(8)>10^{8} on/off ratios.
纳米片( κ = 11.8 , Eg = 3.78 eV κ = 11.8 , Eg = 3.78 eV kappa=11.8,Eg=3.78eV\kappa=11.8, \mathrm{Eg}=3.78 \mathrm{eV} )通过一步 CVD 方法制备,实现了双栅 MoS 2 MoS 2 MoS_(2)\mathrm{MoS}_{2} FET,达到了 > 10 8 > 10 8 > 10^(8)>10^{8} 的开关比。

Figure 7. CVD synthesis of two-dimensional dielectric layers. a) Schematic of the growth process of monolayer hBN merged from wellaligned hexagonal-shaped hBN islands in oxygen-assisted CVD synthesis. b) VdW epitaxial growth and OM image of Gd 2 O 5 Gd 2 O 5 Gd_(2)O_(5)\mathrm{Gd}_{2} \mathrm{O}_{5} nanosheets. Scale bar, 20 μ m 20 μ m 20 mum20 \mu \mathrm{~m}. c) The ε eff ε eff  epsi_("eff ")\varepsilon_{\text {eff }} of 32 nm Gd O 2 32 nm Gd O 2 ∼32nmGdO_(2)\sim 32 \mathrm{~nm} \mathrm{Gd} \mathrm{O}_{2} at various frequencies measured using MIM structure. A 126.5 μ m 2 A 126.5 μ m 2 A~~126.5 mum^(2)A \approx 126.5 \mu \mathrm{~m}^{2}. d) Leakage current density as a function of electric field for a vertical graphite/7.2-nm-thick Gd 2 O 5 / Gd 2 O 5 / Gd_(2)O_(5)//\mathrm{Gd}_{2} \mathrm{O}_{5} / metal device. A 5.6 μ m 2 A 5.6 μ m 2 A~~5.6 mum^(2)A \approx 5.6 \mu \mathrm{~m}^{2}. The dashed lines mark the limits for various electronic applications. DRAM, dynamic random access memory. e) Schematic of the self-limited epitaxy strategy to grow ultrathin MgNb 2 O 6 MgNb 2 O 6 MgNb_(2)O_(6)\mathrm{MgNb}_{2} \mathrm{O}_{6} crystals. f) Schematic and OM images of a top-gated monolayer MoS 2 MoS 2 MoS_(2)\mathrm{MoS}_{2} FET array consisting of 20 individual devices. The width and length of the channel were patterned to be 10 and 4 μ m 4 μ m 4mum4 \mu \mathrm{~m}, respectively. g) Transfer characteristics of all the 20 devices in the array. Inset: corresponding scatter distribution of the recorded mobilities and on/off ratios. h) Schematic of the strategy
图 7. 二维介电层的 CVD 合成。a) 氧辅助 CVD 合成中由排列整齐的六边形 hBN 岛合并而成的单层 hBN 的生长过程示意图。b) Gd 2 O 5 Gd 2 O 5 Gd_(2)O_(5)\mathrm{Gd}_{2} \mathrm{O}_{5} 纳米片的范德华外延生长及光学显微镜图像。比例尺, 20 μ m 20 μ m 20 mum20 \mu \mathrm{~m} 。c) 使用 MIM 结构测量的 32 nm Gd O 2 32 nm Gd O 2 ∼32nmGdO_(2)\sim 32 \mathrm{~nm} \mathrm{Gd} \mathrm{O}_{2} 在不同频率下的 ε eff ε eff  epsi_("eff ")\varepsilon_{\text {eff }} A 126.5 μ m 2 A 126.5 μ m 2 A~~126.5 mum^(2)A \approx 126.5 \mu \mathrm{~m}^{2} 。d) 垂直石墨/7.2 纳米厚 Gd 2 O 5 / Gd 2 O 5 / Gd_(2)O_(5)//\mathrm{Gd}_{2} \mathrm{O}_{5} / 金属器件的泄漏电流密度随电场变化的关系。 A 5.6 μ m 2 A 5.6 μ m 2 A~~5.6 mum^(2)A \approx 5.6 \mu \mathrm{~m}^{2} 。虚线标示了各种电子应用的极限。DRAM,动态随机存取存储器。e) 生长超薄 MgNb 2 O 6 MgNb 2 O 6 MgNb_(2)O_(6)\mathrm{MgNb}_{2} \mathrm{O}_{6} 晶体的自限外延策略示意图。f) 由 20 个单独器件组成的顶栅单层 MoS 2 MoS 2 MoS_(2)\mathrm{MoS}_{2} 场效应晶体管阵列的示意图及光学显微镜图像。通道的宽度和长度分别被设计为 10 和 4 μ m 4 μ m 4mum4 \mu \mathrm{~m} 。g) 阵列中所有 20 个器件的转移特性。插图:记录的迁移率和开关比的散点分布。h) 策略示意图

for the growth of ultrathin antimony oxide. i) Dielectric constant and breakdown voltage of typical high-к materials, graphene oxide, h BN h BN h-BN\mathrm{h}-\mathrm{BN}, and SbO 1.93 SbO 1.93 SbO_(1.93)\mathrm{SbO}_{1.93} a) Reproduced with permission. [ 106 ] [ 106 ] ^([106]){ }^{[106]} 2024, Nature Publishing Group. b-d) Reproduced with permission. [ 12 ] [ 12 ] ^([12]){ }^{[12]} 2024, Nature Publishing Group. e-g) Reproduced with permission. [ 13 ] [ 13 ] ^([13]){ }^{[13]} 2024, Nature Publishing Group. h-i) Reproduced with permission. [ 116 ] [ 116 ] ^([116]){ }^{[116]} 2020, Nature Publishing Group.
超薄氧化锑生长。i) 典型高介电常数材料、氧化石墨烯、 h BN h BN h-BN\mathrm{h}-\mathrm{BN} SbO 1.93 SbO 1.93 SbO_(1.93)\mathrm{SbO}_{1.93} 的介电常数及击穿电压 a) 经许可转载。 [ 106 ] [ 106 ] ^([106]){ }^{[106]} 2024,自然出版集团。b-d) 经许可转载。 [ 12 ] [ 12 ] ^([12]){ }^{[12]} 2024,自然出版集团。e-g) 经许可转载。 [ 13 ] [ 13 ] ^([13]){ }^{[13]} 2024,自然出版集团。h-i) 经许可转载。 [ 116 ] [ 116 ] ^([116]){ }^{[116]} 2020,自然出版集团。

3.2 Synthesis of two-dimensional dielectric layers by Physical vapor deposition (PVD)
3.2 通过物理气相沉积(PVD)合成二维介电层

Parallel to CVD, several advanced dielectrics are synthesized via Physical Vapor Deposition also emerged as promising gate dielectric candidates in 2D electronics. The conventional perovskite oxide SrTiO 3 SrTiO 3 SrTiO_(3)\mathrm{SrTiO}_{3} stands out as a dielectric due to its ultrahigh static permittivity exceeding 300. However, its requirement for high-temperature growth and an epitaxial base poses a challenge for direct integration on 2D material surfaces. Recent advances in combining etching of water-soluble sacrificial layers with mechanical transfer enable the integration of high-к single-crystalline SrTiO 3 SrTiO 3 SrTiO_(3)\mathrm{SrTiO}_{3} onto 2D semiconductors. [ 118 , 119 ] SrTiO 3 [ 118 , 119 ] SrTiO 3 ^([118,119])SrTiO_(3){ }^{[118, ~ 119] ~} \mathrm{SrTiO}_{3} films can be epitaxially grown on a Sr 3 Al 2 O 6 Sr 3 Al 2 O 6 Sr_(3)Al_(2)O_(6)\mathrm{Sr}_{3} \mathrm{Al}_{2} \mathrm{O}_{6}-buffered SrTiO 3 SrTiO 3 SrTiO_(3)\mathrm{SrTiO}_{3} substrate using Pulsed Laser Deposition (PLD). After dissolving the Sr 3 Al 2 O 6 Sr 3 Al 2 O 6 Sr_(3)Al_(2)O_(6)\mathrm{Sr}_{3} \mathrm{Al}_{2} \mathrm{O}_{6} water-soluble sacrificial layer, the released SrTiO 3 SrTiO 3 SrTiO_(3)\mathrm{SrTiO}_{3} films can be transferred onto target substrates with the assistance of the polymer support (Figure 8a). A back-gated field-effect transistor (FET) constructed with an SrTiO 3 SrTiO 3 SrTiO_(3)\mathrm{SrTiO}_{3} gate dielectric and a MoS 2 MoS 2 MoS_(2)\mathrm{MoS}_{2} channel exhibits high on/off ratio of 10 6 10 6 ~~10^(6)\approx 10^{6} and sub-threshold SS as low as 71.5 mV dec 1 71.5 mV dec 1 71.5mVdec^(-1)71.5 \mathrm{mV} \mathrm{dec}^{-1} (Figure 8b). The SrTiO 3 SrTiO 3 SrTiO_(3)\mathrm{SrTiO}_{3} used as gate dielectrics exhibits superior performance in both equivalent oxide thickness (EOT) and SS compared to conventional dielectrics such as CaF 2 CaF 2 CaF_(2)\mathrm{CaF}_{2} and HfO 2 HfO 2 HfO_(2)\mathrm{HfO}_{2} (Figure 8c).
与 CVD 并行,通过物理气相沉积合成的几种先进介电材料也成为二维电子学中有前景的栅介电候选材料。传统的钙钛矿氧化物 SrTiO 3 SrTiO 3 SrTiO_(3)\mathrm{SrTiO}_{3} 因其超过 300 的超高静态介电常数而脱颖而出,成为一种介电材料。然而,其对高温生长和外延基底的需求对直接集成到二维材料表面构成了挑战。最近,将可溶于水的牺牲层蚀刻与机械转移相结合的进展,使得高-к单晶 SrTiO 3 SrTiO 3 SrTiO_(3)\mathrm{SrTiO}_{3} 能够集成到二维半导体上。 [ 118 , 119 ] SrTiO 3 [ 118 , 119 ] SrTiO 3 ^([118,119])SrTiO_(3){ }^{[118, ~ 119] ~} \mathrm{SrTiO}_{3} 薄膜可以通过脉冲激光沉积(PLD)在 Sr 3 Al 2 O 6 Sr 3 Al 2 O 6 Sr_(3)Al_(2)O_(6)\mathrm{Sr}_{3} \mathrm{Al}_{2} \mathrm{O}_{6} 缓冲的 SrTiO 3 SrTiO 3 SrTiO_(3)\mathrm{SrTiO}_{3} 基底上外延生长。溶解 Sr 3 Al 2 O 6 Sr 3 Al 2 O 6 Sr_(3)Al_(2)O_(6)\mathrm{Sr}_{3} \mathrm{Al}_{2} \mathrm{O}_{6} 可溶于水的牺牲层后,释放出的 SrTiO 3 SrTiO 3 SrTiO_(3)\mathrm{SrTiO}_{3} 薄膜可以在聚合物支撑的辅助下转移到目标基底上(图 8a)。采用 SrTiO 3 SrTiO 3 SrTiO_(3)\mathrm{SrTiO}_{3} 栅介电和 MoS 2 MoS 2 MoS_(2)\mathrm{MoS}_{2} 通道构建的背栅场效应晶体管(FET)表现出高达 10 6 10 6 ~~10^(6)\approx 10^{6} 的开关比和低至 71.5 mV dec 1 71.5 mV dec 1 71.5mVdec^(-1)71.5 \mathrm{mV} \mathrm{dec}^{-1} 的亚阈值斜率(图 8b)。 用作栅极介电层的 SrTiO 3 SrTiO 3 SrTiO_(3)\mathrm{SrTiO}_{3} 在等效氧化层厚度(EOT)和亚阈值摆幅(SS)方面表现优于传统介电材料如 CaF 2 CaF 2 CaF_(2)\mathrm{CaF}_{2} HfO 2 HfO 2 HfO_(2)\mathrm{HfO}_{2} (图 8c)。
Similarly, Sr 3 Al 2 O 6 Sr 3 Al 2 O 6 Sr_(3)Al_(2)O_(6)\mathrm{Sr}_{3} \mathrm{Al}_{2} \mathrm{O}_{6} is employed to fabricate large-area, crack-free ( Ba , Sr 2 ) TiO 3 Ba , Sr 2 TiO 3 (Ba,Sr^(2))TiO_(3)\left(\mathrm{Ba}, \mathrm{Sr}^{2}\right) \mathrm{TiO}_{3} films, exhibiting large dielectric permittivity exceeding 3000. [ 120 , 121 ] [ 120 , 121 ] ^([120,121]){ }^{[120,121]} However, these perovskite materials face issues of reduced dielectric property and lower breakdown field as the film-thickness decreases.
同样, Sr 3 Al 2 O 6 Sr 3 Al 2 O 6 Sr_(3)Al_(2)O_(6)\mathrm{Sr}_{3} \mathrm{Al}_{2} \mathrm{O}_{6} 被用来制造大面积、无裂纹的 ( Ba , Sr 2 ) TiO 3 Ba , Sr 2 TiO 3 (Ba,Sr^(2))TiO_(3)\left(\mathrm{Ba}, \mathrm{Sr}^{2}\right) \mathrm{TiO}_{3} 薄膜,表现出超过 3000 的高介电常数。 [ 120 , 121 ] [ 120 , 121 ] ^([120,121]){ }^{[120,121]} 然而,这些钙钛矿材料随着薄膜厚度的减小,面临介电性能降低和击穿场强下降的问题。
The channel material Bi 2 O 2 Se Bi 2 O 2 Se Bi_(2)O_(2)Se\mathrm{Bi}_{2} \mathrm{O}_{2} \mathrm{Se} can be epitaxially grown on the SrTiO 3 SrTiO 3 SrTiO_(3)\mathrm{SrTiO}_{3} surface using Molecular Beam Epitaxy (MBE), facilitating the integration of the 2D Bi 2 O 2 Se / SrTiO 3 Bi 2 O 2 Se / SrTiO 3 Bi_(2)O_(2)Se//SrTiO_(3)\mathrm{Bi}_{2} \mathrm{O}_{2} \mathrm{Se} / \mathrm{SrTiO}_{3} heterojunction onto various substrates (Figure 8d). [ 122 ] [ 122 ] ^([122]){ }^{[122]} The Bi 2 O 2 Se 2 / SrTiO 3 Bi 2 O 2 Se 2 / SrTiO 3 Bi_(2)O_(2)Se^(2)//SrTiO_(3)\mathrm{Bi}_{2} \mathrm{O}_{2} \mathrm{Se}^{2} / \mathrm{SrTiO}_{3} heterostructure is strain-free, ensuring the high quality of the epitaxial films and device integration. Optical images show a back-gated transistor constructed using the transferred Bi 2 O 2 Se / SrTiO 3 Bi 2 O 2 Se / SrTiO 3 Bi_(2)O_(2)Se//SrTiO_(3)\mathrm{Bi}_{2} \mathrm{O}_{2} \mathrm{Se} / \mathrm{SrTiO}_{3} heterostructure on silicon, and the FET exhibits an on/off ratio exceeding 10 4 10 4 10^(4)10^{4}, a minimum SS of 90 mV dec 1 90 mV dec 1 90mVdec^(-1)90 \mathrm{mV} \mathrm{dec}{ }^{-1}, and a leakage current density below 10 3 A cm 2 10 3 A cm 2 10^(-3)Acm^(-2)10^{-3} \mathrm{~A} \mathrm{~cm}^{-2} (Figure 8e).
通道材料 Bi 2 O 2 Se Bi 2 O 2 Se Bi_(2)O_(2)Se\mathrm{Bi}_{2} \mathrm{O}_{2} \mathrm{Se} 可以通过分子束外延(MBE)在 SrTiO 3 SrTiO 3 SrTiO_(3)\mathrm{SrTiO}_{3} 表面上外延生长,促进二维 Bi 2 O 2 Se / SrTiO 3 Bi 2 O 2 Se / SrTiO 3 Bi_(2)O_(2)Se//SrTiO_(3)\mathrm{Bi}_{2} \mathrm{O}_{2} \mathrm{Se} / \mathrm{SrTiO}_{3} 异质结在各种基底上的集成(图 8d)。 [ 122 ] [ 122 ] ^([122]){ }^{[122]} Bi 2 O 2 Se 2 / SrTiO 3 Bi 2 O 2 Se 2 / SrTiO 3 Bi_(2)O_(2)Se^(2)//SrTiO_(3)\mathrm{Bi}_{2} \mathrm{O}_{2} \mathrm{Se}^{2} / \mathrm{SrTiO}_{3} 异质结构无应变,确保了外延薄膜和器件集成的高质量。光学图像显示了一个使用转移的 Bi 2 O 2 Se / SrTiO 3 Bi 2 O 2 Se / SrTiO 3 Bi_(2)O_(2)Se//SrTiO_(3)\mathrm{Bi}_{2} \mathrm{O}_{2} \mathrm{Se} / \mathrm{SrTiO}_{3} 异质结构构建的背栅晶体管,硅基上场效应晶体管表现出超过 10 4 10 4 10^(4)10^{4} 的开关比,最小亚阈值摆幅为 90 mV dec 1 90 mV dec 1 90mVdec^(-1)90 \mathrm{mV} \mathrm{dec}{ }^{-1} ,漏电流密度低于 10 3 A cm 2 10 3 A cm 2 10^(-3)Acm^(-2)10^{-3} \mathrm{~A} \mathrm{~cm}^{-2} (图 8e)。
Simply through Thermal Evaporation (TE), inorganic molecular crystal Sb 2 O 3 Sb 2 O 3 Sb_(2)O_(3)\mathrm{Sb}_{2} \mathrm{O}_{3} can work as a buffer layer on 2D semiconductors, forming a high-quality oxide-to-semiconductor interface, which offers a hydrophilic surface solving the difficulty of integration high-k dielectric via Atomic Layer Deposition (Figure 8f). [ 123 ] [ 123 ] ^([123]){ }^{[123]} The Sb 2 O 3 / HfO 2 Sb 2 O 3 / HfO 2 Sb_(2)O_(3)//HfO_(2)\mathrm{Sb}_{2} \mathrm{O}_{3} / \mathrm{HfO}_{2} heterostructure as a gate dielectric layer shows low EOT of 0.67 nm . Combining with MoS 2 MoS 2 MoS_(2)\mathrm{MoS}_{2} as the channel material, it achieves an on/off ratio exceeding 10 6 10 6 10^(6)10^{6} and an ultra-low SS of 60 mV dec 1 1 ^(-1)^{-1} while operating at an ultra-low gate voltage of 0.4 V (Figure 8g).
仅通过热蒸发(TE),无机分子晶体 Sb 2 O 3 Sb 2 O 3 Sb_(2)O_(3)\mathrm{Sb}_{2} \mathrm{O}_{3} 可以作为二维半导体上的缓冲层,形成高质量的氧化物-半导体界面,提供亲水表面,解决了通过原子层沉积集成高 k 介电层的难题(图 8f)。 [ 123 ] [ 123 ] ^([123]){ }^{[123]} 作为栅介电层的 Sb 2 O 3 / HfO 2 Sb 2 O 3 / HfO 2 Sb_(2)O_(3)//HfO_(2)\mathrm{Sb}_{2} \mathrm{O}_{3} / \mathrm{HfO}_{2} 异质结构表现出 0.67 nm 的低等效氧化层厚度(EOT)。结合 MoS 2 MoS 2 MoS_(2)\mathrm{MoS}_{2} 作为通道材料,实现了超过 10 6 10 6 10^(6)10^{6} 的开关比和超低的 60 mV/dec 亚阈值摆幅(SS) 1 1 ^(-1)^{-1} ,同时在超低栅压 0.4 V 下工作(图 8g)。
Similarly, through thermal evaporation, rare-earth metal fluorides achieve a high dielectric constant of 30 30 ∼30\sim 30 and an ultra-low EOT thickness of 0.15 nm 0.15 nm ∼0.15nm\sim 0.15 \mathrm{~nm}. Based on this, the MoS 2 MoS 2 MoS_(2)\mathrm{MoS}_{2} transistor demonstrates an on/off ratio exceeding 10 8 10 8 10^(8)10^{8}, a low SS of 65 mV dec 1 1 ^(-1)^{-1}, and a leakage current density of 10 6 A cm 2 . [ 124 ] 10 6 A cm 2 . [ 124 ] ∼10^(-6)Acm^(-2).^([124])\sim 10^{-6} \mathrm{~A} \mathrm{~cm}^{-2} .{ }^{[124]}
同样,通过热蒸发,稀土金属氟化物实现了 30 30 ∼30\sim 30 的高介电常数和 0.15 nm 0.15 nm ∼0.15nm\sim 0.15 \mathrm{~nm} 的超低 EOT 厚度。基于此, MoS 2 MoS 2 MoS_(2)\mathrm{MoS}_{2} 晶体管表现出超过 10 8 10 8 10^(8)10^{8} 的开关比,65 mV/dec 的低亚阈值摆幅(SS) 1 1 ^(-1)^{-1} ,以及 10 6 A cm 2 . [ 124 ] 10 6 A cm 2 . [ 124 ] ∼10^(-6)Acm^(-2).^([124])\sim 10^{-6} \mathrm{~A} \mathrm{~cm}^{-2} .{ }^{[124]} 的漏电流密度。

Figure 8. Advanced Dielectrics for 2D Semiconductors via Physical Vapor Deposition. a) Integration of high- SrTiO 3 SrTiO 3 SrTiO_(3)\mathrm{SrTiO}_{3} films by PLD and mechanical transfer. b) Transfer characteristics of SrTiO 3 SrTiO 3 SrTiO_(3)\mathrm{SrTiO}_{3} films as dielectric MoS 2 MoS 2 MoS_(2)\mathrm{MoS}_{2} transistor showing ideal SS and high on/off ratios. c) Comparison of SS and EOT between SrTiO 3 SrTiO 3 SrTiO_(3)\mathrm{SrTiO}_{3} films and other dielectrics, with the red box indicating the IRDS low-power specification for 2028. d) Integration of grown continuously SrTiO 3 / Bi 2 O 2 Se SrTiO 3 / Bi 2 O 2 Se SrTiO_(3)//Bi_(2)O_(2)Se\mathrm{SrTiO}_{3} / \mathrm{Bi}_{2} \mathrm{O}_{2} \mathrm{Se} films s by MBE and mechanical transfer. e) Optical image of SrTiO 3 / Bi 2 O 2 Se SrTiO 3 / Bi 2 O 2 Se SrTiO_(3)//Bi_(2)O_(2)Se\mathrm{SrTiO}_{3} / \mathrm{Bi}_{2} \mathrm{O}_{2} \mathrm{Se} backgated as transistor integrated on silicon and its transfer characteristics. f) Direct deposition of Sb 2 O 3 Sb 2 O 3 Sb_(2)O_(3)\mathrm{Sb}_{2} \mathrm{O}_{3} by TE continuously with HfO 2 HfO 2 HfO_(2)\mathrm{HfO}_{2} by atomic layer deposition (ALD) on MoS 2 MoS 2 MoS_(2)\mathrm{MoS}_{2}. g) Transfer characteristics of Sb 2 O 3 / HfO 2 Sb 2 O 3 / HfO 2 Sb_(2)O_(3)//HfO_(2)\mathrm{Sb}_{2} \mathrm{O}_{3} / \mathrm{HfO}_{2} bilayer as dielectric MoS 2 MoS 2 MoS_(2)\mathrm{MoS}_{2} transistor show near ideal SS and high on/off ratios.
图 8. 通过物理气相沉积制备的二维半导体先进介电材料。a) 通过脉冲激光沉积(PLD)和机械转移集成高- SrTiO 3 SrTiO 3 SrTiO_(3)\mathrm{SrTiO}_{3} 薄膜。b) SrTiO 3 SrTiO 3 SrTiO_(3)\mathrm{SrTiO}_{3} 薄膜作为介电 MoS 2 MoS 2 MoS_(2)\mathrm{MoS}_{2} 晶体管的传输特性,显示理想的亚阈值摆幅(SS)和高开关比。c) SrTiO 3 SrTiO 3 SrTiO_(3)\mathrm{SrTiO}_{3} 薄膜与其他介电材料的 SS 和等效氧化层厚度(EOT)比较,红框标示 2028 年 IRDS 低功耗规范。d) 通过分子束外延(MBE)和机械转移集成连续生长的 SrTiO 3 / Bi 2 O 2 Se SrTiO 3 / Bi 2 O 2 Se SrTiO_(3)//Bi_(2)O_(2)Se\mathrm{SrTiO}_{3} / \mathrm{Bi}_{2} \mathrm{O}_{2} \mathrm{Se} 薄膜。e) SrTiO 3 / Bi 2 O 2 Se SrTiO 3 / Bi 2 O 2 Se SrTiO_(3)//Bi_(2)O_(2)Se\mathrm{SrTiO}_{3} / \mathrm{Bi}_{2} \mathrm{O}_{2} \mathrm{Se} 背栅晶体管集成在硅上的光学图像及其传输特性。f) 通过热蒸发(TE)连续直接沉积 Sb 2 O 3 Sb 2 O 3 Sb_(2)O_(3)\mathrm{Sb}_{2} \mathrm{O}_{3} ,并通过原子层沉积(ALD)沉积 HfO 2 HfO 2 HfO_(2)\mathrm{HfO}_{2} MoS 2 MoS 2 MoS_(2)\mathrm{MoS}_{2} 上。g) Sb 2 O 3 / HfO 2 Sb 2 O 3 / HfO 2 Sb_(2)O_(3)//HfO_(2)\mathrm{Sb}_{2} \mathrm{O}_{3} / \mathrm{HfO}_{2} 双层作为介电 MoS 2 MoS 2 MoS_(2)\mathrm{MoS}_{2} 晶体管的传输特性,显示接近理想的 SS 和高开关比。

3.3 Synthesis of two-dimensional dielectric layers by new fabrication strategies
3.3 通过新型制造策略合成二维介电层

Unlike conventional fabrication methods, recent advancements in fabrication strategies offer state-of-the-art dielectric properties and industrial scalability for
与传统制造方法不同,近期制造策略的进展为二维半导体芯片提供了先进的介电性能和工业规模化的可能性,

wafer-scale integration with 2D semiconductors, paving the way for practical applications in 2D semiconductor chips.
实现了与二维半导体的晶圆级集成,为二维半导体芯片的实际应用铺平了道路。
Metal thermal evaporation technology combined with the intercalation oxidation is employed to stably form an atomically thin, single-crystalline Al 2 O 3 Al 2 O 3 Al_(2)O_(3)\mathrm{Al}_{2} \mathrm{O}_{3} layer on the surface of epitaxial metal alumina films. [ 125 ] [ 125 ] ^([125]){ }^{[125]} An epitaxial aluminum metal film is papered onto a 4-inch graphite/Ge substrate, followed by peeling-off and intercalative oxidation. Through adjusting the oxidation time, the thickness of the Al 2 O 3 Al 2 O 3 Al_(2)O_(3)\mathrm{Al}_{2} \mathrm{O}_{3} layer can be precisely controlled (Figure 9a). During the oxidation process, the oxidation rate decreases from 2 nm h 2 nm h 2nmh2 \mathrm{~nm} \mathrm{~h} ~ to 0.8 nm 1 0.8 nm 1 0.8nm^(-1)0.8 \mathrm{~nm}^{-1} as the oxidation time increased from 1 hour to 12 hours. The Al 2 O 3 Al 2 O 3 Al_(2)O_(3)\mathrm{Al}_{2} \mathrm{O}_{3} layer exhibited an ultra-high breakdown field of 17.4 MV cm 1 17.4 MV cm 1 17.4MVcm^(-1)17.4 \mathrm{MV} \mathrm{cm}^{-1} at a thickness of 2 nm , demonstrating significantly superior properties compared to other dielectrics (Figure 9b). In additionally, when integrated onto a top-gate transistor with MoS 2 MoS 2 MoS_(2)\mathrm{MoS}_{2} as the channel material, it exhibited a SS of 76 mV dec 1 76 mV dec 1 ~~76mVdec^(-1)\approx 76 \mathrm{mV} \mathrm{dec}{ }^{-1}, an on / / /// off ratio of 10 9 10 9 10^(9)10^{9}, and an interface state density of 8.4 × 10 9 cm 2 eV 1 8.4 × 10 9 cm 2 eV 1 8.4 xx10^(9)cm^(-2)eV^(-1)8.4 \times 10^{9} \mathrm{~cm}^{-2} \mathrm{eV}^{-1}. In addition, this method enables the intact transfer of a 4-inch patterned single-crystalline Al 2 O 3 Al 2 O 3 Al_(2)O_(3)\mathrm{Al}_{2} \mathrm{O}_{3} dielectric layer, along with the drain, source, and gate electrode array, onto a MoS 2 MoS 2 MoS_(2)\mathrm{MoS}_{2} film on an Al 2 O 3 Al 2 O 3 Al_(2)O_(3)\mathrm{Al}_{2} \mathrm{O}_{3} substrate, allowing for the direct integration of a wafer-scale device array (Figure 9c).
金属热蒸发技术结合插层氧化被用来稳定地在外延金属氧化铝薄膜表面形成原子级薄的单晶 Al 2 O 3 Al 2 O 3 Al_(2)O_(3)\mathrm{Al}_{2} \mathrm{O}_{3} 层。 [ 125 ] [ 125 ] ^([125]){ }^{[125]} 一层外延铝金属膜被铺设在 4 英寸石墨/Ge 基底上,随后进行剥离和插层氧化。通过调节氧化时间,可以精确控制 Al 2 O 3 Al 2 O 3 Al_(2)O_(3)\mathrm{Al}_{2} \mathrm{O}_{3} 层的厚度(图 9a)。在氧化过程中,氧化速率随着氧化时间从 1 小时增加到 12 小时,从 2 nm h 2 nm h 2nmh2 \mathrm{~nm} \mathrm{~h} ~ 降至 0.8 nm 1 0.8 nm 1 0.8nm^(-1)0.8 \mathrm{~nm}^{-1} Al 2 O 3 Al 2 O 3 Al_(2)O_(3)\mathrm{Al}_{2} \mathrm{O}_{3} 层在厚度为 2 纳米时表现出超高击穿场强 17.4 MV cm 1 17.4 MV cm 1 17.4MVcm^(-1)17.4 \mathrm{MV} \mathrm{cm}^{-1} ,显示出显著优于其他介电材料的性能(图 9b)。此外,当集成到以 MoS 2 MoS 2 MoS_(2)\mathrm{MoS}_{2} 为通道材料的顶栅晶体管上时,表现出 76 mV dec 1 76 mV dec 1 ~~76mVdec^(-1)\approx 76 \mathrm{mV} \mathrm{dec}{ }^{-1} 的亚阈值摆幅(SS)、 10 9 10 9 10^(9)10^{9} 的开关比(on/off ratio)和 8.4 × 10 9 cm 2 eV 1 8.4 × 10 9 cm 2 eV 1 8.4 xx10^(9)cm^(-2)eV^(-1)8.4 \times 10^{9} \mathrm{~cm}^{-2} \mathrm{eV}^{-1} 的界面态密度。 此外,该方法实现了 4 英寸带图案的单晶 Al 2 O 3 Al 2 O 3 Al_(2)O_(3)\mathrm{Al}_{2} \mathrm{O}_{3} 介电层的完整转移,以及漏极、源极和栅极电极阵列,转移到 Al 2 O 3 Al 2 O 3 Al_(2)O_(3)\mathrm{Al}_{2} \mathrm{O}_{3} 基底上的 MoS 2 MoS 2 MoS_(2)\mathrm{MoS}_{2} 薄膜上,实现了晶圆级器件阵列的直接集成(图 9c)。
Utilizing squeeze-printing and surface-tension-driven techniques, an ultrathin oxide layer can naturally form on the surface of liquid Ga metal in an ambient environment, which allows the direct fabrication of an ultrathin and uniform native Ga 2 O 3 Ga 2 O 3 Ga_(2)O_(3)\mathrm{Ga}_{2} \mathrm{O}_{3} layer on the surface of MoS 2 MoS 2 MoS_(2)\mathrm{MoS}_{2} (Figure 9d). [ 126 , 127 ] [ 126 , 127 ] ^([126,127]){ }^{[126, ~ 127] ~} The native Ga 2 O 3 Ga 2 O 3 Ga_(2)O_(3)\mathrm{Ga}_{2} \mathrm{O}_{3} layer exhibits a high dielectric constant of 30 30 ∼30\sim 30 and an EOT of 0.4 nm 0.4 nm ∼0.4nm\sim 0.4 \mathrm{~nm} (Figure 9e). Owing to its exceptional dielectric properties and van der Waals integration, Ga 2 O 3 Ga 2 O 3 Ga_(2)O_(3)\mathrm{Ga}_{2} \mathrm{O}_{3} top-gated MoS 2 MoS 2 MoS_(2)\mathrm{MoS}_{2} transistors achieve an SS of 60 mV dec 1 60 mV dec 1 60mVdec^(-1)60 \mathrm{mV} \mathrm{dec}{ }^{-1}, an on/off ratio of up to 10 8 10 8 10^(8)10^{8}, a break-down field 11 MV cm 1 11 MV cm 1 11MVcm^(-1)11 \mathrm{MV} \mathrm{cm}^{-1} and a low gate leakage current of 4 × 10 7 A cm 2 4 × 10 7 A cm 2 ∼4xx10^(-7)Acm^(-2)\sim 4 \times 10^{-7} \mathrm{~A} \mathrm{~cm}^{-2}. This strategy enables the fabrication of a large-area native Ga 2 O 3 Ga 2 O 3 Ga_(2)O_(3)\mathrm{Ga}_{2} \mathrm{O}_{3} dielectric layer on the surface of MoS 2 MoS 2 MoS_(2)\mathrm{MoS}_{2} films, dramatically simplifying wafer-scale device array integration (Figure 9f).
利用挤压印刷和表面张力驱动技术,在环境条件下液态镓金属表面自然形成超薄氧化层,从而实现了在 MoS 2 MoS 2 MoS_(2)\mathrm{MoS}_{2} 表面直接制备超薄且均匀的本征 Ga 2 O 3 Ga 2 O 3 Ga_(2)O_(3)\mathrm{Ga}_{2} \mathrm{O}_{3} 层(图 9d)。 [ 126 , 127 ] [ 126 , 127 ] ^([126,127]){ }^{[126, ~ 127] ~} 该本征 Ga 2 O 3 Ga 2 O 3 Ga_(2)O_(3)\mathrm{Ga}_{2} \mathrm{O}_{3} 层表现出高介电常数 30 30 ∼30\sim 30 和等效氧化层厚度(EOT)为 0.4 nm 0.4 nm ∼0.4nm\sim 0.4 \mathrm{~nm} (图 9e)。凭借其卓越的介电性能和范德华集成, Ga 2 O 3 Ga 2 O 3 Ga_(2)O_(3)\mathrm{Ga}_{2} \mathrm{O}_{3} 顶栅 MoS 2 MoS 2 MoS_(2)\mathrm{MoS}_{2} 晶体管实现了 60 mV dec 1 60 mV dec 1 60mVdec^(-1)60 \mathrm{mV} \mathrm{dec}{ }^{-1} 的亚阈值摆幅(SS)、高达 10 8 10 8 10^(8)10^{8} 的开关比、 11 MV cm 1 11 MV cm 1 11MVcm^(-1)11 \mathrm{MV} \mathrm{cm}^{-1} 的击穿场强以及 4 × 10 7 A cm 2 4 × 10 7 A cm 2 ∼4xx10^(-7)Acm^(-2)\sim 4 \times 10^{-7} \mathrm{~A} \mathrm{~cm}^{-2} 的低栅极漏电流。该策略实现了在 MoS 2 MoS 2 MoS_(2)\mathrm{MoS}_{2} 薄膜表面制备大面积本征 Ga 2 O 3 Ga 2 O 3 Ga_(2)O_(3)\mathrm{Ga}_{2} \mathrm{O}_{3} 介电层,极大简化了晶圆级器件阵列的集成(图 9f)。
Another interesting method for dielectric layers is synchronizing the thermal decomposition of metal salts and water-assisted forming, which allows for the
另一种用于介电层的有趣方法是同步热分解金属盐和水辅助成形,这种方法允许

mechanical exfoliation of 2D metal oxide flakes, enabling the fabrication of a wide variety of metal oxides, as well as ferroelectric materials. [ 128 ] [ 128 ] ^([128]){ }^{[128]}
机械剥离二维金属氧化物薄片,实现多种金属氧化物以及铁电材料的制造。 [ 128 ] [ 128 ] ^([128]){ }^{[128]}
2D perovskite oxide Sr 2 Nb 3 O 10 Sr 2 Nb 3 O 10 Sr_(2)Nb_(3)O_(10)\mathrm{Sr}_{2} \mathrm{Nb}_{3} \mathrm{O}_{10} nanosheets were synthesized via calcination and liquid-phase exfoliation, exhibiting a high dielectric constant (24.6) and a moderate bandgap, making them suitable as photoactive high- κ κ kappa\kappa dielectrics for integration into 2D optoelectronic devices. [ 129 ] [ 129 ] ^([129]){ }^{[129]}
通过煅烧和液相剥离合成了二维钙钛矿氧化物 Sr 2 Nb 3 O 10 Sr 2 Nb 3 O 10 Sr_(2)Nb_(3)O_(10)\mathrm{Sr}_{2} \mathrm{Nb}_{3} \mathrm{O}_{10} 纳米片,表现出高介电常数(24.6)和适中的带隙,使其适合作为光活性高- κ κ kappa\kappa 介电材料集成到二维光电子器件中。 [ 129 ] [ 129 ] ^([129]){ }^{[129]}
An amorphous, transferable high-к (42.9) copper calcium titanate films are synthesized via a wet chemistry-based method. [ 130 ] [ 130 ] ^([130]){ }^{[130]} Their transferable nature enables harmless integration into 2 D semiconductors, and visible light active properties enables an electrically controlled, optically activated nonvolatile floating gate.
通过湿化学方法合成了非晶态、可转移的高κ(42.9)铜钙钛酸盐薄膜。 [ 130 ] [ 130 ] ^([130]){ }^{[130]} 它们的可转移特性使其能够无害地集成到二维半导体中,且可见光活性特性使其成为电控、光激活的非易失性浮栅。

Figure 9. Advanced dielectrics via new fabrication strategies for wafer-scale integration. a) Fabrication of single-crystalline Al 2 O 3 Al 2 O 3 Al_(2)O_(3)\mathrm{Al}_{2} \mathrm{O}_{3} dielectric through epitaxial lift-off and intercalative oxidation. b) The breakdown field as a function of film thickness for various dielectrics. c) A photograph of a 4-inch CVD-MoS 2 /sapphire
图 9. 通过新型制造策略实现晶圆级集成的先进介电材料。a) 通过外延剥离和插层氧化制备单晶 Al 2 O 3 Al 2 O 3 Al_(2)O_(3)\mathrm{Al}_{2} \mathrm{O}_{3} 介电层。b) 不同介电材料的击穿场强随薄膜厚度的变化。c) 4 英寸 CVD-MoS2/蓝宝石晶圆的照片

wafer with Al 2 O 3 Al 2 O 3 Al_(2)O_(3)\mathrm{Al}_{2} \mathrm{O}_{3} top-gated FET arrays, along with magnified optical images from the adjacent red box. d) Schematic illustration of surface-tension-driven integration of Ga 2 O 3 Ga 2 O 3 Ga_(2)O_(3)\mathrm{Ga}_{2} \mathrm{O}_{3} on 2D semiconductors for top-gated FET. e) Breakdown field as a function of dielectric constant, compared with other dielectrics. f) Image of integration on a 3-inch wafer using wafer-scale CVD MoS 2 MoS 2 MoS_(2)\mathrm{MoS}_{2}. g) SEM image of 25 top-gated FETs on MoS 2 MoS 2 MoS_(2)\mathrm{MoS}_{2} with a Ga 2 O 3 Ga 2 O 3 Ga_(2)O_(3)\mathrm{Ga}_{2} \mathrm{O}_{3} dielectric layer, with the black box highlighting an enlarged false-color SEM image. scale bars: 200 μ m 200 μ m 200 mum200 \mu \mathrm{~m} (left) and 50 μ m 50 μ m 50 mum50 \mu \mathrm{~m} (right) ©; 100 μ m 100 μ m 100 mum100 \mu \mathrm{~m} (left), 10 μ m 10 μ m 10 mum10 \mu \mathrm{~m} (right) .
带有 Al 2 O 3 Al 2 O 3 Al_(2)O_(3)\mathrm{Al}_{2} \mathrm{O}_{3} 顶栅场效应晶体管阵列的晶圆,以及来自相邻红色框的放大光学图像。d) 表面张力驱动的 Ga 2 O 3 Ga 2 O 3 Ga_(2)O_(3)\mathrm{Ga}_{2} \mathrm{O}_{3} 在二维半导体上集成用于顶栅场效应晶体管的示意图。e) 击穿场强与介电常数的关系,与其他介电材料比较。f) 使用晶圆级 CVD MoS 2 MoS 2 MoS_(2)\mathrm{MoS}_{2} 在 3 英寸晶圆上的集成图像。g) 25 个顶栅场效应晶体管在 MoS 2 MoS 2 MoS_(2)\mathrm{MoS}_{2} 上的扫描电子显微镜图像,带有 Ga 2 O 3 Ga 2 O 3 Ga_(2)O_(3)\mathrm{Ga}_{2} \mathrm{O}_{3} 介电层,黑色框突出显示放大的伪彩色扫描电子显微镜图像。比例尺: 200 μ m 200 μ m 200 mum200 \mu \mathrm{~m} (左)和 50 μ m 50 μ m 50 mum50 \mu \mathrm{~m} (右)©; 100 μ m 100 μ m 100 mum100 \mu \mathrm{~m} (左), 10 μ m 10 μ m 10 mum10 \mu \mathrm{~m} (右)。

4. Contact engineering for 2D electronics
4. 2D 电子学的接触工程

4.1 Making vdW contact between metals and 2D semiconductors
4.1 制备金属与二维半导体之间的范德华接触

The electrical contact between the metal and channel is crucial for FET since it depends the contact resistance and thus influences the device performance such as the on/off ratio and the carrier mobility. [ 131 ] [ 131 ] ^([131]){ }^{[131]} However, owing to the atomical thickness and dangling-bond-free surface of 2D semiconductor, the direct deposition of metals can result in the defects and damage to the 2D semiconductor channel, leading to higher contact resistance and thus degrade the FET performance. [ 34 , 132 ] [ 34 , 132 ] ^([34,132]){ }^{[34,132]} Furthermore, the work function and the density of states of the contact materials also plays an important role. [ 133 ] [ 134 ] [ 133 ] [ 134 ] ^([133])^([134]){ }^{[133]}{ }^{[134]} A metal with proper work function corresponding to the energy band of the semiconductor can reduce the Schottky barrier and lead to ohmic contact. To create clean and ohmic contact in 2D FET, methods such as vdW transfer electrode, [ 132 , 135 ] [ 132 , 135 ] ^([132,135]){ }^{[132, ~ 135]} high vacuum and low temperature evaporation, [ 21 ] [ 21 ] ^([21]){ }^{[21]} work function engineering, [ 136 ] [ 136 ] ^([136]){ }^{[136]} semimetal contact and doping, [ 137 , 138 ] [ 137 , 138 ] ^([137,138]){ }^{[137,138]} have been developed.
金属与通道之间的电接触对于场效应晶体管(FET)至关重要,因为它决定了接触电阻,从而影响器件性能,如开关比和载流子迁移率。 [ 131 ] [ 131 ] ^([131]){ }^{[131]} 然而,由于二维半导体的原子厚度和无悬挂键表面,金属的直接沉积可能导致二维半导体通道的缺陷和损伤,导致更高的接触电阻,从而降低 FET 性能。 [ 34 , 132 ] [ 34 , 132 ] ^([34,132]){ }^{[34,132]} 此外,接触材料的功函数和态密度也起着重要作用。 [ 133 ] [ 134 ] [ 133 ] [ 134 ] ^([133])^([134]){ }^{[133]}{ }^{[134]} 具有与半导体能带相对应的适当功函数的金属可以降低肖特基势垒,实现欧姆接触。为了在二维 FET 中创建干净且欧姆的接触,已经开发了诸如范德华转移电极, [ 132 , 135 ] [ 132 , 135 ] ^([132,135]){ }^{[132, ~ 135]} 高真空低温蒸发, [ 21 ] [ 21 ] ^([21]){ }^{[21]} 功函数工程, [ 136 ] [ 136 ] ^([136]){ }^{[136]} 半金属接触和掺杂, [ 137 , 138 ] [ 137 , 138 ] ^([137,138]){ }^{[137,138]} 等方法。
In 2018, Liu et al. adopted transferring metal films onto 2D semiconductors for resolving the defects caused by direct evaporation in contacts between 2D materials and electrodes. [ 132 ] [ 132 ] ^([132]){ }^{[132]} Instead of evaporating the metals on 2D materials that may cause damages and defects, they first deposited the metals on silicon substrates. These metal electrodes with atomically flat surface can be mechanically released from the silicon and be transferred onto the MoS 2 MoS 2 MoS_(2)\mathrm{MoS}_{2} channel. As shown in Figure 10a-d, a clean and sharp interface was formed between the transferred Au and 2D semiconductor, while
2018 年,Liu 等人采用将金属薄膜转移到二维半导体上,以解决二维材料与电极接触中直接蒸发引起的缺陷。 [ 132 ] [ 132 ] ^([132]){ }^{[132]} 他们没有直接在二维材料上蒸发金属以避免损伤和缺陷,而是先将金属沉积在硅基底上。这些具有原子级平整表面的金属电极可以从硅基底机械释放并转移到 MoS 2 MoS 2 MoS_(2)\mathrm{MoS}_{2} 通道上。如图 10a-d 所示,转移的 Au 与二维半导体之间形成了干净且锐利的界面,而

obvious defects were observed in evaporated Au / MoS 2 Au / MoS 2 Au//MoS_(2)\mathrm{Au} / \mathrm{MoS}_{2} interface. Moreover, this transferred electrode method can avoid direct chemical bonding between metals and semiconductors. As illustrated in Figure 10e, the FET with evaporated Pt electrodes showed n-type conductivity, indicating a large n-type Schottky barrier. A p-type conductivity and ohmic contact were observed in FET with transferred Pt electrodes, which demonstrates the advantages of this approach. (Figure 10f) In another work, 2D diodes with transferred electrodes showed performance close to the intrinsic exciton physics limit. [ 135 ] [ 135 ] ^([135]){ }^{[135]} In recent, this method has been utilized to build wafer-scale 2D transistors and 3D integration of 2D semiconductors, indicating its potential in practical applications. [ 139 , 140 ] [ 139 , 140 ] ^([139,140]){ }^{[139,140]} Wang et al. adopted soft metal In to form vdW contact with monolayer MoS 2 MoS 2 MoS_(2)\mathrm{MoS}_{2} without chemical bonding. [ 141 ] [ 141 ] ^([141]){ }^{[141]} As revealed in Figure 10g,h, ideal interface was formed between In and MoS 2 MoS 2 MoS_(2)\mathrm{MoS}_{2}. FET fabricated by this technology shows low contact resistance ( 3.3 ± 0.3 k Ω μ m ) ( 3.3 ± 0.3 k Ω μ m ) (3.3+-0.3kOmega mum)(3.3 \pm 0.3 \mathrm{k} \Omega \mu \mathrm{m}) and relative high mobility ( 167 ± 20 167 ± 20 167+-20167 \pm 20 cm 2 V 1 s 1 cm 2 V 1 s 1 cm^(2)V^(-1)s^(-1)\mathrm{cm}^{2} \mathrm{~V}^{-1} \mathrm{~s}^{-1} ). (Figure 10i,j) The soft nature of Indium (In) enable the formation of high-quality interfaces with monolayer semiconductors and facilitate alloying with different metals to modulate the work function of electrodes, which helps reduce the contact resistance and adjust the polarity of 2D FETs.
在蒸发的 Au / MoS 2 Au / MoS 2 Au//MoS_(2)\mathrm{Au} / \mathrm{MoS}_{2} 界面观察到明显缺陷。此外,这种转移电极方法可以避免金属与半导体之间的直接化学键合。如图 10e 所示,采用蒸发 Pt 电极的场效应晶体管(FET)表现出 n 型导电性,表明存在较大的 n 型肖特基势垒。采用转移 Pt 电极的 FET 表现出 p 型导电性和欧姆接触,展示了该方法的优势。(图 10f)在另一项工作中,带有转移电极的二维二极管表现出接近本征激子物理极限的性能。 [ 135 ] [ 135 ] ^([135]){ }^{[135]} 近期,该方法已被用于构建晶圆级二维晶体管和二维半导体的三维集成,显示出其在实际应用中的潜力。 [ 139 , 140 ] [ 139 , 140 ] ^([139,140]){ }^{[139,140]} Wang 等人采用软金属 In 与单层 MoS 2 MoS 2 MoS_(2)\mathrm{MoS}_{2} 形成范德华接触,无化学键合。 [ 141 ] [ 141 ] ^([141]){ }^{[141]} 如图 10g,h 所示,In 与 MoS 2 MoS 2 MoS_(2)\mathrm{MoS}_{2} 之间形成了理想界面。采用该技术制造的 FET 表现出低接触电阻 ( 3.3 ± 0.3 k Ω μ m ) ( 3.3 ± 0.3 k Ω μ m ) (3.3+-0.3kOmega mum)(3.3 \pm 0.3 \mathrm{k} \Omega \mu \mathrm{m}) 和相对较高的迁移率( 167 ± 20 167 ± 20 167+-20167 \pm 20 cm 2 V 1 s 1 cm 2 V 1 s 1 cm^(2)V^(-1)s^(-1)\mathrm{cm}^{2} \mathrm{~V}^{-1} \mathrm{~s}^{-1} )。 (图 10i,j)铟(In)的柔软特性使其能够与单层半导体形成高质量界面,并促进与不同金属的合金化以调节电极的功函数,这有助于降低接触电阻并调整二维场效应晶体管(2D FETs)的极性。
In 2023, Kwon et al. adopted an intercalation method to make clean vdW contact between electrodes and 2D semiconductors. [ 142 ] [ 142 ] ^([142]){ }^{[142]} As revealed in Figure 10k, before depositing Au on the semiconductor, they first deposited a Se layer. This Se layer can be moved by annealing in vacuum at 150 C 150 C 150^(@)C150^{\circ} \mathrm{C}, resulting in a damage-free vdW contact between Au and the semiconductor. As illustrated in Figure, the 2D FET with vdW Au contact showed p-type conductivity with on/off ratio above 10 6 10 6 10^(6)10^{6} (Figure 101). In addition to the aforementioned methodologies for constructing vdW contacts in 2D FETs, emerging research has focused on investigating interfacial interactions between vdW materials and 2D semiconductors. [ 143 , 144 ] [ 143 , 144 ] ^([143,144]){ }^{[143,144]} These transistors exhibit enhanced carrier mobility and low contact resistance, benefiting from the clean vdW metal-semiconductor interface.
2023 年,Kwon 等人采用插层法在电极与二维半导体之间形成干净的范德华(vdW)接触。 [ 142 ] [ 142 ] ^([142]){ }^{[142]} 如图 10k 所示,在将金(Au)沉积到半导体上之前,他们首先沉积了一层硒(Se)。这层硒通过在真空中退火至 150 C 150 C 150^(@)C150^{\circ} \mathrm{C} 后可以移动,从而实现了 Au 与半导体之间无损伤的 vdW 接触。如图所示,具有 vdW Au 接触的二维场效应晶体管表现出 p 型导电性,开关比超过 10 6 10 6 10^(6)10^{6} (图 101)。除了上述构建二维场效应晶体管 vdW 接触的方法外,最新研究还聚焦于探讨 vdW 材料与二维半导体之间的界面相互作用。 [ 143 , 144 ] [ 143 , 144 ] ^([143,144]){ }^{[143,144]} 这些晶体管因干净的 vdW 金属-半导体界面而表现出增强的载流子迁移率和低接触电阻。

Figure 10. Making vdW contact between metals and 2D semiconductors. a-b) cross-sectional schematic and TEM image of the interface between transferred Au and MoS 2 MoS 2 MoS_(2)\mathrm{MoS}_{2}. c-d, cross-sectional schematic and TEM image of the interface between evaporated Au and MoS 2 MoS 2 MoS_(2)\mathrm{MoS}_{2}. e-f) Transfer characteristic curves of FETs with evaporated Pt and transferred Pt electrodes, respectively. g-h) cross-sectional TEM image of the interface between In and MoS 2 MoS 2 MoS_(2)\mathrm{MoS}_{2}. i, contact resistance of FET that composed of In / MoS 2 In / MoS 2 In//MoS_(2)\mathrm{In} / \mathrm{MoS}_{2} contact. j) Transfer characteristic curves of monolayer MoS 2 MoS 2 MoS_(2)\mathrm{MoS}_{2} FET with In / Au In / Au In//Au\mathrm{In} / \mathrm{Au} electrodes. k ) schematic of a Se intercalation and annealing process for vdW Au / WSe 2 vdW Au / WSe 2 vdWAu//WSe_(2)\mathrm{vdW} \mathrm{Au} / \mathrm{WSe}_{2} contact. 1) Transfer characteristic curves of FETs with evaporated and vdW Au electrodes.
图 10. 在金属与二维半导体之间形成范德华接触。a-b) 转移的 Au 与 MoS 2 MoS 2 MoS_(2)\mathrm{MoS}_{2} 界面的截面示意图和透射电子显微镜(TEM)图像。c-d) 蒸发 Au 与 MoS 2 MoS 2 MoS_(2)\mathrm{MoS}_{2} 界面的截面示意图和 TEM 图像。e-f) 具有蒸发 Pt 和转移 Pt 电极的场效应晶体管(FET)的转移特性曲线。g-h) In 与 MoS 2 MoS 2 MoS_(2)\mathrm{MoS}_{2} 界面的截面 TEM 图像。i) 由 In / MoS 2 In / MoS 2 In//MoS_(2)\mathrm{In} / \mathrm{MoS}_{2} 接触组成的 FET 的接触电阻。j) 单层 MoS 2 MoS 2 MoS_(2)\mathrm{MoS}_{2} FET 与 In / Au In / Au In//Au\mathrm{In} / \mathrm{Au} 电极的转移特性曲线。k) vdW Au / WSe 2 vdW Au / WSe 2 vdWAu//WSe_(2)\mathrm{vdW} \mathrm{Au} / \mathrm{WSe}_{2} 接触的硒插层和退火工艺示意图。l) 具有蒸发和范德华 Au 电极的 FET 的转移特性曲线。

4.2 Contact material engineering for 2D transistors
4.2 二维晶体管的接触材料工程

To reduce the Schottky barrier in metal-semiconductor contacts, electrodes with proper work functions should be considered in 2D metal-semiconductor contact. In addition of the work function, the formation of metal-induced gap states (MIGS) in the semiconductor bandgap arises from the penetration of metallic wave functions into the semiconductor, which hybridize with and perturb the intrinsic wave functions
为了降低金属-半导体接触中的肖特基势垒,应考虑具有适当功函数的电极用于二维金属-半导体接触。除了功函数之外,金属诱导的带隙态(MIGS)在半导体带隙中的形成源于金属波函数渗透到半导体中,这些波函数与半导体的本征波函数杂化并扰动其性质。

of the semiconductor. This phenomenon may also lead to the Fermi pinning and high contact resistance (Figure 11a,b). [ 133 , 145 ] [ 133 , 145 ] ^([133,145]){ }^{[133,145]} Different from metals, semimetals with nearly zero density of states can largely eliminate the MIGS (Figure 11c,d). To suppress the gap states at the interface of metals and 2D semiconductors, Shen et al. adopted semimetal Bismuth (Bi) as the contact electrodes in 2D FETs. [ 133 ] [ 133 ] ^([133]){ }^{[133]} As illustrated in Figure 11e, the FET with Bi electrodes shows higher on/off ratio than that of metal electrodes. Moreover, an ultralow contact resistance of 123 Ω μ m 123 Ω μ m ∼123 Omega mum\sim 123 \Omega \mu \mathrm{~m} was realized (Figure 11f). In 2023, Li et al. utilized semimetal Antimony (Sb) as electrodes for 2D FET. [ 21 ] [ 21 ] ^([21]){ }^{[21]} They found that the crystal direction of Sb played an important role in the contact between the electrode and the semiconductor. Compared to Sb ( 0001 ) , Sb ( 01 1 2 ) Sb ( 0001 ) , Sb ( 01 1 ¯ 2 ) Sb(0001),Sb(01 bar(1)2)\mathrm{Sb}(0001), \mathrm{Sb}(01 \overline{1} 2) exhibits stronger hybridization and vdW interaction with 2D semiconductors, enabling enhanced electron injection and achieving lower contact resistance approaching the quantum limit (Figure g,h). They realized a contact resistance as low as 42 Ω μ m 42 Ω μ m 42 Omega mum42 \Omega \mu \mathrm{~m} (Figure 11i,j). Researchers also have demonstrated wafer-scale MoS 2 MoS 2 MoS_(2)\mathrm{MoS}_{2} transistor arrays with exceptional performance, marking significant progress toward practical applications of 2D electronics. The development of p-type 2D transistors is critical for complementary metal-oxide-semiconductor (CMOS) integrated circuits. Wang et al. achieved p-type conduction in MoS 2 MoS 2 MoS_(2)\mathrm{MoS}_{2} and WSe 2 WSe 2 WSe_(2)\mathrm{WSe}_{2}-based devices by selecting high-work-function metals like Pt and Pd. [ 138 ] [ 138 ] ^([138]){ }^{[138]} Through precise control of evaporation temperature and pressure, they established clean metal-semiconductor interfaces, minimizing damage typically induced by conventional deposition methods. This approach yielded transistors with relatively low contact resistance ( 3.3 k Ω μ m ) ( 3.3 k Ω μ m ) (∼3.3kOmega mum)(\sim 3.3 \mathrm{k} \Omega \mu \mathrm{m}) and high hole mobility ( 190 cm 2 V 1 s 1 ) 190 cm 2 V 1 s 1 (∼190cm^(2)*V^(-1)*s^(-1))\left(\sim 190 \mathrm{~cm}^{2} \cdot \mathrm{~V}^{-1} \cdot \mathrm{~s}^{-1}\right). In 2024, Li et al. synthesized composition-tunable VS 2 x Se 2 ( 1 x ) ( 0 x 1 ) VS 2 x Se 2 ( 1 x ) ( 0 x 1 ) VS_(2x)Se_(2(1-x))(0 <= x <= 1)\mathrm{VS}_{2 \mathrm{x}} \mathrm{Se}_{2(1-\mathrm{x})}(0 \leq \mathrm{x} \leq 1) nanosheets through controlling the growth temperature via CVD (Figure 11m). [ 136 ] [ 136 ] ^([136]){ }^{[136]} These alloys exhibited composition-dependent surface potentials and work functions (from 4.79 ± 0.01 eV 4.79 ± 0.01 eV 4.79+-0.01eV4.79 \pm 0.01 \mathrm{eV} to 4.64 ± 0.01 eV 4.64 ± 0.01 eV 4.64+-0.01eV4.64 \pm 0.01 \mathrm{eV} ). The tunable work functions of 2 D alloys can help reduce the Schottky barrier when contacting with different 2D semiconductors. Leveraging this tunability, they engineered heterostructures where VSe 2 / WSe 2 VSe 2 / WSe 2 VSe_(2)//WSe_(2)\mathrm{VSe}_{2} / \mathrm{WSe}_{2} combinations demonstrated robust p-type characteristics, while VS 2 / MoS 2 VS 2 / MoS 2 VS_(2)//MoS_(2)\mathrm{VS}_{2} / \mathrm{MoS}_{2}
半导体的。这种现象也可能导致费米钉扎和高接触电阻(图 11a,b)。 [ 133 , 145 ] [ 133 , 145 ] ^([133,145]){ }^{[133,145]} 与金属不同,几乎零态密度的半金属可以在很大程度上消除 MIGS(图 11c,d)。为了抑制金属与二维半导体界面的能隙态,Shen 等人采用了半金属铋(Bi)作为二维场效应晶体管(FET)的接触电极。 [ 133 ] [ 133 ] ^([133]){ }^{[133]} 如图 11e 所示,采用 Bi 电极的 FET 显示出比金属电极更高的开关比。此外,实现了超低接触电阻 123 Ω μ m 123 Ω μ m ∼123 Omega mum\sim 123 \Omega \mu \mathrm{~m} (图 11f)。2023 年,Li 等人利用半金属锑(Sb)作为二维 FET 的电极。 [ 21 ] [ 21 ] ^([21]){ }^{[21]} 他们发现 Sb 的晶体方向在电极与半导体的接触中起着重要作用。与 Sb ( 0001 ) , Sb ( 01 1 2 ) Sb ( 0001 ) , Sb ( 01 1 ¯ 2 ) Sb(0001),Sb(01 bar(1)2)\mathrm{Sb}(0001), \mathrm{Sb}(01 \overline{1} 2) 相比, Sb ( 0001 ) , Sb ( 01 1 2 ) Sb ( 0001 ) , Sb ( 01 1 ¯ 2 ) Sb(0001),Sb(01 bar(1)2)\mathrm{Sb}(0001), \mathrm{Sb}(01 \overline{1} 2) 与二维半导体表现出更强的杂化和范德华相互作用,增强了电子注入,实现了接近量子极限的更低接触电阻(图 g,h)。他们实现了低至 42 Ω μ m 42 Ω μ m 42 Omega mum42 \Omega \mu \mathrm{~m} 的接触电阻(图 11i,j)。 研究人员还展示了具有卓越性能的晶圆级 MoS 2 MoS 2 MoS_(2)\mathrm{MoS}_{2} 晶体管阵列,标志着二维电子学实际应用的重大进展。p 型二维晶体管的发展对于互补金属氧化物半导体(CMOS)集成电路至关重要。Wang 等人通过选择高功函数金属如 Pt 和 Pd,实现了基于 MoS 2 MoS 2 MoS_(2)\mathrm{MoS}_{2} WSe 2 WSe 2 WSe_(2)\mathrm{WSe}_{2} 器件的 p 型导电。 [ 138 ] [ 138 ] ^([138]){ }^{[138]} 通过精确控制蒸发温度和压力,他们建立了干净的金属-半导体界面,最大限度地减少了传统沉积方法通常引起的损伤。这种方法产生了具有相对较低接触电阻 ( 3.3 k Ω μ m ) ( 3.3 k Ω μ m ) (∼3.3kOmega mum)(\sim 3.3 \mathrm{k} \Omega \mu \mathrm{m}) 和高空穴迁移率 ( 190 cm 2 V 1 s 1 ) 190 cm 2 V 1 s 1 (∼190cm^(2)*V^(-1)*s^(-1))\left(\sim 190 \mathrm{~cm}^{2} \cdot \mathrm{~V}^{-1} \cdot \mathrm{~s}^{-1}\right) 的晶体管。2024 年,Li 等人通过控制 CVD 生长温度合成了成分可调的 VS 2 x Se 2 ( 1 x ) ( 0 x 1 ) VS 2 x Se 2 ( 1 x ) ( 0 x 1 ) VS_(2x)Se_(2(1-x))(0 <= x <= 1)\mathrm{VS}_{2 \mathrm{x}} \mathrm{Se}_{2(1-\mathrm{x})}(0 \leq \mathrm{x} \leq 1) 纳米片(图 11m)。 [ 136 ] [ 136 ] ^([136]){ }^{[136]} 这些合金表现出成分依赖的表面电势和功函数(从 4.79 ± 0.01 eV 4.79 ± 0.01 eV 4.79+-0.01eV4.79 \pm 0.01 \mathrm{eV} 4.64 ± 0.01 eV 4.64 ± 0.01 eV 4.64+-0.01eV4.64 \pm 0.01 \mathrm{eV} )。二维合金的可调功函数有助于在与不同二维半导体接触时降低肖特基势垒。 利用这种可调性,他们设计了异质结构,其中 VSe 2 / WSe 2 VSe 2 / WSe 2 VSe_(2)//WSe_(2)\mathrm{VSe}_{2} / \mathrm{WSe}_{2} 种组合表现出强健的 p 型特性,而 VS 2 / MoS 2 VS 2 / MoS 2 VS_(2)//MoS_(2)\mathrm{VS}_{2} / \mathrm{MoS}_{2}

configurations showed n-type behavior, as illustrated in their device schematics (Figure 11n,o).
配置表现出 n 型行为,如其器件示意图(图 11n,o)所示。

Figure 11. Contact material engineering for 2D transistors. a-b) the density of states and energy band of semiconductor and normal metal. c-d) the density of states and energy band of semiconductor and semimetal. e) Transfer characteristic curves of monolayer MoS 2 MoS 2 MoS_(2)\mathrm{MoS}_{2} FETs with Bi , Ni Bi , Ni Bi,Ni\mathrm{Bi}, \mathrm{Ni} and Ti contacts. f) contact resistance of Bi MoS 2 Bi MoS 2 Bi-MoS_(2)\mathrm{Bi}-\mathrm{MoS}_{2} FET. g-h) cross-sectional TEM image of the interface between Sb ( 01 1 2 ) Sb ( 01 1 ¯ 2 ) Sb(01 bar(1)2)\mathrm{Sb}(01 \overline{1} 2) and MoS 2 MoS 2 MoS_(2)\mathrm{MoS}_{2}. i j i j i-j\mathrm{i}-\mathrm{j} ) contact resistance of Sb MoS 2 Sb MoS 2 Sb-MoS_(2)\mathrm{Sb}-\mathrm{MoS}_{2} transistors. k) Transfer characteristic curve of MoS 2 MoS 2 MoS_(2)\mathrm{MoS}_{2} FET with Pd contact. 1) Transfer characteristic curve of WSe 2 WSe 2 WSe_(2)\mathrm{WSe}_{2} FET with Pt contact. m) schematic of the CVD growth of VS 2 x Se 2 ( 1 x ) VS 2 x Se 2 ( 1 x ) VS_(2x)Se_(2(1-x))\mathrm{VS}_{2 x} \mathrm{Se}_{2(1-x)} alloy. n) Transfer characteristic curve of WSe 2 WSe 2 WSe_(2)\mathrm{WSe}_{2} FET with VSe 2 VSe 2 VSe_(2)\mathrm{VSe}_{2}, VSSe and In / Au In / Au In//Au\mathrm{In} / \mathrm{Au} contacts. o) Transfer characteristic curve of MoS 2 MoS 2 MoS_(2)\mathrm{MoS}_{2} FET with VS 2 VS 2 VS_(2)\mathrm{VS}_{2}, VSSe and VSe 2 VSe 2 VSe_(2)\mathrm{VSe}_{2} contacts.
图 11. 2D 晶体管的接触材料工程。a-b) 半导体与普通金属的态密度和能带。c-d) 半导体与半金属的态密度和能带。e) 单层 MoS 2 MoS 2 MoS_(2)\mathrm{MoS}_{2} 场效应晶体管(FET)在 Bi , Ni Bi , Ni Bi,Ni\mathrm{Bi}, \mathrm{Ni} 和 Ti 接触下的传输特性曲线。f) Bi MoS 2 Bi MoS 2 Bi-MoS_(2)\mathrm{Bi}-\mathrm{MoS}_{2} 场效应晶体管的接触电阻。g-h) Sb ( 01 1 2 ) Sb ( 01 1 ¯ 2 ) Sb(01 bar(1)2)\mathrm{Sb}(01 \overline{1} 2) MoS 2 MoS 2 MoS_(2)\mathrm{MoS}_{2} 界面的横截面透射电子显微镜(TEM)图像。 i j i j i-j\mathrm{i}-\mathrm{j} ) Sb MoS 2 Sb MoS 2 Sb-MoS_(2)\mathrm{Sb}-\mathrm{MoS}_{2} 晶体管的接触电阻。k) Pd 接触的 MoS 2 MoS 2 MoS_(2)\mathrm{MoS}_{2} 场效应晶体管传输特性曲线。l) Pt 接触的 WSe 2 WSe 2 WSe_(2)\mathrm{WSe}_{2} 场效应晶体管传输特性曲线。m) VS 2 x Se 2 ( 1 x ) VS 2 x Se 2 ( 1 x ) VS_(2x)Se_(2(1-x))\mathrm{VS}_{2 x} \mathrm{Se}_{2(1-x)} 合金的化学气相沉积(CVD)生长示意图。n) WSe 2 WSe 2 WSe_(2)\mathrm{WSe}_{2} 场效应晶体管在 VSe 2 VSe 2 VSe_(2)\mathrm{VSe}_{2} 、VSSe 和 In / Au In / Au In//Au\mathrm{In} / \mathrm{Au} 接触下的传输特性曲线。o) MoS 2 MoS 2 MoS_(2)\mathrm{MoS}_{2} 场效应晶体管在 VS 2 VS 2 VS_(2)\mathrm{VS}_{2} 、VSSe 和 VSe 2 VSe 2 VSe_(2)\mathrm{VSe}_{2} 接触下的传输特性曲线。

4.3 Interlayer mediated contacts for 2D devices
4.3 2D 器件的层间介导接触

Traditional silicon-based contact engineering strategies like ion implantation and silicide buffer layers face challenges in atomically thin 2D semiconductors [ 446 ] [ 446 ] ^([446]){ }^{[446]}. Jiang et al. addressed this by developing a substitutional yttrium (Y) doping technique for few-layer MoS 2 MoS 2 MoS_(2)\mathrm{MoS}_{2}. [ 137 ] [ 137 ] ^([137]){ }^{[137]} As shown in Figure 12a, Their process involved plasma-induced sulfur vacancy generation followed by active metal Y deposition in a high vacuum
传统的基于硅的接触工程策略,如离子注入和硅化物缓冲层,在原子级薄的二维半导体中面临挑战。Jiang 等人通过开发一种替代性钇(Y)掺杂技术解决了这一问题,适用于少层 MoS 2 MoS 2 MoS_(2)\mathrm{MoS}_{2} 。如图 12a 所示,他们的工艺包括等离子体诱导的硫空位生成,随后在高真空中沉积活性金属钇。

( < 1 × 10 8 < 1 × 10 8 < 1xx10^(-8)<1 \times 10^{-8} torr) and annealing, which facilitated selective Y substitution at sulfur sites without excessive downward diffusion. The resulting Y MoS 2 Y MoS 2 Y-MoS_(2)\mathrm{Y}-\mathrm{MoS}_{2} exhibited metallic behavior, enabling ohmic contacts with average contact resistance of 69 Ω μ m 69 Ω μ m 69 Omega mum69 \Omega \mu \mathrm{~m}, total resistance of 235 Ω μ m 235 Ω μ m 235 Omega mum235 \Omega \mu \mathrm{~m} and ON -current density of 1.22 mA μ m 1 1.22 mA μ m 1 1.22mAmum^(-1)1.22 \mathrm{~mA} \mu \mathrm{~m}^{-1} for MoS 2 MoS 2 MoS_(2)\mathrm{MoS}_{2} FETs (Figure 12b-e). Notably, they demonstrated scalable fabrication of large-area transistor arrays using this methodology. In a separate study, researchers introduced an intermediate conductive bridge layer incorporating gold-doped oxide interlayers [ 147 ] [ 147 ] ^([147]){ }^{[147]}. First, a 20 nm -thick layer of low-work-function metals (Al, Ti, Cr, and Cu ) was deposited via evaporation under vacuum conditions, followed by the sequential deposition of a 1 nm -thick Au layer. Subsequently, this metallic stack was intentionally exposed to ambient atmospheric conditions, leading to partial oxidation of the metal layer. The resulting oxide layer incorporated Au nanoclusters, forming a composite structure with heterogeneous work functions (Figure 12f-h). This engineered interface demonstrates enhanced compatibility for achieving optimal electrical contacts in 2D semiconductor devices, leveraging the work function tunability of the mixed metal-oxide system and the conductive pathways provided by the embedded Au nanocluster.
< 1 × 10 8 < 1 × 10 8 < 1xx10^(-8)<1 \times 10^{-8} torr)和退火,促进了选择性地在硫位点进行 Y 替代,而没有过度向下扩散。所得的 Y MoS 2 Y MoS 2 Y-MoS_(2)\mathrm{Y}-\mathrm{MoS}_{2} 表现出金属性行为,实现了欧姆接触,平均接触电阻为 69 Ω μ m 69 Ω μ m 69 Omega mum69 \Omega \mu \mathrm{~m} ,总电阻为 235 Ω μ m 235 Ω μ m 235 Omega mum235 \Omega \mu \mathrm{~m} MoS 2 MoS 2 MoS_(2)\mathrm{MoS}_{2} 场效应晶体管的开态电流密度为 1.22 mA μ m 1 1.22 mA μ m 1 1.22mAmum^(-1)1.22 \mathrm{~mA} \mu \mathrm{~m}^{-1} (图 12b-e)。值得注意的是,他们展示了利用该方法进行大面积晶体管阵列的可扩展制造。在另一项研究中,研究人员引入了包含掺金氧化物中间层的导电桥层 [ 147 ] [ 147 ] ^([147]){ }^{[147]} 。首先,在真空条件下通过蒸发沉积了 20 nm 厚的低功函数金属层(Al、Ti、Cr 和 Cu),随后依次沉积了 1 nm 厚的 Au 层。随后,这个金属堆栈被故意暴露于大气环境中,导致金属层部分氧化。所得的氧化层包含 Au 纳米簇,形成了具有异质功函数的复合结构(图 12f-h)。 该工程界面展示了增强的兼容性,以实现二维半导体器件中最佳的电接触,利用混合金属氧化物系统的功函数可调性以及嵌入的金纳米簇提供的导电路径。
In summary, advanced contact engineering forms the foundation for high-performance 2D electronics. Current research has made remarkable progress on lowering the contact resistance through innovative approaches. 1D edge contact for 2D materials are also attractive for showing ultralow contact resistance and high carrier mobility [ 148 151 ] [ 148 151 ] ^([148-151]){ }^{[148-151]}. However, for practical industrialization, future efforts should focus on developing scalable fabrication methods that maintain performance while ensuring compatibility with existing semiconductor manufacturing infrastructure and cost-effectiveness [ 152 ] [ 152 ] ^([152]){ }^{[152]}.
总之,先进的接触工程构成了高性能二维电子学的基础。当前研究在通过创新方法降低接触电阻方面取得了显著进展。二维材料的一维边缘接触也因显示出超低接触电阻和高载流子迁移率而具有吸引力 [ 148 151 ] [ 148 151 ] ^([148-151]){ }^{[148-151]} 。然而,为了实际工业化,未来的努力应集中于开发可扩展的制造方法,在保持性能的同时确保与现有半导体制造基础设施的兼容性和成本效益 [ 152 ] [ 152 ] ^([152]){ }^{[152]}

(a)  (a)

(d)  (d)

(g)  (g)
(b)  (b)

(e)  (e)

(h)  (h)
Figure 12. Interlayer mediated contacts for 2 D 2 D 2D2 D devices. a) schematic of plasma-deposition-annealing method for Y-doped MoS 2 MoS 2 MoS_(2)\mathrm{MoS}_{2}. b) schematic and cross-sectional SEM image of MoS 2 MoS 2 MoS_(2)\mathrm{MoS}_{2} FET with Y-doped MoS 2 MoS 2 MoS_(2)\mathrm{MoS}_{2} contact. c) Transfer characteristic curves of FETs with Y MoS 2 Y MoS 2 Y-MoS_(2)\mathrm{Y}-\mathrm{MoS}_{2} and MoS 2 MoS 2 MoS_(2)\mathrm{MoS}_{2} channel. d) Transfer characteristic curves of MoS 2 MoS 2 MoS_(2)\mathrm{MoS}_{2} FETs with Y MoS 2 , 1 T MoS 2 Y MoS 2 , 1 T MoS 2 Y-MoS_(2),1T-MoS_(2)\mathrm{Y}-\mathrm{MoS}_{2}, 1 \mathrm{~T}-\mathrm{MoS}_{2} and Ti / Au Ti / Au Ti//Au\mathrm{Ti} / \mathrm{Au} contacts. e) Comparison of the saturation output characteristics and the total resistance of different 2D FETs. f) schematic of metal-insulator-semiconductor and conductive bridge interlayer contact.
图 12. 用于 2 D 2 D 2D2 D 器件的层间介导接触。a) Y 掺杂 MoS 2 MoS 2 MoS_(2)\mathrm{MoS}_{2} 的等离子体沉积-退火方法示意图。b) MoS 2 MoS 2 MoS_(2)\mathrm{MoS}_{2} 场效应晶体管(FET)与 Y 掺杂 MoS 2 MoS 2 MoS_(2)\mathrm{MoS}_{2} 接触的示意图及横截面扫描电子显微镜(SEM)图像。c) 具有 Y MoS 2 Y MoS 2 Y-MoS_(2)\mathrm{Y}-\mathrm{MoS}_{2} MoS 2 MoS 2 MoS_(2)\mathrm{MoS}_{2} 通道的 FET 的传输特性曲线。d) 具有 Y MoS 2 , 1 T MoS 2 Y MoS 2 , 1 T MoS 2 Y-MoS_(2),1T-MoS_(2)\mathrm{Y}-\mathrm{MoS}_{2}, 1 \mathrm{~T}-\mathrm{MoS}_{2} Ti / Au Ti / Au Ti//Au\mathrm{Ti} / \mathrm{Au} 接触的 MoS 2 MoS 2 MoS_(2)\mathrm{MoS}_{2} FET 的传输特性曲线。e) 不同二维 FET 的饱和输出特性和总电阻比较。f) 金属-绝缘体-半导体和导电桥层间接触的示意图。

g ) cross-sectional TEM image of conductive bridge interlayer contact with WS 2 . h WS 2 . h WS_(2).h\mathrm{WS}_{2} . \mathrm{h} ) Effective barrier height of different conductive bridge interlayer contacts as a function of gate voltage.
g) 具有 WS 2 . h WS 2 . h WS_(2).h\mathrm{WS}_{2} . \mathrm{h} 的导电桥层间接触的横截面透射电子显微镜(TEM)图像。) 不同导电桥层间接触的有效势垒高度随栅极电压的变化。

5. Applications of 2D transistors
5. 二维晶体管的应用

As the feature sizes of semiconductor devices enter the sub-nanometer era, traditional silicon-based technology has encountered the dual challenges of physical limits and power consumption bottlenecks. 2D materials (such as graphene, transition metal sulfides, etc.) have become potential candidates for breaking through the limitations of Moore’s Law, thanks to their atomic-level thickness, high carrier mobility, and surface characteristics without dangling bonds. However, efficiently integrating 2D materials into existing silicon-based processes still faces many challenges, especially in terms of large-area, low-damage, high-fidelity wafer-level transfer and
随着半导体器件特征尺寸进入亚纳米时代,传统的硅基技术面临着物理极限和功耗瓶颈的双重挑战。二维材料(如石墨烯、过渡金属硫化物等)凭借其原子级厚度、高载流子迁移率以及无悬挂键的表面特性,成为突破摩尔定律限制的潜在候选材料。然而,将二维材料高效集成到现有硅基工艺中仍面临诸多挑战,特别是在大面积、低损伤、高保真度的晶圆级转移方面。

5.1 Wafer-Level Integration of 2D Materials and Their Heterostructures
5.1 二维材料及其异质结构的晶圆级集成

Two-dimensional (2D) materials have emerged as promising candidates for next-generation electronics due to their unique properties. However, challenges such as efficient transfer, interface engineering, and integration with existing semiconductor processes need to be addressed. This passage presents various innovative methods for wafer bonding, transfer, and integration of 2D materials to overcome these obstacles. [ 140 , 153 , 154 ] [ 140 , 153 , 154 ] ^([140,153,154]){ }^{[140, ~ 153, ~ 154]}
二维(2D)材料因其独特的性质,已成为下一代电子器件的有前景候选材料。然而,高效转移、界面工程以及与现有半导体工艺的集成等挑战亟需解决。本文介绍了多种创新的晶圆键合、转移及二维材料集成方法,以克服这些障碍。 [ 140 , 153 , 154 ] [ 140 , 153 , 154 ] ^([140,153,154]){ }^{[140, ~ 153, ~ 154]}
Traditional wet transfer relies on polymer carriers (such as PMMA), which can easily introduce residues and cause interface contamination. For example, PMMA residues significantly reduce the carrier mobility of graphene, while dry transfer faces issues of interlayer wrinkles and cracks. Figure 13a proposes a wafer bonding method based on BCB (bisbenzocyclobutene) adhesive, which transfers CVD-grown graphene and MoS 2 MoS 2 MoS_(2)\mathrm{MoS}_{2} onto silicon wafers through a thermal pressing process. The hydroxyl-free nature of BCB avoids interface traps, and its thermoplasticity allows for repeated reshaping, supporting the construction of multilayer heterostructures (such as graphene/hBN heterojunctions). This technology has successfully achieved uniform transfer of 4 -inch wafers, with field-effect mobility as high as 4520 cm 2 V 1 s 1 4520 cm 2 V 1 s 1 4520cm^(2)V^(-1)s^(-1)4520 \mathrm{~cm}^{2} \mathrm{~V}^{-1} \mathrm{~s}^{-1}, providing a compatibility solution for back-end integration. [ 159 ] [ 159 ] ^([159]){ }^{[159]} Figure 13b has developed a transfer medium with a gradient surface energy modification (a three-layer structure: borate ester/PMMA/PDMS), which realizes the non-destructive release of graphene by adjusting the difference in surface energy. This method avoids polymer residues, improves the carrier mobility of graphene to 10 4 cm 2 V 1 s 1 10 4 cm 2 V 1 s 1 10^(4)cm^(2)V^(-1)s^(-1)10^{4} \mathrm{~cm}^{2} \mathrm{~V}^{-1} \mathrm{~s}^{-1}, and the surface roughness is below 1 nm . DFT calculations confirm that the low adsorption energy of borate ester reduces interface contamination, providing a high cleanliness transfer substrate for flexible electronic devices. [ 160 ] [ 160 ] ^([160]){ }^{[160]} Figure 13c achieves thermally induced polymer deformation by adding volatile molecules (such as borneol), allowing 2D materials to form conformal contact with the target substrate. When transferring monocrystalline graphene grown on Cu foil to a PET flexible substrate, this method maintains atomic-level flatness and eliminates the need for polymer
传统的湿法转移依赖于聚合物载体(如 PMMA),这容易引入残留物并导致界面污染。例如,PMMA 残留物显著降低了石墨烯的载流子迁移率,而干法转移则面临层间皱纹和裂纹的问题。图 13a 提出了一种基于 BCB(二苯并环丁烯)粘合剂的晶圆键合方法,通过热压工艺将 CVD 生长的石墨烯和 MoS 2 MoS 2 MoS_(2)\mathrm{MoS}_{2} 转移到硅晶圆上。BCB 的无羟基特性避免了界面陷阱,其热塑性允许反复成型,支持多层异质结构(如石墨烯/hBN 异质结)的构建。该技术已成功实现 4 英寸晶圆的均匀转移,场效应迁移率高达 4520 cm 2 V 1 s 1 4520 cm 2 V 1 s 1 4520cm^(2)V^(-1)s^(-1)4520 \mathrm{~cm}^{2} \mathrm{~V}^{-1} \mathrm{~s}^{-1} ,为后端集成提供了兼容性解决方案。 [ 159 ] [ 159 ] ^([159]){ }^{[159]} 图 13b 开发了一种具有梯度表面能改性的转移介质(三层结构:硼酸酯/PMMA/PDMS),通过调节表面能差,实现了石墨烯的无损释放。 该方法避免了聚合物残留,提高了石墨烯的载流子迁移率至 10 4 cm 2 V 1 s 1 10 4 cm 2 V 1 s 1 10^(4)cm^(2)V^(-1)s^(-1)10^{4} \mathrm{~cm}^{2} \mathrm{~V}^{-1} \mathrm{~s}^{-1} ,且表面粗糙度低于 1 纳米。DFT 计算证实硼酸酯的低吸附能降低了界面污染,为柔性电子器件提供了高洁净度的转移基底。 [ 160 ] [ 160 ] ^([160]){ }^{[160]} 图 13c 通过添加挥发性分子(如樟脑)实现了热诱导的聚合物变形,使二维材料与目标基底形成贴合接触。在将生长于铜箔上的单晶石墨烯转移到 PET 柔性基底时,该方法保持了原子级平整度,且无需使用聚合物

residues. Experiments show that the room temperature Hall mobility of graphene exceeds 142 , 000 cm 2 V 1 s 11 142 , 000 cm 2 V 1 s 11 142,000cm^(2)V^(-1)s^(-11)142,000 \mathrm{~cm}^{2} \mathrm{~V}^{-1} \mathrm{~s}^{-11}, and the quantum Hall effect is clearly visible at 1.7 K , verifying the interface quality. [ 95 ] [ 95 ] ^([95]){ }^{[95]}
残留物。实验表明,石墨烯的室温霍尔迁移率超过 142 , 000 cm 2 V 1 s 11 142 , 000 cm 2 V 1 s 11 142,000cm^(2)V^(-1)s^(-11)142,000 \mathrm{~cm}^{2} \mathrm{~V}^{-1} \mathrm{~s}^{-11} ,且在 1.7K 时量子霍尔效应清晰可见,验证了界面质量。 [ 95 ] [ 95 ] ^([95]){ }^{[95]}
In addition, lattice mismatch and differences in thermal expansion coefficients between 2D materials and target substrates can cause interface stress, affecting device performance. For example, the interface roughness of MoS 2 MoS 2 MoS_(2)\mathrm{MoS}_{2} and SiO 2 SiO 2 SiO_(2)\mathrm{SiO}_{2} introduces scattering centers, reducing carrier mobility. Semiconductor back-end processes (BEOL) temperatures are typically below 400 C 400 C 400^(@)C400^{\circ} \mathrm{C}, while high-temperature annealing of 2D semiconductors (such as MoS 2 MoS 2 MoS_(2)\mathrm{MoS}_{2} ) can damage the underlying circuitry. How to achieve high-quality epitaxial growth at low temperatures is a key challenge. Figure 13d and Figure 13e report the low-temperature integration of Bi 2 O 2 Se 2 / Bi 2 SeO 5 Bi 2 O 2 Se 2 / Bi 2 SeO 5 Bi_(2)O_(2)Se_(2)//Bi_(2)SeO_(5)\mathrm{Bi}_{2} \mathrm{O}_{2} \mathrm{Se}_{2} / \mathrm{Bi}_{2} \mathrm{SeO}_{5} heterostructures. Through UV-assisted intercalation oxidation technology, Bi 2 O 2 Se Bi 2 O 2 Se Bi_(2)O_(2)Se\mathrm{Bi}_{2} \mathrm{O}_{2} \mathrm{Se} nanosheets are partially oxidized into single-crystal Bi 2 SeO 5 Bi 2 SeO 5 Bi_(2)SeO_(5)\mathrm{Bi}_{2} \mathrm{SeO}_{5}, forming an atomically flat interface (interface roughness < 0.5 nm < 0.5 nm < 0.5nm<0.5 \mathrm{~nm} ). This structure, as a high-k gate dielectric, supports a subthreshold swing as low as 62 mV dec 1 62 mV dec 1 62mVdec^(-1)62 \mathrm{mV} \mathrm{dec}{ }^{-1} for a 30 nm gate length transistor, with an electron mobility of 280 cm 2 V 1 s 1 280 cm 2 V 1 s 1 280cm^(2)V^(-1)s^(-1)280 \mathrm{~cm}^{2} \mathrm{~V}^{-1} \mathrm{~s}^{-1}, and multi-layer stacking is achieved through M3D (monolithic three-dimensional) integration. Figure 13e further optimizes step-guided epitaxy, preparing vertical FinFET arrays with a channel width of only 1 nm , demonstrating the feasibility of high-density three-dimensional integration. [ 110 , 161 ] [ 110 , 161 ] ^([110,)^(161]){ }^{[110, ~}{ }^{161]} Figure 13 f realizes the parallel synthesis of multi-channel MoS 2 MoS 2 MoS_(2)\mathrm{MoS}_{2} finFETs by controlling the step-flow growth of Cu foil. Combined with an ALD passivation layer, and logic gate circuits are constructed through hetero-integration, providing a hardware basis for multi-value computing. [ 162 ] [ 162 ] ^([162]){ }^{[162]}
此外,二维材料与目标基底之间的晶格失配和热膨胀系数差异会导致界面应力,影响器件性能。例如, MoS 2 MoS 2 MoS_(2)\mathrm{MoS}_{2} SiO 2 SiO 2 SiO_(2)\mathrm{SiO}_{2} 的界面粗糙度引入散射中心,降低载流子迁移率。半导体后端工艺(BEOL)温度通常低于 400 C 400 C 400^(@)C400^{\circ} \mathrm{C} ,而二维半导体(如 MoS 2 MoS 2 MoS_(2)\mathrm{MoS}_{2} )的高温退火可能损坏底层电路。如何在低温下实现高质量的外延生长是一个关键挑战。图 13d 和图 13e 报道了 Bi 2 O 2 Se 2 / Bi 2 SeO 5 Bi 2 O 2 Se 2 / Bi 2 SeO 5 Bi_(2)O_(2)Se_(2)//Bi_(2)SeO_(5)\mathrm{Bi}_{2} \mathrm{O}_{2} \mathrm{Se}_{2} / \mathrm{Bi}_{2} \mathrm{SeO}_{5} 异质结构的低温集成。通过紫外辅助插层氧化技术, Bi 2 O 2 Se Bi 2 O 2 Se Bi_(2)O_(2)Se\mathrm{Bi}_{2} \mathrm{O}_{2} \mathrm{Se} 纳米片部分氧化成单晶 Bi 2 SeO 5 Bi 2 SeO 5 Bi_(2)SeO_(5)\mathrm{Bi}_{2} \mathrm{SeO}_{5} ,形成原子级平整的界面(界面粗糙度 < 0.5 nm < 0.5 nm < 0.5nm<0.5 \mathrm{~nm} )。该结构作为高 k 栅介质,支持 30 纳米栅长晶体管的亚阈值摆幅低至 62 mV dec 1 62 mV dec 1 62mVdec^(-1)62 \mathrm{mV} \mathrm{dec}{ }^{-1} ,电子迁移率达到 280 cm 2 V 1 s 1 280 cm 2 V 1 s 1 280cm^(2)V^(-1)s^(-1)280 \mathrm{~cm}^{2} \mathrm{~V}^{-1} \mathrm{~s}^{-1} ,并通过 M3D(单片三维)集成实现多层堆叠。 图 13e 进一步优化了阶梯引导外延,制备了通道宽度仅为 1 纳米的垂直 FinFET 阵列,展示了高密度三维集成的可行性。 [ 110 , 161 ] [ 110 , 161 ] ^([110,)^(161]){ }^{[110, ~}{ }^{161]} 图 13f 通过控制铜箔的阶梯流动生长,实现了多通道 FinFET 的并行合成。结合 ALD 钝化层,通过异质集成构建逻辑门电路,为多值计算提供了硬件基础。 [ 162 ] [ 162 ] ^([162]){ }^{[162]}
Three-dimensional stacking requires high-density through-silicon vias (TSVs) and low-resistance interconnects, but existing TSV technology has issues with low alignment accuracy and high parasitic capacitance. Figure 13g shows an integrated circuit containing > 10 , 000 > 10 , 000 > 10,000>10,000 2D TMD FETs and CMOS logic devices, achieving three-dimensional interconnection through TSV (through-silicon via) technology. Figure 13h apply Dual-Tier Design which Tier 1 consists of MoS 2 MoS 2 MoS_(2)\mathrm{MoS}_{2} memtransistors (computing units), while Tier 2 incorporates graphene-based chemisensors (sensing
三维堆叠需要高密度的硅通孔(TSV)和低电阻互连,但现有 TSV 技术存在对准精度低和寄生电容高的问题。图 13g 展示了包含二维 TMD 场效应晶体管和 CMOS 逻辑器件的集成电路,通过 TSV(硅通孔)技术实现三维互连。图 13h 采用双层设计,第一层由存算单元的忆阻晶体管组成,第二层则集成了基于石墨烯的化学传感器(传感单元)。

units). The entire fabrication process operates below 200 C 200 C 200^(@)C200^{\circ} \mathrm{C} ensuring compatibility with back-end-of-line (BEOL) integration. Non-volatile memory functionality is enabled by an Al 2 O 3 / HfO 2 / Al 2 O 3 Al 2 O 3 / HfO 2 / Al 2 O 3 Al_(2)O_(3)//HfO_(2)//Al_(2)O_(3)\mathrm{Al}_{2} \mathrm{O}_{3} / \mathrm{HfO}_{2} / \mathrm{Al}_{2} \mathrm{O}_{3} floating-gate stack. The interconnect density achieved an interconnect density of 62 , 500 I / O 62 , 500 I / O 62,500I//O62,500 \mathrm{I} / \mathrm{O} per mm 2 mm 2 mm^(2)\mathrm{mm}^{2}, surpassing Intel’ s Foveros ( 400 I / O / mm 2 400 I / O / mm 2 400I//O//mm^(2)400 \mathrm{I} / \mathrm{O} / \mathrm{mm}^{2} ) and hybrid bonding technologies ( 10 , 000 I / O / mm 2 10 , 000 I / O / mm 2 10,000I//O//mm^(2)10,000 \mathrm{I} / \mathrm{O} / \mathrm{mm}^{2} ). [ 163 ] [ 163 ] ^([163]){ }^{[163]} Figure 13 i shows two-dimensional semiconductor materials (such as transition metal dichalcogenides, TMDs) can overcome the limitations of conventional silicon-based 3D integration, enabling the development of high-performance monolithic 3D (M3D) chips with single-crystalline structures. These methods offer solutions to key challenges in 2D material processing and integration, paving the way for their widespread application in advanced electronic devices. [ 164 ] [ 164 ] ^([164]){ }^{[164]}
单元)。整个制造过程在 200 C 200 C 200^(@)C200^{\circ} \mathrm{C} 以下进行,确保与后端工艺(BEOL)集成的兼容性。非易失性存储功能由 Al 2 O 3 / HfO 2 / Al 2 O 3 Al 2 O 3 / HfO 2 / Al 2 O 3 Al_(2)O_(3)//HfO_(2)//Al_(2)O_(3)\mathrm{Al}_{2} \mathrm{O}_{3} / \mathrm{HfO}_{2} / \mathrm{Al}_{2} \mathrm{O}_{3} 浮栅堆栈实现。互连密度达到每 mm 2 mm 2 mm^(2)\mathrm{mm}^{2} 62 , 500 I / O 62 , 500 I / O 62,500I//O62,500 \mathrm{I} / \mathrm{O} ,超过了英特尔的 Foveros( 400 I / O / mm 2 400 I / O / mm 2 400I//O//mm^(2)400 \mathrm{I} / \mathrm{O} / \mathrm{mm}^{2} )和混合键合技术( 10 , 000 I / O / mm 2 10 , 000 I / O / mm 2 10,000I//O//mm^(2)10,000 \mathrm{I} / \mathrm{O} / \mathrm{mm}^{2} )。 [ 163 ] [ 163 ] ^([163]){ }^{[163]} 图 13i 显示,二维半导体材料(如过渡金属二硫化物,TMDs)能够克服传统基于硅的三维集成的限制,实现具有单晶结构的高性能单片三维(M3D)芯片的开发。这些方法为二维材料的加工和集成中的关键挑战提供了解决方案,为其在先进电子设备中的广泛应用铺平了道路。 [ 164 ] [ 164 ] ^([164]){ }^{[164]}
Despite the significant progress made in the integration capabilities of 2D materials by the above technologies, the following challenges still exist: 1 . Scalability of single-crystal growth: Epitaxially grown 2D materials are still limited to specific substrates (such as sapphire) and cannot be directly grown on the BEOL layer.2. Insufficient interface engineering: The Schottky barrier problem at metal-2D semiconductor contacts has not been fully resolved, restricting device performance.3. Thermal budget limitations: Material selection and process compatibility under low-temperature processes ( < 400 C ) < 400 C ( < 400^(@)C)\left(<400^{\circ} \mathrm{C}\right) still need optimization. [ 155 , 158 , 165 , 166 ] [ 155 , 158 , 165 , 166 ] ^([155,158,165,166]){ }^{[155,158,165,166]}
尽管上述技术在二维材料集成能力方面取得了显著进展,但仍存在以下挑战:1. 单晶生长的可扩展性:外延生长的二维材料仍局限于特定基底(如蓝宝石),无法直接在后端工艺层(BEOL)上生长。2. 界面工程不足:金属-二维半导体接触处的肖特基势垒问题尚未完全解决,限制了器件性能。3. 热预算限制:材料选择和低温工艺下的工艺兼容性仍需优化。 ( < 400 C ) < 400 C ( < 400^(@)C)\left(<400^{\circ} \mathrm{C}\right) [ 155 , 158 , 165 , 166 ] [ 155 , 158 , 165 , 166 ] ^([155,158,165,166]){ }^{[155,158,165,166]}
Future research should focus on: Low-temperature epitaxial technology; Developing non-equilibrium growth processes (such as plasma-enhanced CVD) to break through temperature constraints; Interface reconstruction strategies: Utilizing ALD or MBE to achieve conformal coverage of ultra-thin high-k dielectrics; Three-dimensional architecture innovation: Exploring the integration of vertical tunneling field-effect transistors (TFETs) and neuromorphic devices to promote the development of integrated memory and computing architectures. [ 105 , 157 , 167 ] [ 105 , 157 , 167 ] ^([105,157,167]){ }^{[105, ~ 157, ~ 167] ~}
未来研究应聚焦于:低温外延技术;开发非平衡生长工艺(如等离子体增强化学气相沉积)以突破温度限制;界面重构策略:利用原子层沉积(ALD)或分子束外延(MBE)实现超薄高介电常数材料的均匀覆盖;三维架构创新:探索垂直隧穿场效应晶体管(TFET)和类脑器件的集成,推动集成存储与计算架构的发展。 [ 105 , 157 , 167 ] [ 105 , 157 , 167 ] ^([105,157,167]){ }^{[105, ~ 157, ~ 167] ~}

Figure 13. Wafer-Level Integration of 2D Materials and Their Heterojunctions. a) Photograph of a 100 mmdiameter 100 mmdiameter 100-mmdiameter100-\mathrm{mmdiameter} silicon wafer with van der Pauw (vdP) devices. The graphene sheet covers the entire wafer and lies on top of multilayer CVD hBN in the marked region. [ 159 ] [ 159 ] ^([159]){ }^{[159]} b) Wafer-scale graphene thermal emitter arrays on GSE-transferred graphene. [ 160 ] c [ 160 ] c ^([160])c{ }^{[160]} \mathrm{c} ). Illustration of techniques for transferring graphene onto destination substrates free of cracks and contamination. [ 95 ] [ 95 ] ^([95]){ }^{[95]} d) A photograph of the M3D integrated 2D GAA system, in which the 2 -inch Bi 2 O 2 Se 2 / Bi 2 SeO 5 Bi 2 O 2 Se 2 / Bi 2 SeO 5 Bi_(2)O_(2)Se^(2)//Bi_(2)SeO_(5)\mathrm{Bi}_{2} \mathrm{O}_{2} \mathrm{Se}^{2} / \mathrm{Bi}_{2} \mathrm{SeO}_{5} heterostructure and graphene electrode was subsequently integrated onto 4 -inch Si / SiO 2 Si / SiO 2 Si//SiO_(2)\mathrm{Si} / \mathrm{SiO}_{2} substrate. [ 161 ] [ 161 ] ^([161]){ }^{[161]} e) SEM images of vertical 2D fin-oxide heterostructure arrays on the 1 -inch MgO (110) wafer. [ 110 ] [ 110 ] ^([110]){ }^{[110]} f) Schematic illustration for 2D multi-finFETs potentially applied in advanced integrated circuits. [ 162 ] [ 162 ] ^([162]){ }^{[162]} g)Optical image showing wafer-scale monolithic two-tier 3D integration of 2D FETs with more than 10,000 devices in each tier.h) Optical image of a densely packed array of M3D-integrated two-tier cells based on monolayer MoS2 and graphene. [ 163 ] [ 163 ] ^([163]){ }^{[163]} i) Transfer- and growth-based M3D integration of single-crystalline TMDs. [ 164 ] [ 164 ] ^([164]){ }^{[164]}
图 13. 2D 材料及其异质结的晶圆级集成。a) 带有范德堡(vdP)器件的 100 mmdiameter 100 mmdiameter 100-mmdiameter100-\mathrm{mmdiameter} 硅晶圆照片。石墨烯片覆盖整个晶圆,并位于标记区域的多层 CVD hBN 之上。 [ 159 ] [ 159 ] ^([159]){ }^{[159]} b) GSE 转移石墨烯上的晶圆级石墨烯热发射器阵列。 [ 160 ] c [ 160 ] c ^([160])c{ }^{[160]} \mathrm{c} c) 将石墨烯无裂纹无污染地转移到目标基底的技术示意图。 [ 95 ] [ 95 ] ^([95]){ }^{[95]} d) M3D 集成 2D GAA 系统的照片,其中 2 英寸 Bi 2 O 2 Se 2 / Bi 2 SeO 5 Bi 2 O 2 Se 2 / Bi 2 SeO 5 Bi_(2)O_(2)Se^(2)//Bi_(2)SeO_(5)\mathrm{Bi}_{2} \mathrm{O}_{2} \mathrm{Se}^{2} / \mathrm{Bi}_{2} \mathrm{SeO}_{5} 异质结构和石墨烯电极随后集成到 4 英寸 Si / SiO 2 Si / SiO 2 Si//SiO_(2)\mathrm{Si} / \mathrm{SiO}_{2} 基底上。 [ 161 ] [ 161 ] ^([161]){ }^{[161]} e) 1 英寸 MgO (110)晶圆上垂直 2D 鳍氧化物异质结构阵列的 SEM 图像。 [ 110 ] [ 110 ] ^([110]){ }^{[110]} f) 可能应用于先进集成电路的 2D 多鳍 FET 示意图。 [ 162 ] [ 162 ] ^([162]){ }^{[162]} g) 显示晶圆级单片两层 3D 集成 2D FET 的光学图像,每层超过 10,000 个器件。h) 基于单层 MoS2 和石墨烯的 M3D 集成两层单元密集阵列的光学图像。 [ 163 ] [ 163 ] ^([163]){ }^{[163]}