PS and PL Ethernet Performance and Jumbo Frame Support with PL Ethernet in the Zynq-7000 SoC Zynq-7000 SoC 中的 PS 和 PL 以太网性能以及 PL 以太网的巨型帧支持
Summary 摘要
The focus of this application note is on Ethernet peripherals in the Zynq SoC. This application note describes using the processing system (PS) based gigabit Ethernet MAC (GEM) through the extended multiplexed I/O (EMIO) interface with the 1000BASE-X or SGMII physical interface using high-speed serial transceivers in programmable logic (PL). This application note also describes the implementation of PL-based Ethernet supporting jumbo frames. The designs provided with this application note enable the use of multiple Ethernet ports, and provide kernel-mode Linux device drivers. 本应用说明的重点是 Zynq SoC 中的以太网外设。本应用说明介绍了如何利用可编程逻辑 (PL) 中的高速串行收发器，通过扩展多路复用 I/O (EMIO) 接口与 1000BASE-X 或 SGMII 物理接口，使用基于处理系统 (PS) 的千兆以太网 MAC (GEM)。本应用说明还介绍了基于 PL 的以太网支持巨型帧的实现。本应用笔记提供的设计可使用多个以太网端口，并提供内核模式 Linux 设备驱动程序。
The reference design files for this application note can be downloaded from the Xilinx website. For detailed information about the design files, see Reference Design. 本应用笔记的参考设计文件可从 Xilinx 网站下载。有关设计文件的详细信息，请参阅参考设计。
Introduction 简介
The Zynq-7000 SoC device integrates a dual core ARM Cortex A9 MPCore based PS and PL in a single device. Zynq-7000 SoC 器件在单个器件中集成了基于 ARM Cortex A9 MPCore 的双核 PS 和 PL。
The PL includes the programmable logic, configuration logic, and associated embedded devices. The PS comprises the processor unit, on-chip memory, external memory interfaces, and peripheral connectivity interfaces including two gigabit ethernet controllers (GEM), which access PL signals through the extended multiplexed I/O (EMIO) interface to connect different physical interfaces. PL 包括可编程逻辑、配置逻辑和相关嵌入式器件。PS 包括处理器单元、片上存储器、外部存储器接口和外设连接接口，其中包括两个千兆以太网控制器 (GEM)，它们通过扩展多路复用 I/O (EMIO) 接口访问 PL 信号，以连接不同的物理接口。
In the designs provided with this application note, the PS-GEMO is connected to the Marvell PHY through the reduced gigabit media independent interface (RGMII), which is the default setup for the ZC706 board. The focus of this application note is the design of additional Ethernet ports.The designs described in this application note are: 在本应用笔记提供的设计中，PS-GEMO 通过精简千兆媒体独立接口 (RGMII) 连接到 Marvell PHY，这是 ZC706 板的默认设置。本应用说明的重点是额外以太网端口的设计：
PS Ethernet (GEM1) that is connected to a 1000BASE-X or SGMII physical interface in PL through an EMIO interface PS 以太网 (GEM1) 通过 EMIO 接口连接至 PL 中的 1000BASE-X 或 SGMII 物理接口
PL Ethernet implemented as soft logic in PL and connected to the 1000BASE-X or SGMII physical interface in PL PL 以太网作为 PL 中的软逻辑实现，并连接到 PL 中的 1000BASE-X 或 SGMII 物理接口
Figure 1 shows the various Ethernet implementations on the ZC706 board. 图 1 显示了 ZC706 板上的各种以太网实现方式。
Note: The three Ethernet links cannot be active at the same time because the ZC706 board offers only one SFP cage for the 1000BASE-X or SGMII PHY. The PS-GEM0 is always tied to the RGMII Marvell PHY. The PS-GEM1 and the PL Ethernet share the 1000 BASE-X or SGMII PHY so only two Ethernet Links can be active at a given time. The 1000BASE-X/SGMII PHY and the GTX transceiver are part of the AXI Ethernet core for PL Ethernet design. 注意：由于 ZC706 板只为 1000BASE-X 或 SGMII PHY 提供一个 SFP 盒，因此三个以太网链路不能同时激活。PS-GEM0 始终与 RGMII Marvell PHY 绑定。PS-GEM1 和 PL 以太网共享 1000 BASE-X 或 SGMII PHY，因此在给定时间内只能激活两个以太网链接。1000BASE-X/SGMII PHY 和 GTX 收发器是 PL 以太网设计的 AXI 以太网内核的一部分。
The design uses the GTX transceiver X0Y10 on the Zynq-7000 SoC connected to the SFP cage on the ZC706 board for 1000BASE-X or SGMII transceivers. The GTX transceiver reference clock ( differential) is generated from the Si5324 jitter attenuator on the ZC706 board. The clock divider values are adjusted to generate from the crystal connected to the Si5324. 该设计使用 Zynq-7000 SoC 上的 GTX 收发器 X0Y10 连接到 ZC706 板上的 SFP 封装盒，用于 1000BASE-X 或 SGMII 收发器。GTX 收发器参考时钟（ 差分）由 ZC706 板上的 Si5324 抖动衰减器生成。通过调整时钟分频值，可从连接到 Si5324 的 晶振生成 。
The Si5324 driver programs the device over the interface to generate the required clock value. This driver initializes the Si5324 once at boot time. At boot time, the driver probe function is invoked by the framework. The probe function fetches the client address from the device tree and programs the hardware registers with the relevant values. See [Ref 1] for details on Si5324. Si5324 驱动程序通过 接口对器件进行编程，以生成所需的时钟值。该驱动程序在启动时对 Si5324 进行一次初始化。启动时，驱动程序探针函数由 框架调用。探测函数从设备树中获取客户地址，并用相关值对硬件寄存器进行编程。有关 Si5324 的详细信息，请参阅 [参考文献 1]。
Using PS GEM Through EMIO 通过 EMIO 使用 PS GEM
This section describes how to use the PS Ethernet block GEM1 with the PL PHY through the EMIO interface. The PS Ethernet block is exposed to the PL through the EMIO, GMII, and management data input/output (MDIO) interfaces. The 1G/2.5G Ethernet PCS/PMA or SGMII core is used as Ethernet physical media in 1000BASE-X or SGMII modes, and uses the high-speed serial transceivers to access the SFP cage on the ZC706 board. The connection between the SFP cage to a standard Ethernet LAN is through an SFP-to-RJ45 converter module. 本节介绍如何通过 EMIO 接口将 PS 以太网模块 GEM1 与 PL PHY 配合使用。PS 以太网模块通过 EMIO、GMII 和管理数据输入/输出 (MDIO) 接口与 PL 连接。1G/2.5G 以太网 PCS/PMA 或 SGMII 内核在 1000BASE-X 或 SGMII 模式下用作以太网物理介质，并使用高速串行收发器访问 ZC706 板上的 SFP 封装盒。通过 SFP 至 RJ45 转换模块，可将 SFP 保持架连接到标准以太网 LAN。
Hardware Design 硬件设计
Figure 2 shows the design block diagram. The GMII interface connects the PHY and PS EMAC through the EMIO pins. The GEM1 block is enabled while generating the hardware system. See the Checksum Offloading section in the Gigabit Ethernet Controller chapter in [Ref 2] for information on checksum offloading in PS_GEM. See the chapter on using 1000BASE-X or SGMII PHY with Zynq-7000 SoC in [Ref 3] for more information. 图 2 显示了设计框图。GMII 接口通过 EMIO 引脚连接 PHY 和 PS EMAC。GEM1 块在生成硬件系统时已启用。有关 PS_GEM 中校验和卸载的信息，请参阅 [参考文献 2] 中千兆以太网控制器章节的校验和卸载部分。更多信息，请参阅 [参考文献 3] 中关于在 Zynq-7000 SoC 中使用 1000BASE-X 或 SGMII PHY 的章节。
Figure 2: Design Block Diagram 图 2：设计框图
Software Design 软件设计
The design uses the common macb. driver code for the PS- GEM0 and PS-GEM1. To enable GEM1 through the EMIO interface, specific registers must be programmed. This is part of the PS configuration data used by the Zynq- 7000 SoC first stage bootloader (FSBL). On system generation with the EMIO enabled for the second GEM, the ps7_init. tcl file that is available on SDK export of the hardware design, includes the register settings by default, which are: 该设计使用通用的 macb.0# 驱动代码。要通过 EMIO 接口启用 GEM1，必须对特定寄存器进行编程。这是 Zynq- 7000 SoC 第一阶段引导加载程序 (FSBL) 使用的 PS 配置数据的一部分。在为第二个 GEM 启用 EMIO 的系统生成过程中，SDK 导出硬件设计时可用的 ps7_init：
To select the EMIO as the source of receive clock, data, and control signals: 选择 EMIO 作为接收时钟、数据和控制信号的源：
Set SLCR.GEM1_RCLK_CTRL[SRCSEL] bit to 1 将 SLCR.GEM1_RCLK_CTRL[SRCSEL] 位设为 1
To select the EMIO as the source to generate reference clock: 选择 EMIO 作为产生参考时钟的源：
Set SLCR.GEM1_CLK_CTRL[SRCSEL] bit to 3'b1xx 将 SLCR.GEM1_CLK_CTRL[SRCSEL] 位设置为 3'b1xx
where ' ' is don't care (can be either 1 or 0 ) 其中" "表示不关心（可以是 1 或 0）
The macb driver uses the DMA controller attached to the GEM Ethernet controller in the PS. This driver is responsible for several functions, including DMA descriptor rings setup, allocation, and recycling. The interrupt handling is done only for the PS GEM events, as the interrupt status implicitly reflects the DMA events as well. Additionally, the device tree is updated to include PS-GEM1 with relevant parameters. macb 驱动程序使用连接到 PS 中 GEM 以太网控制器的 DMA 控制器。该驱动程序负责多项功能，包括 DMA 描述符环的设置、分配和回收。中断处理只针对 PS GEM 事件，因为中断状态也隐含地反映了 DMA 事件。此外，还更新了设备树，以包括 PS-GEM1 和相关参数。
Note: To support other PL physical interfaces, such as TBI, the hardware design and device tree must be edited. The PHY specific initialization is handled in the phylib subsystem in the Linux driver (macb) and information regarding the PHY can be provided in the device tree. To use the phylib subsystem for PHY programming, the phylib subsystem must support the PHY initialization routine for the desired PHY. 注：要支持其他 PL 物理接口（如 TBI），必须编辑硬件设计和设备树。特定 PHY 的初始化在 Linux 驱动程序 (macb) 的 phylib 子系统中处理，有关 PHY 的信息可在设备树中提供。要使用 phylib 子系统进行 PHY 编程，phylib 子系统必须支持所需 PHY 的 PHY 初始化例程。
Linux Driver Linux 驱动程序
A monolithic Linux device driver is provided for this design. Figure 3 shows the software architecture for the PS Ethernet interfaces. 为本设计提供了单片式 Linux 设备驱动程序。图 3 显示 PS 以太网接口的软件架构。
This section describes a PL implementation of Ethernet. The design consists of the AXI Ethernet, AXI DMA, and AXI Interconnect IP cores. The AXI Ethernet IP is connected to the 1000BASE-X or SGMII PHY. The design uses the high performance (HP) port for fast access to the PS-DDR memory, however, the general purpose slave port can also be used if the HP port is occupied with other peripherals. 本节介绍以太网的 PL 实现。该设计由 AXI 以太网、AXI DMA 和 AXI 互连 IP 核组成。AXI 以太网 IP 连接到 1000BASE-X 或 SGMII PHY。该设计使用高性能（HP）端口快速访问 PS-DDR 存储器，但如果 HP 端口被其他外设占用，也可使用通用从端口。
Hardware Design 硬件设计
Figure 4 shows the block diagram for the Ethernet implementation in PL. 图 4 显示了 PL 实现以太网的框图。
The HP port is used for fast data transfers between the PL and the PS DDR3 memory. It connects to the AXI DMA scatter-gather, stream to memory mapped (S2MM), and memory mapped to stream (MM2S) interfaces through the AXI interconnect. This interconnect also performs data-width conversion to connect the 64-bit HP port to the 32-bit interfaces of AXI DMA. In the AXI DMA, both the scatter-gather option and data realignment engine are enabled for the S2MM and MM2S paths. HP 端口用于 PL 和 PS DDR3 内存之间的快速数据传输。它通过 AXI 互连连接到 AXI DMA 散点采集、数据流到内存映射（S2MM）和内存映射到数据流（MM2S）接口。这种互连还能进行数据宽度转换，将 64 位 HP 端口连接到 AXI DMA 的 32 位接口。在 AXI DMA 中，S2MM 和 MM2S 路径都启用了散点收集选项和数据重新调整引擎。
The streaming interface of the AXI DMA is connected to the AXI Ethernet subsystem. The AXI Ethernet subsystem has full checksum offloading (CSO) enabled and has FIFO depths of 16K to support jumbo frame transfers. AXI DMA 的流接口与 AXI 以太网子系统相连。AXI 以太网子系统启用了完全校验和卸载（CSO）功能，FIFO 深度为 16K，支持巨型帧传输。
The AXI Ethernet core implements an Ethernet MAC and supports 1000BASE-X and SGMII PHY interfaces. It connects to the SFP through GTX transceivers through 1000Base-X/SGMII interfaces. AXI 以太网内核实现了以太网 MAC，支持 1000BASE-X 和 SGMII PHY 接口。它通过 1000Base-X/SGMII 接口的 GTX 收发器连接到 SFP。
For the control interface, a general-purpose AXI master port is enabled in the PS. This port connects to the AXI DMA and AXI Ethernet cores. The 1000BASE-X or SGMII PHY registers are accessed using the MDIO interface provided through the AXI Ethernet core. 对于控制接口，PS 中启用了一个通用 AXI 主端口。该端口连接到 AXI DMA 和 AXI 以太网内核。通过 AXI 以太网内核提供的 MDIO 接口访问 1000BASE-X 或 SGMII PHY 寄存器。
The interrupt ports from the AXI DMA and the AXI Ethernet IPs are connected to the general interrupt controller (GIC) in the PS. AXI DMA 和 AXI 以太网 IP 的中断端口连接到 PS 中的通用中断控制器 (GIC)。
Note: For further details on the IP cores, see [Ref 3], [Ref 4], and [Ref 5]. 注：有关 IP 核的更多详情，请参阅 [参考文献 3]、[参考文献 4] 和 [参考文献 5]。
Software Design 软件设计
This section describes the software aspects of the design. 本节介绍设计的软件方面。
The monolithic Linux driver code facilitates the functionality listed here: 单片式 Linux 驱动程序代码有助于实现此处列出的功能：
PL Ethernet MAC accesses PL 以太网 MAC 访问
AXI DMA transfers AXI DMA 传输
Physical media initialization for 1000BASE-X or SGMII interface using the phylib subsystem 使用 phylib 子系统初始化 1000BASE-X 或 SGMII 接口的物理介质
Linux Driver Linux 驱动程序
Figure 5 shows the software architecture for the design. 图 5 显示了设计的软件架构。
Figure 5: Driver Architecture for PL Ethernet 图 5：PL 以太网驱动程序架构
The driver is divided into these sections (see Appendix A for more information): 驱动程序分为以下几个部分（更多信息请参见附录 A）：
Initialization 初始化
MAC driver hooks MAC 驱动程序钩子
Interrupt service routines 中断服务例程
About Device Trees 关于设备树
The Device Tree is a data structure for describing hardware. Rather than hard coding every detail of a device into an operating system, many aspects of the hardware can be described in a data structure that is passed to the operating system at boot time. These settings are parsed by the drivers at the time of loading and parameters are set as defined in the device tree. The Linux drivers' device trees consist of: 设备树是一种用于描述硬件的数据结构。与将设备的每个细节硬编码到操作系统中相比，硬件的许多方面都可以在数据结构中进行描述，并在启动时传递给操作系统。驱动程序会在加载时解析这些设置，并根据设备树中的定义设置参数。Linux 驱动程序的设备树包括
PS Ethernet MAC EMIO-specific: PS GEM1 section, containing PS MAC parameters. PS 以太网 MAC EMIO 专用：PS GEM1 部分，包含 PS MAC 参数。
Ethernet section, containing the AXI Ethernet MAC parameters. 以太网部分，包含 AXI 以太网 MAC 参数。
I2C section, containing Si5324 parameters. The Si5324 device is the reference clock generator for the 1000BASE-X or SGMII PHY transceivers. I2C 部分，包含 Si5324 参数。Si5324 器件是 1000BASE-X 或 SGMII PHY 收发器的参考时钟发生器。
Hardware Requirements 硬件要求
Testing the design requires: 测试设计要求
Standard PC, preferably running the Linux OS 标准个人电脑，最好运行 Linux 操作系统
Ethernet port supporting 支持 的以太网端口
Netperf tool [Ref 6] Netperf 工具 [参考文献 6］
Zynq-7000 SoC ZC706 board with an SFP-to-RJ45 adapter module for testing 带 SFP 转 RJ45 适配器模块的 Zynq-7000 SoC ZC706 板，用于测试
Figure 6 shows the board setup. Jumper J 17 should be set to enable transmission through the SFP. The design was tested with the HP 378928-B21 Cisco Gigabit Ethernet RJ45 SFP Module. 图 6 显示了电路板设置。跳线 J 17 应设置为启用通过 SFP 传输。该设计使用 HP 378928-B21 Cisco 千兆以太网 RJ45 SFP 模块进行了测试。
Figure 6: Board Setup 图 6：电路板设置
Ethernet Performance 以太网性能
This section presents a summary of Ethernet throughput associated with the designs. 本节总结了与设计相关的以太网吞吐量。
The performance of various Ethernet applications at different layers is less than the throughput of the software driver and the Ethernet interface. This is due to the various headers and trailers inserted in each packet by the various layers of the networking stack. Ethernet is used as a medium to carry traffic. Various protocols, such as TCP/UDP, implement protocol specific header/trailer formats. 不同层的各种以太网应用性能低于软件驱动程序和以太网接口的吞吐量。这是由于网络堆栈各层在每个数据包中插入了各种报头和预告片。以太网被用作传输流量的媒介。各种协议（如 TCP/UDP）实施特定于协议的报头/预告片格式。
CPU Affinity Considerations CPU 亲和性考虑因素
In a multi-processor environment, CPU affinity is the ability of an OS scheduler to bind a certain process to a given processor. The OS scheduler tries to schedule a process on the same processor where it last executed. If the processor is not available, the process is scheduled on a different processor. 在多处理器环境中，CPU 亲和性是指操作系统调度程序将特定进程绑定到给定处理器的能力。操作系统调度程序会尝试将进程调度到它上次执行的同一处理器上。如果该处理器不可用，进程就会被调度到另一个处理器上。
Binding a process to a processor ensures that the process is always scheduled on the same processor. The primary benefit of binding a process with a processor is optimal cache performance, as it circumvents the invalidating of cache that is necessary each time a process is scheduled on a different processor. 将进程绑定到处理器可确保进程始终被调度到同一个处理器上。将进程与处理器绑定的主要好处是优化缓存性能，因为这样可以避免每次在不同处理器上调度进程时都必须对缓存进行无效化处理。
The CPU affinity of a process can be altered with the taskset program in Linux. For all benchmarking results, netserver or netperf was bound to CPU2 using taskset. In this example, binding netserver and netperf results in significant performance improvement: 进程的 CPU 亲和性可通过 Linux 中的 taskset 程序进行更改。在所有基准测试结果中，netserver 或 netperf 都是通过 taskset 绑定到 CPU2 上的。在本例中，绑定 netserver 和 netperf 可显著提高性能：
This application note provides designs for implementing the PS Ethernet through the EMIO with PHY and Ethernet implementation in the PL to support multiple Ethernet links and jumbo frames. Performance benchmarking results for the designs are included in this application note (see http://www.wiki.xilinx.com/Zynq+PL+Ethernet). 本应用说明提供了通过 EMIO 实现 PS 以太网的设计，并在 PL 中实现 PHY 和以太网，以支持多个以太网链路和巨型帧。设计的性能基准测试结果包含在本应用说明中（见 http://www.wiki.xilinx.com/Zynq+PL+以太网）。
The test results show a trend of throughput improvement with increasing packet size, and the impact of CSO on both throughput and CPU utilization. 测试结果显示了吞吐量随数据包大小增加而提高的趋势，以及 CSO 对吞吐量和 CPU 利用率的影响。
Reference Design 参考设计
The reference design files for this application note can be downloaded from: 本应用说明的参考设计文件可从以下网站下载：
static int axienet_probe(struct platform_device *pdev)
The probe function is the actual initialization function that performs these tasks: 探针函数是执行这些任务的实际初始化函数：
Create the Ethernet driver structure alloc_etherdev(). 创建以太网驱动程序结构 alloc_etherdev()。
Set up the Ethernet driver structure. 设置以太网驱动程序结构。
Map the physical device register address space into the kernel address space of_iomap(). 将物理设备寄存器地址空间映射到内核地址空间 of_iomap()。
Read the driver configuration properties from the device structure and set the driver flags accordingly. The properties handled are: 从设备结构中读取驱动程序配置属性，并相应设置驱动程序标志。处理的属性包括
MAC address: local-mac-address MAC 地址： local-mac-address
PHY handle: To handle the PHY device PHY 句柄：处理 PHY 设备
Map the DMA register address space (physical) into Kernel address space of_iomap(). 将 DMA 寄存器地址空间（物理）映射到内核地址空间 of_iomap()。
Get TXIRQ and RX IRQ numbers 获取 TXIRQ 和 RX IRQ 编号
Set MAC address 设置 MAC 地址
Get the PHY handle to attach the PHY device 获取 PHY 句柄以连接 PHY 设备
MDIO setup MDIO 设置
Register to net device 注册到网络设备
MAC Driver Hooks MAC 驱动程序挂钩
The MAC driver supports these handles to interface to upper layers: MAC 驱动程序支持这些句柄，以连接上层：
Open: This driver open routine invokes PHY start, allocates ISRs, and enables the interrupts and ISR handling. It also resets the AXI_DMA core and its buffer descriptors are initialized. Additionally, it starts the network interface queues. 打开：该驱动程序的打开例程调用 PHY 启动、分配 ISR 并启用中断和 ISR 处理。它还会重置 AXI_DMA 内核，并初始化其缓冲区描述符。此外，它还会启动网络接口队列。
Stop: This driver stop routine stops the PHY, removes the interrupt handlers, and disables interrupts. AXI_DMA (RX and TX) is stopped and the descriptors are released. DMA tasklet is disabled and network interface queues are stopped. 停止：该驱动程序停止例程可停止 PHY、移除中断处理程序并禁用中断。停止 AXI_DMA（RX 和 TX）并释放描述符。禁用 DMA 小任务，停止网络接口队列。
Start_xmit: This routine is invoked from upper layers to initiate transmission of a packet. It fetches next available descriptor, populate their fields, start transmission, by starting the DMA transfer. It also considers the transmit CSO setting and accordingly populates transmit descriptor user application fields. Start_xmit：上层调用此例程启动数据包传输。它通过启动 DMA 传输，获取下一个可用描述符、填充其字段并开始传输。它还会考虑传输 CSO 设置，并相应地填充传输描述符用户应用字段。
Change_mtu: This hook is called to change the MTU size dynamically. It is used to support jumbo frames. Change_mtu：调用此钩子可动态更改 MTU 大小。它用于支持巨型帧。
Set_mac_address: This function changes the MAC address of the Ethernet core. Set_mac_address：此函数用于更改以太网核心的 MAC 地址。
Interrupt Service Routines 中断服务例程
The Linux driver has two interrupt service routines (ISR) as follows: Linux 驱动程序有以下两个中断服务例程 (ISR)：
Receive ISR: Handles AXI DMA receive interrupts. It checks for the RX status; if the status is OK, it processes the descriptors and passes them to interface for further process. 接收 ISR：处理 AXI DMA 接收中断。它会检查 RX 状态；如果状态正常，它就会处理描述符，并将其传递给接口进行进一步处理。
Transmit ISR: Handles AXI DMA transmit interrupt. It checks for the TX status; if the status is OK, it clears the descriptors and unmaps corresponding buffers so that CPU can regain ownership of the same. At the end, it invokes interface TX queue wake-up, so that transmission can resume. 发送 ISR：处理 AXI DMA 发送中断。它检查 TX 状态；如果状态正常，则清除描述符并取消映射相应的缓冲区，以便 CPU 重新获得相同的所有权。最后，它会调用接口 TX 队列唤醒，以便继续传输。
In case of an error status, ISR schedules the tasklet to reset the DMA and Ethernet services, and reconfigures all transmit and receive descriptors. In-case interface TX queue was stopped due to unavailability of free TX buffers in the transmit path. 如果出现错误状态，ISR 会调度任务单元重置 DMA 和以太网服务，并重新配置所有发送和接收描述符。如果接口 TX 队列因传输路径中没有空闲的 TX 缓冲区而停止。
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References 参考资料
This document uses the following references: 本文档使用了以下参考文献：
ZC706 Evaluation Board for the Zynq-7000 XC7Z045 User Guide (UG954) 用于 Zynq-7000 XC7Z045 的 ZC706 评估板用户指南 (UG954)
7 Series FPGAs GTX/GTH Transceivers User Guide (UG476) 7 系列 FPGA GTX/GTH 收发器用户指南 (UG476)
Revision History 修订历史
The following table shows the revision history for this document. 下表列出了本文档的修订历史。
Date
Version
Description of Revisions
1.0
Initial Xilinx release.
2.0
Added last sentence under Hardware Requirements. Updated
example and note under CPU Affinity Considerations. Updated
CPU Affinity Considerations and Figure 7. Deleted Figure 8,
"Impact of CSO on PS GEM CPU Utilization". Updated PL Ethernet:
Throughput Observation and Figure 8 and Figure 9. Updated
Figure 10. Updated ISE and PlanAhead versions from 14.4 to 14.6.
3.0
Updated Figure 1, Figure 4, and Figure 6. Deleted last sentence
preceding Figure 6. Deleted note and performance-related
information (subsections "Test Methodology", "PL Ethernet:
Throughput Observation", and "Jumbo Frame Performance") from
Ethernet Performance and added reference to test methodology
and performance observations wiki site. Updated ISE synthesis
software from ISE 14.6 to Vivado 2014.4 and PlanAhead version
from 14.6 to 2014.4 in Table 1. Deleted Appendix A (PS EMIO
Ethernet Device Tree) and Appendix B (PL Ethernet Device Tree).
4.0 .1
Replaced the xilinx_emacps driver with the macb driver. Removed
the PHY timer implementation used in the axieth driver and used
the phylib interface. Updated Appendix A with the latest axieth
driver details. In addition to 1000BASE-X, SGMII PHY interface
support is also added to the design. Document is updated to show
SGMII mode support. Updated synthesis and implementation
software from Vivado 2014.4 to Vivado 2015.4.
5.0
Updated synthesis and implementation software from Vivado tools
2015.4 to 2017.4.
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