Module Revision
Indicates the revision number of the implementation. This information
depends on the design step.| Module Revision |
| :--- |
| Indicates the revision number of the implementation. This information |
| depends on the design step. |
MOD_TYPE
15:815: 8
r
模块类型
此内部标记固定为CO_(H)\mathrm{CO}_{H}.
Module Type
This internal marker is fixed to CO_(H).| Module Type |
| :--- |
| This internal marker is fixed to $\mathrm{CO}_{H}$. |
Field Bits Type Description
MOD_REV 7:0 r "Module Revision
Indicates the revision number of the implementation. This information
depends on the design step."
MOD_TYPE 15:8 r "Module Type
This internal marker is fixed to CO_(H)."
"MOD_NUMBE
R" 31:16 r "Module Number
Indicates the module identification number
(00FF" {f92a6f3f1-13eb-405d-bbd5-7751382aca1d} CONVCTRL)| Field | Bits | Type | Description |
| :--- | :--- | :--- | :--- |
| MOD_REV | $7: 0$ | r | Module Revision <br> Indicates the revision number of the implementation. This information <br> depends on the design step. |
| MOD_TYPE | $15: 8$ | r | Module Type <br> This internal marker is fixed to $\mathrm{CO}_{H}$. |
| MOD_NUMBE <br> R | $31: 16$ | r | Module Number <br> Indicates the module identification number <br> $(00 \mathrm{FF}$ {f92a6f3f1-13eb-405d-bbd5-7751382aca1d} CONVCTRL) |
,
Clock Control Register
Clock Control Register 允许编程器根据应用的要求调整模块的功能和功耗。它控制 module clock 信号和对 sleep 信号的反应性。 中图分类
Clock Control Register
31
转换器控制块 (CONVCTRL)
田
位
类型
描述
DISR
0
乌尔曼
Module Disable Request Bit(模块禁用请求位) 用于启用/禁用模块的控制。 0_(B)quad0_{\mathrm{B}} \quad On request: 启用模块时钟 1_(B)quad1_{\mathrm{B}} \quad Off request: 停止模块时钟
Module Disable Request Bit
Used for enable/disable control of the module.
0_(B)quad On request: enable the module clock
1_(B)quad Off request: stop the module clock| Module Disable Request Bit |
| :--- |
| Used for enable/disable control of the module. |
| $0_{\mathrm{B}} \quad$ On request: enable the module clock |
| $1_{\mathrm{B}} \quad$ Off request: stop the module clock |
DISS
1
rh
Module Disable Status Bit 0_(B)quad0_{\mathrm{B}} \quad Module clock is enabled 1_(B)quad1_{\mathrm{B}} \quad Off:模块未计时
Module Disable Status Bit
0_(B)quad Module clock is enabled
1_(B)quad Off: module is not clocked| Module Disable Status Bit |
| :--- |
| $0_{\mathrm{B}} \quad$ Module clock is enabled |
| $1_{\mathrm{B}} \quad$ Off: module is not clocked |
Sleep Mode Enable Control
Used to control module's reaction to sleep mode.
0_(B)quad Sleep mode request is enabled and functional
1_(B)quad Module disregards the sleep mode control signal| Sleep Mode Enable Control |
| :--- |
| Used to control module's reaction to sleep mode. |
| $0_{\mathrm{B}} \quad$ Sleep mode request is enabled and functional |
| $1_{\mathrm{B}} \quad$ Module disregards the sleep mode control signal |
0\mathbf{0}
2,
r
31:431: 4
保留,写入 0,读取为 0
Field Bits Type Description
DISR 0 rw "Module Disable Request Bit
Used for enable/disable control of the module.
0_(B)quad On request: enable the module clock
1_(B)quad Off request: stop the module clock"
DISS 1 rh "Module Disable Status Bit
0_(B)quad Module clock is enabled
1_(B)quad Off: module is not clocked"
EDIS 3 rw "Sleep Mode Enable Control
Used to control module's reaction to sleep mode.
0_(B)quad Sleep mode request is enabled and functional
1_(B)quad Module disregards the sleep mode control signal"
0 2, r
31:4 Reserved, write 0, read as 0 | Field | Bits | Type | Description |
| :--- | :--- | :--- | :--- |
| DISR | 0 | rw | Module Disable Request Bit <br> Used for enable/disable control of the module. <br> $0_{\mathrm{B}} \quad$ On request: enable the module clock <br> $1_{\mathrm{B}} \quad$ Off request: stop the module clock |
| DISS | 1 | rh | Module Disable Status Bit <br> $0_{\mathrm{B}} \quad$ Module clock is enabled <br> $1_{\mathrm{B}} \quad$ Off: module is not clocked |
| EDIS | 3 | rw | Sleep Mode Enable Control <br> Used to control module's reaction to sleep mode. <br> $0_{\mathrm{B}} \quad$ Sleep mode request is enabled and functional <br> $1_{\mathrm{B}} \quad$ Module disregards the sleep mode control signal |
| $\mathbf{0}$ | 2, | r | |
| | $31: 4$ | Reserved, write 0, read as 0 | |