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9

On-chip ESD Protection Circuits - Input Circuitry
片上ESD保护电路 - 输入电路

9.1 Receivers and ESD
9.1 接收器和ESD

Receiver circuits and the electrostatic discharge (ESD) protection of receiver circuits are very important in ESD design [1-6] . Why? Almost all products and applications contain standalone receivers, or bi-directional receiver/transmitter circuits. Receiver circuits are typically the most sensitive circuits in a chip application. Receiver performance has a critical role in the semiconductor chip performance. First, receiver circuits are small. Second, the receiver performance requirements limit the ESD loading on the receiver. Metal oxide semiconductor field effect transistor (MOSFET) gate area, bipolar emitter area, and electrical interconnect wiring widths impact the receiver performance. Third, receivers are electrically connected to either the MOSFET gate (in a complementary metaloxide semiconductor [CMOS] receiver) and the bipolar base region (in a bipolar receiver); both the MOSFET gate dielectric region and the bipolar transistor base region are the more sensitive region of the structures. Hence, they evolve with MOSFET gate dielectric scaling and bipolar transistor performance objectives. Fourth, receivers require low series resistance. Because of these factors, the receiver is also one of the most interesting networks for evaluation of ESD protection. Since receivers are one of the smallest and most sensitive networks, they provide the opportunity to understand the future limitations on ESD protection of future technology generation, potential scaling implications and the lower limits of ESD protection levels achievable.
接收器电路和接收器电路的静电放电（ESD）保护在ESD设计中非常重要[1-6]。为什么？几乎所有产品和应用都包含独立的接收器或双向接收器/发射器电路。接收器电路通常是芯片应用中最敏感的电路。接收器性能对半导体芯片性能起着至关重要的作用。首先，接收器电路很小。其次，接收器性能要求限制了接收器上的ESD负载。金属氧化物半导体场效应晶体管 （MOSFET） 栅极面积、双极性发射极面积和电气互连接线宽度会影响接收器性能。第三，接收器与MOSFET栅极（在互补金属氧化物半导体[CMOS]接收器中）和双极性基极区（在双极接收器中）电连接;MOSFET栅极介电区域和双极晶体管基极区域都是结构中更敏感的区域。因此，它们随着MOSFET栅极介电缩放和双极晶体管性能目标而发展。第四，接收器需要低串联电阻。由于这些因素，接收器也是评估ESD保护的最有趣的网络之一。由于接收器是最小和最敏感的网络之一，因此它们提供了了解未来技术生成对ESD保护的未来限制、潜在的扩展影响以及可实现的ESD保护水平下限的机会。
In this chapter, we will discuss receiver, receiver evolution, ESD receiver problems, receiver ESD integration and solutions, as well as
在本章中，我们将讨论接收器、接收器演进、ESD接收器问题、接收器ESD集成和解决方案，以及

full-transmission gates, zero-threshold voltage transmission gates, Schmitt triggers and other networks will be used to discuss the issues
将使用全传输门、零阈值电压传输门、施密特触发器和其他网络来讨论这些问题
and problems with receiver networks. The ESD protection sensitivity and solutions will be highlighted in the discussion [1-6].
以及接收器网络的问题。ESD保护的灵敏度和解决方案将在讨论中重点介绍[1-6]。

9.2 Receivers and Receiver Delay Time
9.2 接收器和接收器延迟时间

Receiver circuit performance can be quantified by the receiver delay time. A receiver response can be quantified as the intrinsic CMOS receiver gate delay, and the extrinsic receiver delay [7-11].
接收器电路性能可以通过接收器延迟时间来量化。接收机响应可以量化为内在CMOS接收机栅极延迟和外在接收机延迟[7-11]。
The CMOS intrinsic gate delay can be expressed as
CMOS固有栅极延迟可以表示为：
The extrinsic delay components of the receiver gate delay include the interconnect delay components of the CMOS gate delay, and the ESD networks.
接收器门延迟的外延分量包括CMOS门延迟的互连延迟分量和ESD网络。
The interconnect delay components of the CMOS gate delay, excluding the intrinsic components, can be expressed as [7-11]
CMOS栅极延迟的互连延迟分量（不包括固有分量）可以表示为[7-11]
where denotes the interconnect-related delay terms, , and are MOSFET output resistance and capacitance (respectively), is the MOSFET receiver switching capacitance, , and are the resistance, capacitance and line length of the interconnect, and is the circuit fan-out [7-9.]. These interconnect delay terms become a larger percentage of the total CMOS gate delay as the intrinsic delay, , decreases and must be reduced either through interconnect resistance or capacitance reduction. Interconnect RC delay can be reduced by migrating from to based interconnects, which improves electrical conductivity [10, 11].
其中 ，表示与互连相关的延迟项， 分别 是MOSFET输出电阻和电容， 是MOSFET接收器开关电容， 是互连的电阻、电容和线长， 是电路扇出[7-9]。随着固有延迟的降低，这些互连延迟项在总CMOS栅极延迟中所占的百分比越来越大， 必须通过互连电阻或电容降低来降低。通过从 互连迁移到 基于互连，可以减少互连RC延迟，从而提高导电性[10,11]。

9.3 ESD Loading Effect on Receiver Performance
9.3 ESD负载对接收器性能的影响

With the addition of ESD protection, receiver performance objectives must add the influence of the extrinsic loading on the receiver network. The extrinsic delay of the receiver can be represented as the extrinsic interconnect wiring load, and the ESD element load,
随着ESD保护的增加，接收机性能目标必须增加外部负载对接收机网络的影响。接收器的外在延迟可以表示为外在互连布线负载和ESD元件负载，
An important ESD design consideration is the relationship of the extrinsic delay terms of the receiver network. As the receiver performance objectives increase, the total extrinsic delay of the receiver must be reduced. Hence, the loading of the interconnects, the ESD element, and any other auxiliary circuitry must be evaluated in the receiver performance. There are two issues. First, the scaling of the interconnects provides for the ability to have a larger percentage of the extrinsic delay term for ESD protection. Second, the scaling of the interconnect can lead to ESD failures [12-17]. The transition from to interconnects is not only important for semiconductor chip performance objectives, it is also important for ESD robustness in high-performance chips. Aluminum interconnects were a significant ESD failure mechanism in high-pin-count microprocessor chips for the and sub- technology generations due to the interconnect scaling and system level wireability requirements . With the migration to a low-k material, the extrinsic delay loading associated with interconnects can be reduced [16, 17.]. As the interconnect extrinsic delay term is reduced, this will provide some reduced relief on the scaling of the ESD network extrinsic delay factor on receiver networks.
ESD设计的一个重要考虑因素是接收器网络的外在延迟项之间的关系。随着接收机性能目标的提高，接收机的总外在延迟必须降低。因此，必须在接收器性能中评估互连、ESD元件和任何其他辅助电路的负载。有两个问题。首先，互连的缩放提供了更大比例的外部延迟项，用于ESD保护。其次，互连的缩放会导致ESD故障[12-17]。从 互连到 互连的转变不仅对半导体芯片的性能目标很重要，而且对高性能芯片的ESD鲁棒性也很重要。由于互连扩展和系统级可接线性要求 ，铝互连是高 引脚数微处理器芯片中 重要的ESD故障机制。通过向低k材料的迁移，可以降低与互连相关的外部延迟负载[16,17]。随着互连外部延迟项的减小，这将在一定程度上缓解接收器网络上ESD网络外部延迟因子的缩放。
Providing ESD protection for receiver networks is a challenge because of the receiver performance requirements and the receiver evolution for each technology generation. A few standard circuit topologies are used for ESD protection of receivers for both human body model (HBM) and CDM events.
为接收机网络提供ESD保护是一项挑战，因为接收机性能要求和每一代技术的接收机演进。一些标准电路拓扑用于人体模型 （HBM） 和 CDM 事件的接收器的 ESD 保护。

9.4 Receivers and HBM
9.4 接收器和 HBM

For HBM events, receiver networks used ESD networks include the following:
对于 HBM 事件，使用的 ESD 网络包括：
  • Primary stage of a grounded gate thick oxide MOSFET, a resistor, and a grounded gate thin oxide MOSFET element.
    接地栅极厚氧化物MOSFET、电阻器和接地栅极薄氧化物MOSFET元件的初级级。
  • Primary stage of a Double-diode ESD network.
    双二极管ESD网络的初级级。
In early development, grounded-gate "thick oxide" MOSFETs were designed using a parasitic device; the local oxidation (LOCOS) isolation served as a thick oxide gate structure, and the LOCOS region defined the source and drain regions. The primary stage of the ESD network would initiate when MOSFET snapback occurred in the "thick oxide" MOSFET. Avalanche breakdown in the primary thick oxide MOSFET would allow conduction to the MOSFET source. Additionally, the standard MOSFET structure served as a secondary stage. With MOSFET avalanche breakdown in the thin oxide MOSFET, the secondary stage would provide conduction to the thin oxide MOSFET source. In conjunction with the resistor element, a resistive divider was formed, allowing a lower voltage on the input node of the MOSFET receiver gate dielectric. In some implementations, the substrate conduction led to a dynamic threshold effect on the thick oxide MOSFET where the secondary stage influenced the primary stage, triggering and conduction process. This topology was favored in N-channel metal oxide semiconductor (NMOS) technology where there was no p-channel MOSFET to utilize for ESD protection. Additionally, with the introduction of shallow trench isolation (STI), the usage of the primary "thick oxide" MOSFET usage was curtailed because of the high turn-on voltage of the parasitic STI-defined npn element (Figure 9.1).
在早期开发中，使用寄生器件设计了接地栅极“厚氧化物”MOSFET;局部氧化（LOCOS）隔离作为厚氧化物栅结构，LOCOS区域定义了源极和漏极区域。当MOSFET在“厚氧化物”MOSFET中发生回弹时，ESD网络的初级级将启动。初级厚氧化物MOSFET中的雪崩击穿将允许传导到MOSFET源。此外，标准MOSFET结构用作次级。随着MOSFET在薄氧化物MOSFET中的雪崩击穿，次级将向薄氧化物MOSFET源提供传导。与电阻元件一起形成电阻分压器，允许MOSFET接收器栅极电介质的输入节点上的电压较低。在某些实现中，衬底导通导致厚氧化物MOSFET的动态阈值效应，其中次级影响初级级，触发和导通过程。这种拓扑结构在N沟道金属氧化物半导体（NMOS）技术中受到青睐，该技术没有用于ESD保护的p沟道MOSFET。此外，随着浅沟槽隔离 （STI） 的引入，由于寄生 STI 定义的 npn 元件的高导通电压，主要“厚氧化物”MOSFET 的使用受到限制（图 9.1）。
Figure 9.1 Thick oxide/resistor/thin oxide MOSFET ESD network.
图 9.1 厚氧化物/电阻/薄氧化物 MOSFET ESD 网络。

Figure 9.2 Double diode ESD network.
图 9.2 双二极管 ESD 网络。

Double-diode ESD networks using two diode elements between the input pad and the two power rails is used in CMOS technology [ , 18]. Diode structures were formed utilizing the p-channel and nchannel MOSFET source/drain regions in addition to the well and tub regions (Figure 9.2).
CMOS技术采用在输入焊盘和两个电源轨之间使用两个二极管元件的双二极管ESD网络[ ，18]。除了孔和管区域外，还利用p沟道和n沟道MOSFET源极/漏极区域形成二极管结构（图9.2）。

9.5 Receivers and CDM
9.5 接收器和 CDM

For CDM events, receiver networks used ESD networks include the following :
对于CDM事件，使用ESD网络的接收器网络包括：
  • Primary stage of a double-diode ESD network, a resistor, and a secondary stage consisting of a second double-diode ESD
    双二极管ESD网络的初级级、电阻器和由第二个双二极管ESD组成的次级
    network. 网络。
  • Primary stage of a double-diode ESD network, a series resistor and a secondary stage of a grounded-gate MOSFET ESD element.
    双二极管ESD网络的初级级、接地栅MOSFET ESD元件的串联电阻和次级。
Figure 9.3 shows an example of an ESD network with a primary stage of a double-diode ESD network, a resistor, and a secondary stage consisting of a second double-diode ESD network. Some of the advantages of this network are as follows:
图9.3显示了一个ESD网络示例，该网络具有双二极管ESD网络的初级级，电阻器和由第二个双二极管ESD网络组成的次级。该网络的一些优点如下：
  • Scaling. 缩放。
  • Migration. 迁移。
  • Avoidance of dielectric regions.
    避免介电区域。
Figure 9.4 shows a second embodiment of a network that combines both the diode-based and MOSFET-based ESD protection [ 1,2 . The advantage of this network is the utilization of the resistor/thin oxide MOSFET which provides a resistor divider operation. This improves both the HBM and the CDM ESD results. This CDM network has some of the following advantages:
图9.4显示了网络的第二个实施例，该实施例结合了基于二极管和基于MOSFET的ESD保护[ 1,2 .该网络的优点是利用电阻器/薄型氧化物MOSFET，提供电阻分压器操作。这改善了 HBM 和 CDM ESD 结果。该CDM网络具有以下一些优点：
  • Primary and Secondary Stages both active during HBM events.
    初级和次要阶段在 HBM 事件期间都处于活动状态。
  • Utilization of MOSFET drain for CDM protection.
    利用MOSFET漏极保护CDM。
  • Allowance of a lower series resistor element.
    允许使用较低的串联电阻元件。
Figure 9.3 Primary stage of a double-diode ESD network, a resistor, and a secondary CDM stage consisting of a second double-diode ESD network.
图 9.3 双二极管 ESD 网络、电阻器和由第二个双二极管 ESD 网络组成的次级 CDM 级的初级。
Figure 9.4 Primary stage of a double-diode ESD network, a series resistor and a secondary stage of a groundedgate MOSFET ESD element. Sources: S. Voldman. ESD: Physics and Devices. John Wiley and Sons Ltd., 2004, S. Voldman. ESD: Circuits and Devices. First Edition. John Wiley and Sons Ltd. 2005.
图 9.4 双二极管 ESD 网络的初级级、接地栅极 MOSFET ESD 元件的串联电阻和次级。资料来源：S. Voldman。ESD：物理与器件。John Wiley and Sons Ltd.，2004 年，S. Voldman。ESD：电路和器件。初版。John Wiley and Sons Ltd. 2005年。

9.6 Receivers and Receiver Evolution
9.6 接收器和接收器演进

In CMOS, with MOSFET constant electric field scaling theory, the MOSFET dielectric thickness and power supply voltage are scaled to provide improved MOSFET device performance. With MOSFET dielectric scaling, power supply scaling, voltage signal level scaling, and the introduction of mixed voltage interface (MVI) applications, receiver architecture and design continues to become more complex [19.-37.]. In CMOS technology, for and power supplies, the
在CMOS中，利用MOSFET恒定电场缩放理论，对MOSFET介电厚度和电源电压进行缩放，以提供改进的MOSFET器件性能。随着MOSFET介电缩放、电源缩放、电压信号电平缩放以及混合电压接口（MVI）应用的引入，接收器的架构和设计变得越来越复杂[19.-37]。在CMOS技术中，对于 电源和
dielectric thickness in receiver networks allowed for direct electrical connections to MOSFET gate structures . As the power supply was scaled, and with the introduction of mixed voltage applications, the need to reduce the voltage stress on the dielectric was achieved using a transmission gate (TG) or pass transistor to lower the voltage levels . With decreasing voltage levels, mixed voltage signals, and dielectric over-voltage condition concerns, a plethora of new receiver circuits evolved with new features: half-pass transmission gates, full-pass transmission gates, pseudo-zero threshold voltage transmission gates, zero threshold voltages, keeper feedback networks, and hysteresis feedback elements. Each of these provided new ESD receiver issues and challenges [1, 2].
接收器网络中的介电厚度允许直接与MOSFET栅极结构 进行电气连接。随着电源的扩展，以及混合电压应用的引入，需要使用传输栅极（TG）或传输晶体管来降低电压水平 ，从而降低电介质上的电压应力。随着电压电平的降低、混合电压信号和介电过压条件问题，大量新的接收器电路发展起来具有新功能：半通传输门、全通传输门、伪零阈值电压传输门、零阈值电压、保持器反馈网络和迟滞反馈元件。这些都带来了新的ESD接收器问题和挑战[1,2]。

9.7 Receiver Circuits with Half-pass Transmission Gate
9.7 带半通传输门的接收器电路

A common element in a receiver network is a transmission gate network. A half-pass transmission gate, using a n-channel MOSFET element is electrically connected between the ESD element and the MOSFET inverter stage of the receiver network. A transmission gate (TG) has an influence on both the ESD robustness of a receiver. The transmission gate (TG) typically is involved in the ESD failure from HBM, MM, and CDM events. The transmission gate (TG) structure is typically connected to the input pad, and the power supply , making it vulnerable during ESD events.
接收机网络中的一个常见元素是传输门网络。使用n沟道MOSFET元件的半通传输栅极在ESD元件和接收器网络的MOSFET逆变器级之间电连接。传输栅极 （TG） 对接收器的 ESD 鲁棒性都有影响。传输栅极 （TG） 通常与 HBM、MM 和 CDM 事件引起的 ESD 故障有关。传输栅极（TG）结构通常连接到输入焊盘和电源 ，使其在ESD事件中容易受到攻击。
A transmission gate (TG) is a voltage-controlled switch which has a high and low impedance state. In a half-pass transmission gate, the transmission gate is typically a single MOSFET structure whose source and drain are connected in series between the input pad and the MOSFET receiver gate stage (Figure 9.5). The MOSFET gate controls the logic state. When the n-channel MOSFET gate has a gate voltage equal to the power supply voltage , the logic transfers a logic " 1 " from the pad to the receiver.
传输栅极 （TG） 是一种具有高阻抗和低阻抗状态的压控开关。在半通道传输栅极中，传输栅极通常为单个MOSFET结构，其源极和漏极串联在输入焊盘和MOSFET接收器栅极级之间（图9.5）。MOSFET栅极控制逻辑状态。当n沟道MOSFET栅极的栅极电压等于电源电压 时，逻辑将逻辑“1”从焊盘传输到接收器。
Assuming the receiver network is initially uncharged, the output capacitance has an initial value. In this state, the voltage that will be observed at the output of the transmission gate, assuming a loading capacitance, , is [20]
假设接收器网络最初未充电，则输出电容具有初始值。在这种状态下，假设负载电容为 ，在传输栅极输出端观察到的电压为 [20]
with a charging time of
充电时间
Figure 9.5 MOSFET receiver network with n-channel MOSFET half-pass transmission gate.
图9.5 采用n沟道MOSFET半通传输栅极的MOSFET接收器网络。
When the ratio of the time to charging time is large, the output voltage approaches the maximum output voltage, during functional operation of the circuit,
当时间与充电时间之比较大时，输出电压接近最大输出电压，在电路的功能运行期间，
From a functional perspective, the highest voltage output value is a threshold voltage lower than the voltage placed on the n-channel MOSFET gate electrode. The MOSFET half-pass transistor transmission gate also has a characteristic resistance. The resistance can be expressed as
从功能角度来看，最高电压输出值是低于施加在n沟道MOSFET栅极上的电压的阈值电压。MOSFET半通晶体管传输栅极也具有特性电阻。电阻可以表示为
The resistance of the MOSFET half-pass transistor plays a role in the ESD event in that it limits the amount of current that can flow from the signal pad to the MOSFET receiver network. In conjunction with other circuit elements, and additional ESD elements, it serves as a resistor divider. During ESD events, after the MOSFET snapback voltage, the resistance of interest is the MOSFET dynamic onresistance.
MOSFET半通晶体管的电阻在ESD事件中起着重要作用，因为它限制了从信号焊盘流向MOSFET接收器网络的电流量。与其他电路元件和附加ESD元件一起，它用作电阻分压器。在ESD事件期间，在MOSFET回弹电压之后，目标电阻为MOSFET动态导通电阻。
During ESD operation, there are two points that influence the operation of the n-channel MOSFET half-pass transistor. First, the output voltage will be dependent on the MOSFET gate voltage state. Second, the MOSFET snapback voltage has a role in the voltage drop, and the conduction process through the half-pass transistor.
在ESD工作期间，有两点会影响n沟道MOSFET半通晶体管的工作。首先，输出电压将取决于MOSFET栅极电压状态。其次，MOSFET的回弹电压对压降和通过半通晶体管的传导过程有影响。
In the case of the voltage on the MOSFET gate electrode, assuming the gate is floating, the state of the gate electrode is a function of the half-pass transistor input-to-gate capacitance and the other electrode capacitances that form a capacitor divider network. As the input voltage increases, the capacitance coupling between the MOSFET half-pass transistor input-to-gate capacitor causes the MOSFET gate to rise.
在MOSFET栅极上的电压的情况下，假设栅极是浮动的，则栅极的状态是半通晶体管输入到栅极电容和形成电容分压器网络的其他电极电容的函数。随着输入电压的增加，MOSFET半通晶体管输入-栅极电容之间的电容耦合导致MOSFET栅极上升。
At the same time, as the input voltage on the MOSFET passtransistor increases, and the half-pass transistor drain-to-source voltage increases, the MOSFET snapback voltage is reached leading to MOSFET snapback. In order for MOSFET snapback to occur, the impedance in series with the MOSFET half-pass transistor must allow current conduction. In the case that there are no circuit elements except the MOSFET receiver inverter stage, the current
同时，随着MOSFET传递晶体管上的输入电压增加，半通晶体管漏源电压增加，达到MOSFET回弹电压，导致MOSFET回弹。为了实现MOSFET回弹，与MOSFET半通晶体管串联的阻抗必须允许电流传导。在除MOSFET接收器逆变器级外没有电路元件的情况下，电流
conduction leads to a charging of the MOSFET gates. As the current flows through the half-pass transistor, the MOSFET gates of the inverter stage increases until the current through the MOSFET halfpass transistor fails, or MOSFET gate dielectric breakdown occurs.
导通导致MOSFET栅极充电。当电流流过半通晶体管时，逆变器级的MOSFET栅极增加，直到通过MOSFET半过程晶体管的电流失效，或发生MOSFET栅极介电击穿。
In the case of additional other elements in the receiver network between the MOSFET half-pass transistor and the MOSFET receiver inverter stage, a current path can be established leading to current flowing through the MOSFET half-pass transistor, and the additional elements. The presence of the other elements can lead to MOSFET second breakdown of the MOSFET half-pass transmission gate structure.
在MOSFET半通晶体管和MOSFET接收器反相级之间的接收器网络中存在其他元件的情况下，可以建立电流路径，导致电流流过MOSFET半通晶体管和其他元件。其他元件的存在会导致MOSFET半通传输栅极结构的MOSFET二次击穿。
The introduction of the MOSFET half-pass transistor establishes a voltage margin allowing the operation of the ESD networks to discharge current away from the receiver network and through the ESD network current loop. For ESD events that occur at the input signal pads, the ESD elements should be placed between the signal pad and the MOSFET half-pass transistor (e.g. HBM, MM, and transmission line pulse (TLP) events).
MOSFET半通晶体管的引入建立了一个电压裕量，允许ESD网络的工作将电流从接收器网络释放出来，并通过ESD网络电流环路。对于输入信号焊盘上发生的ESD事件，ESD元件应放置在信号焊盘和MOSFET半通晶体管之间（例如HBM、MM和传输线脉冲（TLP）事件）。
For charged device model (CDM) events, the ESD current flows from the substrate to the signal pad. In the case of a p-substrate that is charged positively, when the signal pad is placed at a ground potential, current will flow from the chip substrate to the signal pad. When there is an n-channel MOSFET half-pass transistor transmission gate, current will flow in a few different current paths .
对于带电器件模型 （CDM） 事件，ESD 电流从基板流向信号焊盘。对于带正电的p型衬板，当信号焊盘置于地电位时，电流将从芯片衬底流向信号焊盘。当存在n沟道MOSFET半通晶体管传输栅极时，电流将流过几个不同的电流路径 。
  • First, current will flow from the substrate to the n-diffusion (e.g. p-substrate-to-n-channel MOSFET diffusion metallurgical junction) input side of the MOSFET half-pass transmission gate.
    首先，电流将从衬底流向MOSFET半通传输栅极的n扩散（例如p衬底到n沟道MOSFET扩散冶金结）输入侧。
  • A second current path is through the MOSFET receiver inverter stage n-channel MOSFET gate and continuing through the MOSFET half-pass transistor channel region (e.g. source-todrain).
    第二条电流路径是通过MOSFET接收器逆变级n沟道MOSFET栅极，并继续通过MOSFET半通道晶体管沟道区域（例如源极漏极）。
  • When there are more circuit elements present between the MOSFET half-pass transmission gate and the MOSFET inverter stage, current will flow through those circuit elements and through the n-channel MOSFET half-pass transmission gate.
    当MOSFET半程传输栅极和MOSFET逆变器级之间存在较多的电路元件时，电流将流过这些电路元件并通过n沟道MOSFET半通道传输栅极。
In the case that the current is flowing from the output side of the MOSFET half-pass transmission gate, there is a delay time that occurs to allow the current to flow to the signal pad from the interior of the chip. If we assume the MOSFET inverter stage and subsequent elements are at capacitance, , and the voltage rises to a maximum voltage condition, we can estimate the MOSFET half-pass transistor delay time by assuming the signal pad is at a ground potential [20],
当电流从MOSFET半通传输栅极的输出侧流出时，会出现延迟时间，以允许电流从芯片内部流向信号焊盘。如果我们假设MOSFET逆变器级和后续元件处于电容状态， 并且电压上升到最大电压条件，我们可以通过假设信号焊盘处于地电位[20]来估计MOSFET半通晶体管延迟时间。
and discharge time ,
和放电时间 ，
During functional operation, the voltage . During ESD events, the MOSFET half-pass transmission gate voltage is a function of the capacitive divider formed between the gate-to-source, and gate-to-drain capacitances.
在功能运行期间，电压 .在ESD事件中，MOSFET半通传输栅极电压是栅-源电容和栅-漏极电容之间形成的电容分压器的函数。
From an ESD design perspective, the key issues associated with MOSFET half-pass transistor transmission gates are the following:
从ESD设计的角度来看，与MOSFET半通晶体管传输栅极相关的关键问题如下：
  • Half-pass MOSFET transmission gate elements are to be placed between HBM ESD networks and MOSFET receiver inverter stages.
    半通道MOSFET传输栅极元件将放置在HBM ESD网络和MOSFET接收器逆变器级之间。
  • Half-pass MOSFET transmission gate elements are vulnerable to ESD events due to the electrical placement in series with the MOSFET receiver inverter stage and the input signal pad.
    半通道MOSFET传输栅极元件容易受到ESD事件的影响，因为电气位置与MOSFET接收器反相器级和输入信号焊盘串联。
  • Half-pass MOSFET transmission gate elements are vulnerable to ESD events due to the electrical placement in series with the signal pad and the power rails (e.g. and ).
    半通道MOSFET传输栅极元件容易受到ESD事件的影响，因为电气放置与信号焊盘和电源轨（例如 和 ）串联。
  • Half-pass MOSFET transmission gate elements must be integrated with the HBM ESD networks, CDM networks, and
    半通道MOSFET传输栅极元件必须与HBM ESD网络、CDM网络和
    additional receiver network functions to provide good ESD results in receiver signal pads.
    额外的接收器网络功能，可在接收器信号焊盘中提供良好的ESD结果。
  • MOSFET-based receiver network ESD failures typically involve failure of the MOSFET half-pass transmission gate element.
    基于MOSFET的接收器网络ESD故障通常涉及MOSFET半通传输栅极元件的故障。
  • MOSFET half-pass transmission gate ESD failures during HBM events are typically MOSFET source-to-drain failures.
    HBM 事件期间的 MOSFET 半通传输栅极 ESD 故障通常是 MOSFET 源极到漏极故障。
  • MOSFET half-pass transmission gate ESD failures during CDM events can be MOSFET substrate-to-input diffusion contact and junction failures, MOSFET source-to-drain, and MOSFET gateto-input diffusion failure mechanisms.
    CDM事件期间的MOSFET半通传输栅极ESD故障可能是MOSFET衬底到输入扩散接触和结故障、MOSFET源极到漏极和MOSFET栅极到输入扩散故障机制。

9.8 Receiver with Full-pass Transmission Gate
9.8 带全通发射门的接收机

A common element in a receiver network is a transmission gate (TG). Transmission gates are in the form of full-pass and half-pass transmission gates [20]. A full-pass transmission gate, uses a pchannel MOSFET and an n-channel MOSFET element. The logic state of the full-pass transistor for the p-channel and n-channel halfpass elements are complementary. A transmission gate (TG) is a voltage-controlled switch which has high and low impedance states. In a full-pass transmission gate, the transmission gate has both the p-channel and n-channel MOSFET structure sources and drains connected in series between the input pad and the MOSFET receiver gate stage [18]. The MOSFET gate controls the logic state. When the n-channel MOSFET gate has a gate voltage equal to the power supply voltage , the logic transfers a logic " 1 " from the pad to the receiver. When the p-channel MOSFET gate has a gate voltage equal to the power supply voltage , the logic transfers a logic " 1 " from the pad to the receiver. Figure 9.6 shows the full-pass transmission gate electrically connected between the ESD element and the MOSFET inverter stage of the receiver network.
接收机网络中的一个常见元件是传输门 （TG）。传输门有全通和半通传输门两种形式[20]。全通传输栅极使用p沟道MOSFET和n沟道MOSFET元件。p沟道和n沟道半功元件的全通晶体管的逻辑状态是互补的。传输栅极 （TG） 是一种具有高阻抗和低阻抗状态的压控开关。在全通传输栅极中，传输栅极具有p沟道和n沟道MOSFET结构的源极，并在输入焊盘和MOSFET接收器栅极级之间串联[18]。MOSFET栅极控制逻辑状态。当n沟道MOSFET栅极的栅极电压等于电源电压 时，逻辑将逻辑“1”从焊盘传输到接收器。当p沟道MOSFET栅极的栅极电压等于电源电压 时，逻辑将逻辑“1”从焊盘传输到接收器。图9.6显示了在接收器网络的ESD元件和MOSFET逆变器级之间电连接的全通传输栅极。
Figure 9.6 Full-pass transmission gate integrated between the ESD network and the MOSFET receiver.
图9.6 集成在ESD网络和MOSFET接收器之间的全通传输栅极。
A full-pass transmission gate (TG) has an influence on both the ESD robustness of a MOSFET receiver network [18]. During a positive polarity ESD HBM event, a positive pulse occurs on an input pad. When the potential of the -well diode element reaches forward bias, current flows through the diode element, to the power supply. As this occurs, the voltage potential on the input of the fullpass transistor begins to increase. In the case of an n-channel halfpass transistor, the voltage differential across the n-channel device would increase until MOSFET snapback would occur; if gatecoupling occurs, the half-pass may under undergo MOSFET turn-on during ESD events. In the case of the full-pass transmission gate, as the voltage drop increases, the -channel pass transistor -well node will forward bias; this leads to forward-active operation of the
全通发射栅极（TG）对MOSFET接收器网络的ESD鲁棒性都有影响[18]。在正极性 ESD HBM 事件期间，输入焊盘上会出现正脉冲。当 二极管元件的电位达到正向偏置时，电流流过二极管元件，流向 电源。当这种情况发生时，全通晶体管输入端的电压电位开始增加。对于n沟道半通晶体管，n沟道器件两端的压差将增加，直到MOSFET发生回弹;如果发生栅极耦合，则在ESD事件期间，半通道可能会经历MOSFET导通。在全通传输栅极的情况下，随着压降的增加， -沟道通晶体管 -阱节点将正向偏置;这导致了
lateral and/or vertical parasitic pnp bipolar transistor. In the case of the lateral parasitic pnp element, this will lead to a decrease in the voltage-differential across the full-pass transmission gate. In some sense, the p-channel half-pass transmission gate transistor prevents failure of the n-channel half-pass transmission gate transistor. In the case of a negative polarity event, the half-pass transistor will discharge to the semiconductor substrate, in parallel with the nwell/p-substrate diode ESD element [1-6].
横向和/或垂直寄生PNP双极晶体管。对于侧向寄生 pnp 元件，这将导致全通传输栅极两端的压差减小。从某种意义上说，p沟道半通传输栅极晶体管可以防止n沟道半通传输栅极晶体管失效。在发生负极性事件时，半通晶体管将与nwell/p基板二极管ESD元件并联放电至半导体衬底[1-6]。
Figure 9.7 shows the experimental results of a MOSFET receiver network as a function of n-well sheet resistance for a positive HBM pulse event (with the substrate grounded). Figure 9.8 shows the experimental results of a MOSFET receiver network as a function of a normalized group containing n-well film thickness and n-well sheet resistance for a positive HBM pulse event. Experimental results show that the highest HBM ESD results occur with the full-pass transistor. A key point in the results is that the presence of the full-pass transmission gate does not degrade the ESD protection results in the receiver. The experimental results show that the highest results occur with the presence of a p-type element on the input node improving the receiver network ESD results. Independent of the nwell sheet resistance or reference polarity, for a positive pulse event, the highest address pin results occurs with the full-pass transmission gate .
图9.7显示了MOSFET接收器网络的实验结果，作为正HBM脉冲事件（基板接地）的n阱片电阻的函数。图 9.8 显示了 MOSFET 接收器网络的实验结果，该网络是归一化组的函数，其中包含 n 孔膜厚和 n 孔片电阻，用于正 HBM 脉冲事件。实验结果表明，全通晶体管的HBM ESD结果最高。结果的一个关键点是，全通传输栅极的存在不会降低接收器的ESD保护结果。实验结果表明，当输入节点上存在p型元件时，接收机网络ESD结果得到改善，结果最高。与nwell片电阻或参考极性无关，对于正脉冲事件，全通传输栅极 会产生最高的地址引脚结果。
Figure 9.7. ESD HBM results of receiver networks as a function of -well sheet resistance.
图 9.7.接收器网络的 ESD HBM 结果与 阱片电阻的关系。

9.9 Receiver, Half-pass Transmission Gate, and Keeper Network
9.9 接收器、半通传输门和保持器网络

With the introduction of the MOSFET half-pass transmission gate in receiver networks, the quality of the CMOS logic levels is hampered in CMOS receiver networks. The half-pass transmission gate, using an n-channel MOSFET element is electrically connected between the ESD element and the MOSFET inverter stage of the receiver network [15]. A half-pass transmission gate (TG) is a voltage-controlled switch which has a high and low impedance state. In a half-pass transmission gate, the transmission gate is typically a single channel MOSFET structure whose source and drain are connected in series between the input pad and the MOSFET receiver gate stage. The MOSFET gate controls the logic state. When the n-channel MOSFET gate has a gate voltage equal to the power supply voltage , the logic transfers a logic " 1 " from the pad to the receiver. The output voltage of the half-pass transistor can be expressed as [20]
随着MOSFET半通传输栅极在接收器网络中的引入，CMOS接收器网络中的CMOS逻辑电平质量受到阻碍。半通传输栅极使用n沟道MOSFET元件，在ESD元件和接收器网络的MOSFET逆变器级之间电连接[15]。半通传输栅极 （TG） 是一种具有高阻抗和低阻抗状态的压控开关。在半通道传输栅极中，传输栅极通常为单 通道MOSFET结构，其源极和漏极串联在输入焊盘和MOSFET接收器栅极级之间。MOSFET栅极控制逻辑状态。当n沟道MOSFET栅极的栅极电压等于电源电压 时，逻辑将逻辑“1”从焊盘传输到接收器。半通晶体管的输出电压可以表示为[20]
with a charging time of [20]
充电时间为 [20]