Verilog $^{®}$ HDL Verilog $^{®}$ 硬件描述语言

Quick Reference Guide 快速参考指南

based on the Verilog-2001 standard
基于 Verilog-2001 标准
(IEEE Std 1364-2001) （IEEE 标准 1364-2001）

by
Stuart Sutherland

SUTHERLAND

SUTHERLAND $H_{D}$
www.sutherland-hdl.com
作者：斯图尔特·萨瑟兰 SUTHERLAND SUTHERLAND $H_{D}$ www.sutherland-hdl.com

Copyright © 2001, Sutherland HDL, Inc., all rights reserved.
版权所有 © 2001，Sutherland HDL 公司，保留所有权利。

Permission is granted by Sutherlaand HDL to download and/or print the PDF document containing this reference guide from www.sutherland-hdl.com for personal use only. The reference guide may not be used for commercial purposes or distributed in any form or by any means without obtaining express permission from Sutherland HDL.
经 Sutherland HDL 许可，允许从 www.sutherland-hdl.com 下载和/或打印包含本参考指南的 PDF 文档，仅供个人使用。未经 Sutherland HDL 明确许可，本参考指南不得用于商业目的或以任何形式或方式分发。

Verilog $^{®} HDL$ Quick Reference Guide
Verilog $^{®} HDL$ 快速参考指南

based on the Verilog-2001 standard (IEEE Std 1364-2001)
基于 Verilog-2001 标准（IEEE 标准 1364-2001）
by 由
Stuart Sutherland 斯图尔特·萨瑟兰

published by 由...出版\title{ SUTHERLAND } $H_{D}$ \title{ 萨瑟兰 } $H_{D}$ Sutherland HDL, Inc. 萨瑟兰 HDL 公司22805 SW $92^{nd}$ Place 22805 西南路 $92^{nd}$ 广场Tualatin, OR 97062 俄勒冈州图拉丁市，邮编 97062(503) 692-0898www.sutherland-hdl.com www.sutherland-hdl.com（网站地址无需翻译）

Copyright © 1992, 1996, 2001 by Sutherland HDL, Inc.
版权所有 © 1992、1996、2001，Sutherland HDL 公司
All rights reserved. No part of this book may be reproduced in any form or by any means without the express written permission of Sutherland HDL, Inc.
版权所有。未经 Sutherland HDL 公司书面明确许可，不得以任何形式或任何方式复制本书的任何部分。

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ISBN: 1-930368-03-8 国际标准书号：1-930368-03-8

Verilog

^{®}

is a registered trademark of Cadence Design Systems, San Jose, CA.
Verilog

^{®}

是 Cadence Design Systems 公司（位于加州圣何塞）的注册商标。

Verilog HDL Quick Reference Guide
Verilog HDL 快速参考指南

Table of Contents 目录
1.0 New Features In Verilog-2001 … 1
1.0 Verilog-2001 的新特性…1
2.0 Reserved Keywords … 2
2.0 保留关键字 … 2
3.0 Concurrency … 3
3.0 并发性 … 3
4.0 Lexical Conventions … 3
4.0 词法约定 … 3
4.1 Case Sensitivity … 3
4.1 大小写敏感性 … 3
4.2 White Space Characters … 3
4.2 空白字符…3
4.3 Comments … 3
4.3 注释…3
4.4 Attributes … 3
4.4 属性…3
4.5 Identifiers (names) … 4
4.5 标识符（名称）…4
4.6 Hierarchical Path Names … 4
4.6 层次化路径名称 … 4
4.7 Hierarchy Scopes and Name Spaces … 4
4.7 层次作用域与命名空间 … 4
4.8 Logic Values … 5
4.8 逻辑值 … 5
4.9 Logic Strengths … 5
4.9 逻辑强度 … 5
4.10 Literal Real Numbers … 5
4.10 实数直接量 … 5
4.11 Literal Integer Numbers … 6
4.11 整数直接量 … 6
5.0 Module Definitions … 7
5.0 模块定义 … 7
5.1 Module Items … 7
5.1 模块项 … 7
5.2 Port Declarations … 8
5.2 端口声明…8
6.0 Data Type Declarations … 10
6.0 数据类型声明…10
6.1 Net Data Types … 10
6.1 线网数据类型…10
6.2 Variable Data Types … 12
6.2 变量数据类型…12
6.3 Other Data Types … 14
6.3 其他数据类型 … 14
6.4 Vector Bit Selects and Part Selects … 15
6.4 向量位选与部分选择 … 15
6.5 Array Selects … 15
6.5 数组选择 … 15
6.6 Reading and Writing Arrays … 15
6.6 数组读写操作 … 15
7.0 Module Instances … 16
7.0 模块实例…16
8.0 Primitive Instances … 18
8.0 原语实例…18
9.0 Generate Blocks … 20
9.0 生成块…20
10.0 Procedural Blocks … 22
10.0 过程块…22
10.1 Procedural Time Controls … 23
10.1 过程时间控制…23
10.2 Sensitivity Lists … 23
10.2 敏感列表…23
10.3 Procedural Assignment Statements … 24
10.3 过程赋值语句…24
10.4 Procedural Programming Statements … 25
10.4 过程编程语句…25
11.0 Continuous Assignments … 27
11.0 连续赋值…27
12.0 Operators … 28
12.0 运算符…28
13.0 Task Definitions … 30
13.0 任务定义…30
14.0 Function Definitions … 31
14.0 函数定义…31
15.0 Specify Blocks … 32
15.0 指定块…32
15.1 Pin-to-pin Path Delays … 32
15.1 引脚到引脚的路径延迟…32
15.2 Path Pulse (Glitch) Detection … 33
15.2 路径脉冲（毛刺）检测…33
15.3 Timing Constraint Checks … 34
15.3 时序约束检查…34
16.0 User Defined Primitives (UDPs) … 35
16.0 用户自定义原语（UDP）… 35
17.0 Common System Tasks and Functions … 37
17.0 常用系统任务与函数… 37
18.0 Common Compiler Directives … 40
18.0 常用编译器指令… 40
19.0 Configurations … 42
19.0 配置… 42
20.0 Synthesis Supported Constructs … 44
20.0 综合支持的语法结构…44

1.0 New Features In Verilog-2001
1.0 Verilog-2001 的新特性

Verilog-2001, officially the “IEEE 1364-2001 Verilog Hardware Description Language”, adds several significant enhancements to the Verilog-1995 standard.
Verilog-2001，正式名称为“IEEE 1364-2001 Verilog 硬件描述语言”，在 Verilog-1995 标准基础上增加了多项重要增强功能。

Attribute properties (page 4)
属性特性（第 4 页）
Generate blocks (page 21)
生成块（第 21 页）
Configurations (page 43)
配置（第 43 页）
Combined port and data type declarations (page 8)
组合式端口与数据类型声明（第 8 页）
ANSI C style port definitions (page 8)
ANSI C 风格端口定义（第 8 页）
Arrays of net data types (page 11)
网络数据类型的数组（第 11 页）
Multidimensional arrays (page 11, 13)
多维数组（第 11 页，第 13 页）
Variable initialization with declaration (page 13)
声明时变量初始化（第 13 页）
Bit and part selects of array words (page 16)
数组字的位选择和部分选择（第 16 页）
Indexed vector part selects (page 16)
索引向量部分选择（第 16 页）
Explicit in-line parameter passing (page 17)
显式内联参数传递（第 17 页）
Comma separated sensitive lists (page 24)
逗号分隔的敏感列表（第 24 页）
Combinational logic sensitivity wild card (page 24)
组合逻辑敏感通配符（第 24 页）
Inferred nets with any continuous assignment (page 28)
任何连续赋值推断出的网络（第 28 页）
Power operator (page 29)
幂运算符（第 29 页）
Signed arithmetic extensions (page 7, 9, 11, 13, 29, 32, 38)
有符号算术扩展（第 7、9、11、13、29、32、38 页）
ANSI C style task/function I/O definitions (page 31, 32)
ANSI C 风格的任务/函数输入输出定义（第 31、32 页）
Re-entrant tasks (page 31)
可重入任务（第 31 页）
Recursive functions (page 32)
递归函数（第 32 页）
Constant functions (page 32)
常量函数（第 32 页）
On-detect pulse detection (page 34)
边沿检测脉冲检测（第 34 页）
Negative pulse detection (page 34)
负脉冲检测（第 34 页）
Negative timing constraints (page 35)
负时序约束（第 35 页）
New timing constraint checks (page 35)
新增时序约束检查（第 35 页）
Enhanced file I/O (page 39)
增强型文件输入/输出（第 39 页）
Enhanced testing of invocation options (page 39)
增强的调用选项测试（第 39 页）
Enhanced conditional compilation (page 41)
增强的条件编译功能（第 41 页）
Disabling of implicit net declarations (page 41)
禁用隐式网络声明（第 41 页）
2.0 Reserved Keywords 2.0 保留关键字

always

如果如果无

ifnone

rpmos

assign 赋值

initial 初始

rtranif0 电阻传输门（低电平有效）

automatic

^{†}

自动

^{†}

instance

^{†}

实例

^{†}

rtranifi 电阻传输门（高阻态有效）

begin 开始

inout 双向端口

scalared 标量

buf 缓冲器

input 输入

signed 有符号

bufif0 低电平使能缓冲器

integer 整数

showcancelled

^{†}

显示已取消

^{†}

bufif1 缓冲器（高电平使能）

join 连接

small 小型

case 情况

large 大的

specify 指定

casex 情况 x

liblist

^{}

库列表

^{}

specparam 特殊参数

casez 条件选择（casez）

localparam

^{†}

局部参数

^{†}

strength 强度

cell

^{†}

单元

^{†}

macromodule 宏模块

strong0 强 0

cmos 互补金属氧化物半导体

medium 中等

strong1 强 1

config

^{†}

配置

^{†}

module 模块

supply0 电源地（逻辑 0）

deassign 取消赋值

nand 与非门

supply1 电源 1

default 默认

negedge 负边沿

table 表格

defparam 参数重定义

nmos NMOS 晶体管

task 任务

design

^{†}

设计

^{†}

nor 或非

time 时间

disable 禁用

not 非

tran 传输

edge 边沿

noshowcancelled

^{†}

不显示已取消

^{†}

tranif0 传输条件为 0

else 否则

notif0 非门（低电平触发）

tranif1 传输门（高电平触发）

end 结束

notif1 非门 1

tri 三态

endcase 结束 case 语句

or 或门

trio 三重

endconfig

^{†}

结束配置

^{†}

output 输出

tril 三重线

endfunction 结束函数

parameter 参数

triand 三态与

endgenerate

^{†}

结束生成

^{†}

pmos PMOS 晶体管

trior 三态或门

endmodule 模块结束

posedge 上升沿

trireg 三态寄存器

endprimitive 结束原语

primitive 原语

unsigned 无符号

endspecify 结束指定

pull0 下拉 0

use

^{†}

使用

^{†}

endtable 结束表

pull1 上拉

vectored 向量化

endtask 任务结束

pulldown 下拉

wait 等待

event 事件

pullup 上拉

wand 线与

for 对于

pulsestyle_onevent

^{†}

事件触发式脉冲

^{†}

weak0 弱 0

force 强制

pulsestyle_ondetect

^{†}

脉冲样式_检测时

^{†}

weak1 弱 1

forever 永远

rcmos 电阻 CMOS

while 当

fork 分叉

real 实数

wire 线网

function 函数

realtime 实时

wor 线或

generate

^{†}

生成

^{†}

reg 寄存器

xnor 同或

genvar

^{†}

生成变量

^{†}

release 释放

xor 异或

highz0 高阻态 0

repeat 重复

highz1 高阻 1

rnmos 电阻性 NMOS

3.0 Concurrency 3.0 并发性

The following Verilog HDL constructs are independent processes that are evaluated concurrently in simulation time:
以下 Verilog HDL 结构体是在仿真时间中并行评估的独立进程：

module instances 模块实例
primitive instances 原语实例
continuous assignments 连续赋值
procedural blocks 过程块

4.0 Lexical Conventions 4.0 词法约定

4.1 Case Sensitivity 4.1 大小写敏感性

Verilog is case sensitive.
Verilog 区分大小写。

4.2 White Space Characters
4.2 空白字符

blanks, tabs, newlines (carriage return), and formfeeds.
空格、制表符、换行符（回车）以及换页符。

4.3 Comments 4.3 注释

// begins a single line comment, terminated by a newline.
// 开始单行注释，以换行符终止。
/* begins a multi-line block comment, terminated by a */.
/* 开始多行块注释，以 */ 结束。

4.4 Attributes 4.4 属性

(* begins an attribute, terminated by a *).
（* 开始一个属性，以 * 结束）。

An attribute specifies special properties of a Verilog object or statement, for use by specific software tools, such as synthesis. Attributes were added in Verilog-2001.
属性用于指定 Verilog 对象或语句的特殊性质，供特定软件工具（如综合工具）使用。属性是在 Verilog-2001 中新增的。
An attribute can appear as a prefix to a declaration, module items, statements, or port connections.
属性可以作为声明、模块项、语句或端口连接的前缀出现。
An attribute can appear as a suffix to an operator or a call to a function.
属性可以作为操作符的后缀或函数调用的后缀出现。
An attribute may be assigned a value. If no value is specified, the default value is 1 .
属性可以被赋值。如果未指定值，则默认值为 1。
Multiple attributes can be specified as a comma-separated list.
可以指定多个属性，以逗号分隔的列表形式。
There are no standard attributes in the Verilog-2001 standard; Software tools or other standards will define attributes as needed.
Verilog-2001 标准中没有预定义的属性；软件工具或其他标准将根据需要定义属性。

Attribute Example 属性示例

(* full_case, parallel_case *) case (state)
(* full_case, parallel_case *) case (状态)

a. .

endcase

assign sum

= a + (^{*}

CLA=1 *) b;
赋值 sum

= a + (^{*}

CLA=1 *) b;

4.5 Identifiers (names) 4.5 标识符（名称）

Must begin with alphabetic or underscore characters a-z A-Z _
必须以字母或下划线字符开头 a-z A-Z _
May contain the characters a-z A-Z 0-9 _ and $
可包含字符 a-z A-Z 0-9 _ 和 $
May use any character by escaping with a backslash ( \ ) at the beginning of the identifier, and terminating with a white space.
可通过在标识符开头使用反斜杠（\）进行转义，并以空白字符结尾来使用任何字符。
Identifiers created by an array of instances or a generate block may also contain the characters [ and ].
由实例数组或生成块创建的标识符也可包含字符 [ 和 ]。

Examples 示例	Notes 注释
adder 加法器	legal identifier name 合法的标识符名称
XOR	uppercase identifier is unique from xor keyword 大写的标识符与 xor 关键字不同
\reset -	an escaped identifier (must be followed by a white space) 转义标识符（必须后跟空白字符）

4.6 Hierarchical Path Names
4.6 层次化路径命名

A net, variable, task or function can be referenced anywhere in the design hierarchy using either a full or relative hierarchy path.
设计层次结构中的任何网络、变量、任务或函数都可以通过完整或相对的层次路径进行引用。

A full path consists of the top-level module, followed by any number of module instance names down to the object being reference. A period is used to separate each name in the hierarchy path.
完整路径由顶层模块开始，后跟任意数量的模块实例名称直至被引用对象，层级路径中各名称间用句点分隔。
A relative path consists of a module instance name in the current module, followed by any number of module instance names down to the object being referenced. A period is used to separate each name in the hierarchy path.
相对路径由当前模块中的模块实例名称开始，后跟任意数量的模块实例名称直至被引用对象，层级路径中各名称间同样用句点分隔。

4.7 Hierarchy Scopes and Name Spaces
4.7 层次化作用域与命名空间

There are four primary types of name spaces.
主要存在四种命名空间类型。

Global names are visible in all names spaces:
全局名称在所有命名空间中可见：
Module, primitive and configuration definition names
模块、原语及配置定义名称
Text macro names (created by 'define). Macro names are only visible from the point of definition on; source code compiled prior to the definition cannot see the macro names.
文本宏名称（由'define 创建）。宏名称仅从定义点开始可见；在定义之前编译的源代码无法看到该宏名。
Scope names create a new level of hierarchy:
作用域名称创建新的层级结构：
module definitions 模块定义
function definitions 函数定义
task definitions 任务定义
named blocks (begin-end or fork-join)
命名块（begin-end 或 fork-join）
Other name spaces: 其他命名空间：
specify blocks 指定块
attributes 属性

An identifier name defined within a name space is unique to that space and cannot be defined again within the same space. In general, references to an identifier name within a scope will search first in the local scope, and then search upward through the scope hierarchy up to a module boundary.
在命名空间内定义的标识符名称对该空间是唯一的，不能在同一空间内重复定义。通常，在作用域内对标识符名称的引用会先在局部作用域中查找，然后沿作用域层次向上搜索直至模块边界。

4.8 Logic Values 4.8 逻辑值

Verilog uses a 4 value logic system for modeling. There are two additional unknown logic values that may occur internal to the simulation, but which cannot be used for modeling.
Verilog 采用四值逻辑系统进行建模。此外还有两种未知逻辑值可能出现在仿真内部，但不能用于建模。

Logic Value 逻辑值

Description 描述

0

zero, low, or false
零、低电平或假

1

one, high, or true
一、高电平或真

z

Z

0# 或 1#

high impedance (tri-stated or floating)
高阻抗（三态或浮空）

x

X

0# 或 1#

unknown or uninitialized
未知或未初始化

L

部分未知；可能是 0 或 Z，但不可能是 1（仅内部仿真值）

partially unknown; either 0 or Z, but not 1

(internal simulation value only)

H

部分未知；可能是 1 或 Z，但不可能是 0（仅内部仿真值）

partially unknown; either 1 or Z, but not 0

(internal simulation value only)

4.9 Logic Strengths 4.9 逻辑强度

Logic values can have 8 strength levels: 4 driving, 3 capacitive, and high impedance (no strength). A net with multiple drivers can have a combination of strengths, represented as a pair of octal numbers, plus the value (e.g. 65X).
逻辑值可具有 8 种强度级别：4 种驱动强度、3 种容性强度及高阻抗（无强度）。具有多个驱动源的网络可呈现强度组合，以一对八进制数字加逻辑值表示（例如 65X）。

强度等级

Strength

Level

强度名称

Strength

Name

规范关键字

Specification

Keyword

显示助记符

Display

Mnemonic

supply drive 电源驱动

supply0 地电平电源

supply1 电源高电平

Su0 地电平简写

Su1 强驱动 1

strong drive 强驱动

strong0 强驱动 0

strong1 强驱动 1

St0 状态 0

St1 状态 1

pull drive 下拉驱动

pull0 下拉 0

pull1 下拉 1

Pu0 上拉 0

Pu1 上拉 1

large capacitive 大电容

large 大的

La0 低电平 0

La1 低电平 1

weak drive 弱驱动

weak0 弱 0

weak1 弱 1

We0 我们 0

We1 我们 1

medium capacitive 中等电容性

medium 中等

Me0 金属 0 层

Me1 金属 1 层

small capacitive 小电容

small 小

Sm0 小 0

Sm1 小 1

high impedance 高阻抗

highz0 高阻态 0

highz1 高阻态 1

Hiz0 高阻 0

Hiz1 高频 1

4.10 Literal Real Numbers
4.10 实数直接量

value.value 值.值

decimal notation 十进制表示法

基数

e

指数基数

E

指数

base

e

exponent

base

E

exponent

科学计数法；

e

或

E

标记前后不应有空格

scientific notation; there should be no space before

and after the

e

E

token

Real numbers are represented in double-precision floating point form.
实数以双精度浮点数形式表示。
There must be a value on either side of the decimal point.
小数点两侧必须都有数值。
The value may only contain the characters 0-9 and underscore.
该值只能包含 0-9 数字和下划线字符。

Examples 示例	Notes 注释
0.5	must have value on both sides of decimal point 小数点两侧必须都有数值
3 e 4	3 times $10^{4} (30000)$ 3 次 $10^{4} (30000)$
$5.8 E - 3$	5.8 times $10^{- 3} (0.0058)$ 5.8 次 $10^{- 3} (0.0058)$

4.11 Literal Integer Numbers
4.11 字面整型数

value 值	unsized decimal integer 无位宽十进制整数
size'base value 位宽'基数数值	sized integer in a specific radix (base) 特定基数（进制）下的有位宽整数

size (optional) is the number of bits in the number. Unsized integers default to at least 32-bits.
位宽（可选）表示数值的比特位数。无位宽整数默认至少为 32 位。
'base represents the radix and sign property of the value. The base and sign characters are not case sensitive (e.g. ’ b and ’ B are equivalent).
'基数（base）表示数值的进制和符号属性。基数与符号字符不区分大小写（例如，'b 和 'B 是等效的）。'

Radix 进制	Symbol 符号	Legal Values 合法值
unsigned binary 无符号二进制	'b	0, 1, x, X, z, Z, ?,
unsigned octal 无符号八进制	'o	0-7, x, X, z, z, ?, -
unsigned decimal 无符号十进制	'd	$0 - 9$ ,
unsigned hexadecimal 无符号十六进制	'h	0-9, a-f, A-F, x, X, z, Z, ?, _
signed binary 有符号二进制	'sb	0, 1, x, X, z, Z, ?,
signed octal 有符号八进制	'so	0-7, x, X, z, z, ?, 0-7、x、X、z、Z、？
signed decimal 有符号十进制	'sd	0-9,
signed hexadecimal 有符号十六进制	'sh 'sh'	0-9, a-f, A-F, x, X, z, Z, ?,

The ? is another way of representing the $Z$ logic value.
'? 是表示 $Z$ 逻辑值的另一种方式。'
An underscore is ignored (used to enhance readability). The underscore cannot be used as the first character of the value.
'下划线被忽略（用于增强可读性）。下划线不能用作值的第一个字符。'
Values are expanded from right to left (lsb to msb).
数值从右向左扩展（从最低有效位到最高有效位）。
When size is fewer bits than value, the upper bits are truncated.
当指定位数小于数值实际位数时，高位将被截断。
When size is more bits than value, and the left-most bit of value is $0$ or $1$ , zeros are left-extended to fill the size.
当指定位数多于数值实际位数且数值最左侧位为 $0$ 或 $1$ 时，左侧用零扩展填充至指定位数。
When size is more bits than value, and the left-most bit of value is $Z$ or $X$ , the $Z$ or $X$ is left-extended to fill the size.
当指定位数多于数值实际位数且数值最左侧位为 $Z$ 或 $X$ 时，左侧用 $Z$ 或 $X$ 扩展填充至指定位数。
Signed numbers are interpreted as 2’s complement values.
有符号数被解释为 2 的补码值。
Specifying a literal number as signed affects operations on the number; it does not affect expanding a value to the specified size of the number.
将字面量数字指定为有符号数会影响对该数字的操作，但不会影响将该数值扩展至指定大小的操作。

Examples 示例	Size 大小	Sign 符号	Radix 基数	Binary Equivalent 二进制等效值
10	unsized 无大小限制	signed 有符号	decimal 十进制	$0 \dots 01010$ (32-bits) $0 \dots 01010$ （32 位）
' o7	unsized 未指定大小	unsigned 无符号	octal 八进制	$0 \dots 00111$ (32-bits) $0 \dots 00111$ （32 位）
1'b1	1 bit 1 位	unsigned 无符号	binary 二进制	1
8' sHc5 8 位有符号十六进制数 c5	8 bits 8 位	signed 有符号	hex 十六进制	11000101
6' hF0 6'hF0	6 bits 6 位	unsigned 无符号	hex 十六进制	110000 (truncated) 110000（截断）
6' hA 6 位十六进制 A	6 bits 6 位	unsigned 无符号	hex 十六进制	001010 (zero filled) 001010（零填充）
6' shA 6 位有符号十六进制数	6 bits 6 位	signed 有符号	hex 十六进制	001010 (zero filled) 001010（零填充）
6'bZ	6 bits 6 位	unsigned 无符号	binary 二进制	ZZZZZZ (Z filled) ZZZZZZ（填充 Z）

5.0 Module Definitions 5.0 模块定义

Verilog HDL models are represented as modules.
Verilog HDL 模型以模块形式表示。

            ANSI-C Style Port List (added in Verilog-2001)
module module_name
    #(parameter_declaration, parameter_declaration,... )
    (port_declaration port_name, port_name,...,
        port declaration port name, port name,...);
    module items
endmodule
                    Old Style Port List
module module_name (port name, port name, ... );
    port_declaration port_name, port_name,...;
    port_declaration port_name, port_name,...;
    module items
endmodule

(refer to the next page for the syntax of port declarations)
（端口声明的语法请参阅下一页）
port name can be either:
端口名称可以是以下两种形式之一：

A simple name, which implicitly connects the port to an internal signal with the same name.
简单名称，这会隐式地将端口连接到具有相同名称的内部信号。
A name with an explicit internal connection, in the form of .port_name(signal), which connects the port to an internal signal with a different name, or a bit select, part select, or concatenation of internal signals.
一种具有显式内部连接的名称，形式为.port_name(signal)，用于将端口连接到名称不同的内部信号，或内部信号的位选、部分选择或拼接。
Note: it is the internal signal name that is given a direction, not the port name.
注意：赋予方向性的是内部信号名称，而非端口名称。
The keyword macromodule is a synonym for module.
关键字 macromodule 是 module 的同义词。

5.1 Module Items 5.1 模块项

A module may contain any of the following items:
一个模块可以包含以下任意项：

data_type_declarations 数据类型声明	(see section 6.0) （参见第 6.0 节）
parameter_declarations 参数声明	(see section 6.3) （参见第 6.3 节）
module_instances 模块实例	(see section 7.0) （参见第 7.0 节）
primitive_instances 原语实例	(see section 8.0 ) （参见第 8.0 节）
generate_blocks 生成块	(see section 9.0) （参见第 9.0 节）
procedural_blocks 过程块	(see section 10.0) （参见第 10.0 节）
continuous_assignments 连续赋值	(see section 11.0) （参见第 11.0 节）
task_definitions 任务定义	(see section 13.0) （参见第 13.0 节）
function_definitions 函数定义	(see section 14.0) （参见第 14.0 节）
specify_blocks 指定块	(see section 15.0) （参见第 15.0 节）

Module items may appear in any order, but port, data_type or parameter declarations must come before the declared name is referenced.
模块项可以按任意顺序出现，但端口、数据类型或参数声明必须在引用已声明名称之前完成。
Module functionality may be represented as:
模块功能可表示为：
Behavioral or RTL - modeled with procedural blocks or continuous assignment statements.
行为级或 RTL 级——通过过程块或连续赋值语句建模。
Structural - a netlist of module instances or primitive instances.
结构化的 - 模块实例或原语实例的网络列表。
A mix of behavioral and structural.
行为化与结构化的混合。

5.2 Port Declarations 5.2 端口声明

Combined Declarations (added in Verilog-2001)
组合声明（Verilog-2001 新增）

port_direction data_type signed range port_name, port_name, ... ;
端口方向数据类型有符号范围端口名, 端口名, ... ;

Old Style Declarations 旧式声明

port_direction signed range port_name, port_name, ... ;
端口方向有符号范围端口名, 端口名, ... ;

data_type_declarations (see section 6.0)
数据类型声明（参见第 6.0 节）

port_direction is declared as:
端口方向声明为：
input for scalar or vector input ports.
input 用于标量或向量输入端口。
output for scalar or vector output ports.
output 用于标量或向量输出端口。
inout for scalar or vector bidirectional ports.
inout 用于标量或向量双向端口。
data_type (optional) is any of the types listed in section 6.0, except real. Combined port/data type declarations were added in Verilog-2001.
data_type（可选）可以是 6.0 节中列出的任何类型，除了 real 类型。组合端口/数据类型声明是在 Verilog-2001 中新增的。
signed (optional) indicates that values passed through the port are interpreted as 2’s complement signed values. If either the port or the data type of the internal signal connected to the port are declared as signed, then both are signed. Signed ports were added in Verilog-2001.
signed（可选）表示通过端口传递的值被解释为 2 的补码有符号值。如果端口或连接到端口的内部信号的数据类型中任意一个被声明为有符号，则两者均为有符号。有符号端口是在 Verilog-2001 中新增的。
range (optional) is a range from [msb :lsb] (most-significant-bit to least-significant-bit).
range（可选）是一个从[msb:lsb]（最高有效位到最低有效位）的范围。
If no range is specified, ports are 1-bit wide.
如果未指定范围，则端口宽度为 1 位。
The msb and Isb must be a literal number, a constant, an expression, or a call to a constant function.
最高有效位（msb）和最低有效位（lsb）必须是一个字面数字、常量、表达式或对常量函数的调用。
Either little-endian convention (the $l s b$ is the smallest bit number) or bigendian convention (the Isb is the largest bit number) may be used.
可以使用小端序约定（ $l s b$ 是最小的位编号）或大端序约定（lsb 是最大的位编号）。
The maximum port size may be limited, but will be at least 256 bits. Most software tools have a limit of 1 million bits.
端口最大尺寸可能有限制，但至少为 256 位。大多数软件工具的限制为 100 万位。
Port/data type connection rules:
端口/数据类型连接规则：

input ports 输入端口

output ports 输出端口

inout ports 双向端口

模块实例（模块外部）

Module Instance

(outside the module)

表达式、线网或变量类型（实数除外）

expression, net

or variable types

(except real)

net types only 仅限线网类型

模块定义（模块内部）

Module Definition

(inside the module)

net types only 仅限网络类型

网络或变量类型（实数除外）

net or

variable types

(except real)

net types only 仅限网络类型

A real variable cannot be directly connected to a port. Real numbers can first be converted to or from 64-bit vectors using the $realtobits and $bitstoreal system tasks.
实数变量不能直接连接到端口。可先通过$realtobits 和$bitstoreal 系统任务将实数与 64 位向量相互转换。
The port range and data type range must be the same (if different, some software tools will use the data type size instead of reporting an error).
端口范围与数据类型范围必须相同（若存在差异，部分软件工具会采用数据类型大小而不报错）。
The port direction must be declared before the data type is declared.
必须在声明数据类型前声明端口方向。

10 VEriLog HDL QUick Reference Guide
Verilog HDL 快速参考指南 10

Port Declaration Examples
端口声明示例

Notes 注释

input a,b,sel; 输入 a, b, sel;

three scalar (1-bit) ports
三个标量（1 位）端口

input signed [15:0] a, b;
输入有符号数 [15:0] a, b;

两个 16 位端口，采用 2 的补码值传递，遵循小端序约定

two 16-bit ports that pass 2’s

complement values, little

endian convention

output signed [31:0] result;
输出有符号数 [31:0] 结果;

32 位端口；通过该端口传递的数值采用 2 的补码形式

32-bit port; values passed

through the port are in 2's

complement form

output reg signed [32:1] sum;
输出寄存器型有符号数 [32:1] 求和;

32 位端口；与该端口连接的内部信号为有符号 reg 数据类型

32-bit port; the internal

signal connected to the port

is a signed reg data type

inout [0:15] data_bus; 双向[0:15]数据总线

big endian convention 大端序约定

input [15:12] addr ;
输入[15:12]地址线

msb:lsb may be any integer
最高有效位到最低有效位可以是任意整数值

参数 WORD

= 32;

输入 [WORD-1:0] 地址;

parameter WORD

= 32;

input [WORD-1:0] addr;

声明中可以使用常量表达式

constant expressions may be

used in the declaration

参数 SIZE

= 4096;

输入 [log2(SIZE)

- 1 : 0]

地址;

parameter SIZE

= 4096;

input [log2(SIZE)

- 1 : 0]

addr ;

常量函数可以在声明时调用

constant functions may be

called in the declaration

6.0 Data Type Declarations
6.0 数据类型声明

Verilog has two major data type classes:
Verilog 有两大主要数据类型类别：

Net data types are used to make connections between parts of a design.
网络数据类型用于连接设计中的各个部分
Nets reflect the value and strength level of the drivers of the net or the capacitance of the net, and do not have a value of their own.
网络反映其驱动源的值与强度等级或自身的电容特性，本身并不具备独立的值。
Nets have a resolution function, which resolves a final value when there are multiple drivers on the net.
网络具有决议功能，当存在多个驱动源时能决议出最终值。
Variable data types are used as temporary storage of programming data.
变量数据类型用于临时存储程序数据。
Variables can only be assigned a value from within an initial procedure, an always procedure, a task or a function.
变量只能通过 initial 过程、always 过程、任务或函数进行赋值。
Variables can only store logic values; they cannot store logic strength.
变量只能存储逻辑值，无法存储逻辑强度。
Variables are un-initialized at the start of simulation, and will contain a logic X until a value is assigned.
变量在仿真开始时未初始化，在赋值前将保持逻辑 X 状态。

General Rules For Choosing The Correct Data Type Class
选择正确数据类型类别的通用规则

当信号由模块输出、原语输出或连续赋值驱动时

when a signal is driven by a module output, a primitive

output, or a continuous assignment

use a net type
使用网络类型

when a signal is assigned a value in a Verilog procedure
当信号在 Verilog 过程中被赋值时

use a variable type
使用变量类型

6.1 Net Data Types
6.1 网络数据类型

net_type signed [range] #(delay) net_name [array], ... ;
net_type (drive_strength) signed [range] #(delay) net_name =
continuous_assignment;
trireg (capacitance_strength) signed [range] #(delay, decay_time)
net_name [array], ...;

Nets are used connect structural components together.
网络用于将结构组件连接在一起。

A net data type must be used when a signal is:
当信号满足以下情况时，必须使用线网数据类型：
Driven by the output of a module instance or primitive instance.
由模块实例或原语实例的输出驱动。
Connected to an input or inout port of the module in which it is declared.
连接到声明该信号的模块的输入或双向端口。
On the left-hand side of a continuous assignment.
位于连续赋值语句的左侧。
net_type is one of the following keywords:
网络类型是以下关键字之一：

wire 线网	interconnecting wire; CMOS resolution 互连线网；CMOS 解析
wor 线或	wired outputs OR together; ECL resolution 线或输出；ECL 集电极开路逻辑解析
wand 线与	wired outputs AND together; open-collector resolution 线与输出；集电极开路解析
supply0 电源地（逻辑 0）	constant logic 0 (supply strength) 恒定逻辑 0（电源强度）
supply1 电源 1	constant logic 1 (supply strength) 恒定逻辑 1（电源强度）
tri0 三态 0	pulls down when tri-stated 三态时下拉
tri1 三态 1	pulls up when tri-stated 三态时上拉
tri 三态	same as wire 同 wire 类型
trior 三态或线	same as wor 同 wor 类型
triand 三态与线	same as wand 同 wand（线与）功能相同
trireg 三态寄存器（trireg）	holds last value when tri-stated (capacitance strength) 三态时保持最后值（具有电容强度特性）

signed (optional) indicates that values are interpreted as 2’s complement signed values. If either a port or the net connected to the port is declared as signed, then both are signed. Signed nets were added in Verilog-2001.
有符号（可选）表示数值按 2 的补码有符号数解释。若端口或其连接的网络任一被声明为有符号，则两者均为有符号。有符号网络类型在 Verilog-2001 中新增。
[range] (optional) is a range from [msb :Isb] (most-significant-bit to least-significant-bit).
[范围]（可选）表示从[最高有效位:最低有效位]的位宽范围。
If no range is specified, the nets are 1-bit wide.
若未指定范围，则网络默认为 1 位宽。
The msb and Isb must be a literal number, a constant, an expression, or a call to a constant function.
最高有效位和最低有效位必须为字面数值、常量、表达式或对常量函数的调用。
Either little-endian convention (the $I s b$ is the smallest bit number) or bigendian convention (the $I s b$ is the largest bit number) may be used.
可采用小端序约定（ $I s b$ 表示最小位编号）或大端序约定（ $I s b$ 表示最大位编号）。
The maximum net size may be limited, but will be at least 65,536 bits $(2^{16})$ bits. Most software tools have a limit of 1 million bits.
最大网络规模可能受限，但至少为 65,536 位 $(2^{16})$ 位。大多数软件工具的限制为 100 万位。
delay (optional) may only be specified on net data types. The syntax is the same as primitive delays (refer to section 8.0).
延迟（可选）仅可在网络数据类型上指定。语法与原始延迟相同（参见第 8.0 节）。
[array] is [first_address : last_address] [first_address : last_address]…
[数组]表示为[首地址:末地址][首地址:末地址]…
Any number of array dimensions may be declared. Arrays of nets were added in Verilog-2001.
可声明任意数量的数组维度。网络数组功能是在 Verilog-2001 中新增的。
first_address and last_address must be a literal number, a constant, an expression, or a call to a constant function.
first_address 和 last_address 必须是一个字面数字、常量、表达式或对常量函数的调用。
Either ascending or descending address order may be used.
可以使用升序或降序的地址顺序。
The maximum array size for each dimension may be limited, but is at least 16,777,216 ( $2^{24}$ ). Most software tools have unlimited array sizes.
每个维度的最大数组大小可能有限制，但至少为 16,777,216（ $2^{24}$ ）。大多数软件工具没有数组大小限制。
(strength) (optional) is specified as (strength1, strength0) or (strength0, strength1). See section 4.9 for the strength keywords.
（强度）（可选）指定为（strength1, strength0）或（strength0, strength1）。有关强度关键字，请参见第 4.9 节。
decay_time (optional) specifies the amount of time a trireg net will store a charge after all drivers turn-off, before decaying to logic X. The syntax is (rise_delay, fall_delay, decay_time). The default decay is infinite.
decay_time（可选）指定了在所有驱动关闭后，trireg 网络存储电荷的时间长度，之后会衰减至逻辑 X。语法为(rise_delay, fall_delay, decay_time)。默认衰减时间为无限。
The keywords vectored or scalared may be used immediately following the net_type keyword. Software tools and/or the Verilog PLI may restrict access to individual bits within a vector that is declared as vectored.
关键字 vectored 或 scalared 可紧接在 net_type 关键字后使用。软件工具和/或 Verilog PLI 可能会限制对声明为 vectored 的向量中单个位的访问。

Net Declaration Examples
网络声明示例

Notes 注释

Wire a, b, c;
线网 a, b, c;

3 scalar (1-bit) nets
3 个标量（1 位）网络

tri1 [7:0] data_bus; 三态 1 [7:0] 数据总线;

8-bit net, pulls-up when tri-stated
8 位网络，三态时上拉

wire signed [1:8] result;
有符号的 8 位线网 result;

an 8-bit signed net
一个 8 位有符号线网

Wire [7:0] Q [0:15][0:256];
16x256 的 8 位线网数组 Q;

a 2-dimensional array of 8-bit wires
一个二维的 8 位线网数组

Wire #(2.4,1.8) carry; 线网 #(2.4,1.8) 进位;

a net with rise, fall delays
具有上升、下降延迟的线网

线网 [0:15] (强 1, 弱 0) 求和 a a b;

Wire [0:15] (strong1, pull0)

sum a a b;

具有驱动强度和连续赋值的 16 位线网

a 16-bit net with drive strength and a

continuous assignment

三态寄存器（小型）#(0,0,35) ram_bit;

trireg (small)

#(0,0,35) ram_bit;

具有小电容和 35 个时间单位衰减时间的网络

net with small capacitance and 35

time unit decay time

6.2 Variable Data Types
6.2 变量数据类型

variable_type signed [range] variable_name, variable_name, ... ;
变量类型有符号 [范围] 变量名, 变量名, ... ;

variable_type signed [range] variable_name = initial_value, ... ;
变量类型有符号 [范围] 变量名 = 初始值, ... ;

variable_type signed [range] variable_name [array], ... ;
变量类型有符号 [范围] 变量名 [数组], ... ;

Variable data types are used for programming storage in procedural blocks.
变量数据类型用于在过程块中编程存储。

Variables store logic values only, they do not store logic strength.
变量仅存储逻辑值，不存储逻辑强度。
A variable data type must be used when the signal is on the left-hand side of a procedural assignment.
当信号位于过程赋值语句的左侧时，必须使用变量数据类型。
Variables were called “registers” in older versions of the Verilog standard.
在旧版 Verilog 标准中，变量被称为“寄存器”。
variable_type is one of the following:
变量类型为以下之一：

reg 寄存器类型

任意位宽的变量；除非显式声明为有符号数，否则默认为无符号

a variable of any bit size; unsigned unless explicitly

declared as signed

integer 整数类型

a signed 32-bit variable
有符号 32 位变量

time 时间类型

an unsigned 64-bit variable
一个无符号的 64 位变量

real 实数

a double-precision floating point variable
一个双精度浮点变量

realtime 实时

same as real 同 real 类型

signed (optional) may only be used with reg variables, and indicates that values are interpreted as 2’s complement signed values. If either a port or the reg connected to the port is declared as signed, then both are signed. Signed reg variables were added in Verilog-2001.
signed（可选）仅可与 reg 变量一起使用，表示数值将被解释为 2 的补码有符号数。若端口或其连接的 reg 被声明为 signed，则二者均为有符号类型。带符号的 reg 变量是在 Verilog-2001 中新增的。
[range] (optional) may only be used with reg variables, and is a range from [msb :lsb] (most-significant-bit to least-significant-bit).
[范围]（可选）仅适用于 reg 变量，表示从[最高有效位:最低有效位]的位宽范围。
If no range is specified, then reg variables are 1-bit wide.
若未指定范围，则 reg 变量默认为 1 位宽。
The msb and Isb must be a literal number, a constant, an expression, or a call to a constant function.
最高有效位（msb）和最低有效位（lsb）必须是一个字面数字、常量、表达式或对常量函数的调用。
Either little-endian convention (the Isb is the smallest bit number) or bigendian convention (the $I s b$ is the largest bit number) may be used.
可以使用小端序约定（最低有效位是最小的位编号）或大端序约定（最高有效位是最大的位编号）。
The maximum reg size may be limited, but will be at least $65, 536 (2^{16})$ bits. Most software tools have a limit of 1 million bits.
寄存器最大容量可能有限制，但至少会有 $65, 536 (2^{16})$ 位。大多数软件工具的限制为 100 万位。
[array] is [first_address : last_address] [first_address : last_address]…
[数组]是[起始地址 : 结束地址] [起始地址 : 结束地址]…
Any number of array dimensions may be declared. Variable arrays of more than one dimension were added in Verilog-2001.
可以声明任意维度的数组。Verilog-2001 新增了对多维变量数组的支持。
first_address and last_address must be a literal number, a constant, an expression, or a call to a constant function.
first_address 和 last_address 必须是一个字面数字、常量、表达式或对常量函数的调用。
Either ascending or descending address order may be used.
可以使用升序或降序的地址顺序。
The maximum array size for each dimension may be limited, but is at least 16,777,216 ( $2^{24}$ ). Most software tools have unlimited array sizes.
每个维度的最大数组大小可能有限制，但至少为 16,777,216（ $2^{24}$ ）。大多数软件工具对数组大小没有限制。
A one-dimensional array of reg variables with is referred to as a memory.
由 reg 变量构成的一维数组被称为存储器。
initial_value (optional) sets the initial value of the variable.
initial_value（可选）用于设置变量的初始值。
The value is set in simulation time 0 , the same as if the variable had been assigned a value in an initial procedure.
该值在仿真时间 0 时被设置，等同于通过 initial 过程对变量进行赋值的效果。
If not initialized, the default value for reg, integer and time variables is X , and the initial value for real and realtime variables is 0.0 .
若未初始化，reg、integer 及 time 类型变量的默认值为 X，而 real 与 realtime 类型变量的初始值为 0.0。
Specifying the initial value as part of the variable declaration was added in Verilog-2000
在 Verilog-2000 中新增了将初始值作为变量声明的一部分进行指定的功能

14 VERILOG HDL QUICK REFERENCE GUIDE
14 Verilog HDL 快速参考指南

The keywords vectored or scalared may be used immediately following the reg keyword. Software tools and/or the Verilog PLI may restrict access to individual bits within a vector that is declared as vectored.
关键字 vectored 或 scalared 可紧接在 reg 关键字后使用。软件工具和/或 Verilog PLI 可能会限制对声明为 vectored 的向量中各个位的访问。

Variable Declaration Examples 变量声明示例	Notes 注释
reg a, b, c; 寄存器变量 a, b, c;	three scalar (1-bit) variables 三个标量（1 位）变量
reg signed $[7 : 0] d 1, d 2;$ 带符号的寄存器变量 $[7 : 0] d 1, d 2;$	two 8-bit signed variables 两个 8 位带符号变量
reg $[7 : 0] Q [0 : 3] [0 : 15];$ 寄存器 $[7 : 0] Q [0 : 3] [0 : 15];$	a 2-dimensional array of 8-bit variables 一个 8 位变量的二维数组
integer i, j; 整型变量 i, j;	two signed integer variables 两个有符号整型变量
real r1, r2; 实数型变量 r1, r2	two double-precision variables 两个双精度变量
reg clock $= 0$ , reset $= 1;$ 寄存器变量 clock $= 0$ , reset $= 1;$	two reg variables with initial values 两个带有初始值的寄存器变量

6.3 Other Data Types
6.3 其他数据类型

parameter 参数

用于存储整数、实数、时间、延迟或 ASCII 字符串的运行时常量；可为模块的每个实例重新定义（参见第 7.0 节）。

a run-time constant for storing integers, real numbers, time,

delays, or ASCII strings; may be redefined for each instance

of a module (see section 7.0).

localparam 局部参数

用于存储整数、实数、时间、延迟或 ASCII 字符串的局部常量；不可直接重定义，但可通过将其赋值为参数的值间接重定义。

a local constant for storing integers, real numbers, time,

delays, or ASCII strings; may not be directly redefined, but

may be indirectly redefined by assigning the localparam the

value of a parameter..

specparam 指定参数

用于存储整数、实数、时间、延迟或 ASCII 字符串的指定块常量；可在模块作用域或指定块作用域中声明；可通过 SDF 文件或 PLI 重定义。

a specify block constant for storing integers, real numbers,

time, delays or ASCII strings; may be declared in the module

scope or the specify block scope; may be redefined through

SDF files or the PLI.

genvar 生成变量

仅用于生成循环内部的临时变量；无法在其他任何地方使用，且在仿真期间不可读取。

a temporary variable used only within a generate loop; cannot

be used anywhere else, and cannot be read during simulation.

event 事件

无逻辑值或数据存储的瞬时标志；可用于同步模块内的并发活动。

a momentary flag with no logic value or data storage; can be

used for synchronizing concurrent activities within a module.

Declaration syntax: 声明语法：

parameter signed [range] constant_name = value, ... ;
parameter signed [范围] 常量名 = 值, ... ;

parameter constant_type constant_name = value, ... ;
参数常量类型常量名 = 值, ... ;

localparam signed [range] constant_name = value, ...;
局部参数有符号 [范围] 常量名 = 值, ...;

localparam constant_type constant_name = value, ... ;
局部参数常量类型常量名 = 值, ... ;

specparam constant_name = value, ... ;
特殊参数常量名 = 值, ... ;

event event_name, ... ;
事件 event_name, ... ;

signed (optional) indicates that values are interpreted as 2’s complement signed values. Signed constants were added in Verilog-2001.
signed（可选）表示数值将被解释为 2 的补码有符号值。有符号常量是在 Verilog-2001 中新增的。
[range] (optional) is a range from [msb :lsb] (most-significant-bit to least-significant-bit).
[范围]（可选）表示从[最高有效位:最低有效位]的位宽范围。
If no range is specified, the constant will default to the size of the last value initially assigned to it after any parameter redefinitions.
若未指定范围，常量将默认采用参数重定义后首次赋值时的最后数值的位宽。
The msb and Isb must be a literal number, a constant, an expression, or a call to a constant function.
最高有效位（msb）和最低有效位（lsb）必须是一个字面数字、常量、表达式或对常量函数的调用。
Either little-endian convention (the Isb is the smallest bit number) or bigendian convention (the $I s b$ is the largest bit number) may be used.
可以使用小端序约定（最低有效位是最小的比特编号）或大端序约定（最高有效位是最大的比特编号）。
The maximum range may be limited, but will be at least $65, 536 (2^{16})$ bits. Most software tools have a limit of 1 million bits.
最大范围可能有限制，但至少为 $65, 536 (2^{16})$ 比特。大多数软件工具的限制为 100 万比特。
constant_type (optional) can be integer, time, real or realtime. A constant declared with a type will have the same properties as a variable of that type. If no type is specified, the constant will default to the data type of the last value assigned to it, after any parameter redefinitions.
常量类型（可选）可以是整数、时间、实数或实时数。带有类型声明的常量将具有与该类型变量相同的属性。如果未指定类型，常量将默认为分配给它的最后一个值的数据类型（在参数重定义之后）。

Data Type Examples 数据类型示例	Notes 注释
parameter $[2 : 0]$ s1 $= 3^{'}$ b001, 参数 $[2 : 0]$ s1 $= 3^{'}$ b001,
s2 $= 3^{'}$ b010,
s3 $= 3^{'} b 100;$	three 3-bit constants 三个 3 位常量
parameter integer period $= 10;$ 参数整型周期 $= 10;$
localparam integer constant 局部参数整型常量
event data_ready, data_sent; 事件 data_ready, data_sent;	two event data types 两种事件数据类型

6.4 Vector Bit Selects and Part Selects
6.4 向量位选择与部分选择

vector_name[bit_number]

Bit Select
向量名[位编号]

位选择

Constant Part Select 常量部分选择

vector_name[bit_number: bit_number]
向量名[位编号: 位编号]

Variable Part Select (added in Verilog-2001)
可变部分选择（Verilog-2001 新增）

vector_name[starting_bit_number + : part_select_width]
向量名[起始位编号 + : 部分选择宽度]

vector_name[starting_bit_number - : part_select_width]
向量名[起始位编号 - : 部分选择宽度]

A bit select can be an integer, a constant, a net, a variable or an expression.
位选择可以是一个整数、常量、网络、变量或表达式。
A constant part select is a group of bits from within the vector
常量部分选择是从向量中选取的一组连续位。
The part select must be contiguous bits.
部分选择必须是连续的位。
The bit numbers must be a literal number or a constant.
位编号必须是一个字面数字或常量。
The order of the part select must be consistent with the declaration of the vector (e.g. if the lsb is the the lowest bit number in the declaration, then the lsb of the part select must also be the lowest bit number).
部分选择的顺序必须与向量的声明一致（例如，如果最低有效位在声明中是最小的位编号，那么部分选择的最低有效位也必须是最小的位编号）。
Variable part selects can vary the starting point of the part select, but the width of the part select must be a literal number, a constant or a call to a constant function. Variable part selects were added in Verilog-2001.
可变部分选择可以改变选择的起始点，但选择的宽度必须是一个字面数字、常量或对常量函数的调用。可变部分选择是在 Verilog-2001 中新增的。
+: indicates the part select increases from the starting point.
"+:"表示部分选择从起始点开始递增。
- : indicates the part select decreases from the starting point.
  表示部分选择从起点开始递减。

6.5 Array Selects 6.5 数组选择

array_name[index][index]...
数组名[索引][索引]...

array_name[index][index]... [bit_number]
数组名[索引][索引]...[位编号]

array_name[index][index]...[part_select]
数组名[索引][索引]...[部分选择]

An array select can be an integer, a net, a variable, or an expression.
数组选择可以是一个整数、网络、变量或表达式。
Multiple indices, bit selects and part selects from an array were added in Verilog-2001.
Verilog-2001 新增了对数组的多重索引、位选择和部分选择功能。

6.6 Reading and Writing Arrays
6.6 数组的读取与写入

Only one element at a time within an array can be read from or written to.
数组中的元素每次只能读取或写入一个。
A memory array (a one-dimensional array of reg variables) can be loaded using the $readmemb, $readmemh, $sreadmemb, or $sreadmemh system tasks.
可以使用$readmemb、$readmemh、$sreadmemb 或$sreadmemh 系统任务加载内存数组（一组一维的 reg 变量）。

7.0 Module Instances 7.0 模块实例

Port Order Connections 端口顺序连接

module_name instance_name instance_array_range (signal, signal, ...) ;
模块名实例名实例数组范围 (信号, 信号, ...) ;

Port Name Connections 端口名称连接

module_name instance_name instance_array_range
模块名实例名实例数组范围

( .port_name_(signal), .port_name(signal), ... );
( .端口名_(信号), .端口名(信号), ... );

Explicit Parameter Redefinition
显式参数重定义

defparam heirarchy_path.parameter_name = value;
defparam 层次路径.参数名 = 值;

In-line Implicit Parameter Redefinition
内联隐式参数重定义

module_name #(value,value, ...) instance_name (signal, ... );
模块名 #(值, 值, ...) 实例名 (信号, ... );

In-line Explicit Parameter Redefinition (added in Verilog-2001)
行内显式参数重定义（Verilog-2001 新增）

module_name #(.parameter_name(value),
模块名 #(.参数名(值),

.parameter_name(value), ...) instance_name (signal, ... );
.参数名(值), ...) 实例名 (信号, ... );

Port order connections list the signals in the same order as the port list in the module definition. Unconnected ports are designated by two commas with no signal listed.
端口顺序连接按照模块定义中端口列表的顺序列出信号。未连接的端口用两个连续的逗号表示，中间不列出信号。
Port name connections list both the port name and signal connected to it, in any order.
端口名称连接列表可以任意顺序列出端口名及与其连接的信号。
instance_name (required) is used to make multiple instances of the same module unique from one another.
实例名称（必需）用于使同一模块的多个实例彼此区分。
instance_array_range (optional) instantiates multiple modules, each instance is connected to different bits of a vector.
实例数组范围（可选）用于实例化多个模块，每个实例连接到向量的不同位。
The range is specified as [left_hand_index : right_hand_index].
范围以[左端索引 : 右端索引]的形式指定。
If the bit width of a module port in the array is the same as the width of the signal connected to it, the full signal is connected to each instance of the module.
如果模块端口的位宽与所连接信号的宽度相同，则完整信号会连接到模块的每个实例。
If the bit width of a module port is different than the width of the signal connected to it, each module port instance is connected to a part select of the signal, with the right-most instance index connected to the right-most part of the vector, and progressing towards the left.
如果模块端口的位宽与所连接信号的宽度不同，则每个模块端口实例将连接到信号的一部分选择，最右侧的实例索引连接到向量的最右侧部分，并依次向左推进。
There must be the correct number of bits in each signal to connect to all instances (the signal size and port size must be multiples).
每个信号中必须有足够的位数来连接到所有实例（信号大小和端口大小必须是倍数关系）。
Instance arrays were added in Verilog-1995, but many software tools did not support them until Verilog-2001.
实例数组在 Verilog-1995 中引入，但许多软件工具直到 Verilog-2001 才支持它们。
Multiple instances of a module can also be created using a generate block (see section 9.0).
也可以通过使用 generate 块来创建模块的多个实例（参见第 9.0 节）。
parameter values within a module may be redefined for each instance of the module. Only parameter declarations may be redefined; localparam and specparam constants cannot be redefined.
模块内的参数值可以为每个模块实例重新定义。只有参数声明可以被重新定义；localparam 和 specparam 常量不能被重新定义。
Explicit redefinition uses a defparam statement with the parameter’s hierarchical name.
显式重定义使用带有参数层次名称的 defparam 语句。
In-line implicit redefinition uses the # token as part of the module instantiation. Parameter values are redefined in the same order in which they are declared within the module.
内联隐式重定义使用#符号作为模块实例化的一部分。参数值按照它们在模块内声明的顺序进行重新定义。
In-line explicit redefinition uses the # token as part of the module instantiation. Parameter values may be redefined in any order. In-line explicit parameter redefinition was added in Verilog-2001.
行内显式重定义使用#符号作为模块实例化的一部分。参数值可以按任意顺序重新定义。行内显式参数重定义功能是在 Verilog-2001 中新增的。

18 Verilog HDL Quick Reference Guide
18 Verilog HDL 快速参考指南

Module Instance Examples
模块实例示例

\begin{array}{r} module reg4 (output wire [3:0] q, \\ input wire [3:0] d, \\ input wire \\ ink); \end{array}

//port order connection, no connection to 2nd port position dff u1 (q[0], , d[0], clk);
//端口顺序连接，第二个端口位置未连接 dff u1 (q[0], , d[0], clk);

//端口名称连接，qb 未连接 dff u2 (.clk(clk),.q(q[1]),.data(d[1]));

//port name connection, qb not connected

dff u2 (.clk(clk),.q(q[1]),.data(d[1]));

//explicit parameter redefinition dff u3 (q[2], ,d[2], clk); defparam u3.delay = 3.2;
//显式参数重定义 dff u3 (q[2], ,d[2], clk); defparam u3.delay = 3.2;

//in-line implicit parameter redefinition dff #(2) u4 (q[3], , d[3], clk);
//行内隐式参数重定义 dff #(2) u4 (q[3], , d[3], clk);

//行内显式参数重定义 dff #(.delay(3)) u5 (q[3], , d[3], clk); endmodule

//in-line explicit parameter redefinition

dff #(.delay(3)) u5 (q[3], , d[3], clk); endmodule

module dff (output q, output qb, input data, input clk);

参数 delay = 1; //默认延迟参数 dff_udp #(delay) (q, data, clk); 非门 (qb, q); 结束模块

parameter delay = 1; //default delay parameter dff_udp #(delay) (q, data, clk); not (qb, q);

endmodule

Array of Instances Example 实例数组示例
module tribuf64bit (output wire [63:0] out, 模块三态缓冲 64 位 (输出线 [63:0] out,
input wire [63:0] in, 输入线 [63:0] in,
input wire 输入线

//array of 8 8-bit tri-state buffers; each instance is connected //to 8 -bit part selects of the 64-bit vectors; The scalar enable line //is connected to all instances
//8 个 8 位三态缓冲器组成的数组；每个实例连接到 64 位向量的 8 位部分选择；标量使能线连接到所有实例
tribuf8bit i[7:0] (out, in, enable); endmodule
tribuf8bit i[7:0] (输出, 输入, 使能); 结束模块

module tribuf8bit (output wire [7:0] y,
    input wire [7:0] a,
    input wire en);

//array of 8 Verilog tri-state primitives; each bit of the
//8 个 Verilog 三态原语组成的数组；每个位对应
//vectors is connected to a different primitive instance
//vectors 连接到另一个基本元件实例
bufif1 u[7:0] (y, a, en);
endmodule

8.0 Primitive Instances 8.0 基本元件实例

gate_type (drive_strength) #(delay) instance_name [instance_array_range] (terminal, terminal, … ) ;
门类型（驱动强度）#（延迟）实例名[实例数组范围]（端子，端子，…）;
switch_type #(delay) instance_name
开关类型#（延迟）实例名
[instance_array_range] (terminal, terminal, … );
[实例数组范围]（端子，端子，…）;

Gate Primitives 门级原语

Switch Primitives 开关原语

Terminal Order and Quantity
终端顺序与数量

pmos rpmos（P 型金属氧化物半导体）

pmos

rpmos

nmos rnmos（N 型金属氧化物半导体）

nmos

rnmos

(1-output, 1-input, 1-control)
(1 输出, 1 输入, 1 控制)

cmos CMOS（互补金属氧化物半导体）

rcmos RCMOS（电阻互补金属氧化物半导体）

(1-output, 1-input, n-control, p-control)
(1 输出端，1 输入端，n 控制端，p 控制端)

tran 传输门

rtran 电阻传输

(2-bidirectional-inouts)
(2-双向输入输出)

条件 0 传输电阻条件 0 传输

tranif0

rtranif0

条件 1 传输电阻条件 1 传输

tranif1

rtranif1

(2-bidirectional-inouts, 1-control)
(2 个双向输入输出端口，1 个控制端口)

delay (optional) represents the propagation delay through a primitive. The default delay is zero. Integers or real numbers may be used
延迟（可选）表示通过原语的传播延迟。默认延迟为零。可以使用整数或实数
Separate delays for 1,2 or 3 transitions may be specified.
可以为 1、2 或 3 种转换分别指定延迟。
Each transition may have a single delay or a min:typ:max delay range.
每种转换可以有一个单一延迟或一个最小:典型:最大延迟范围。

Delays 延迟

Transitions represented (in order)
按顺序表示的转换

all output transitions 所有输出转换

rise, fall output transitions
上升、下降输出转换

上升、下降、关断输出转换（关断延迟是指三态原语过渡到 Z 状态所需的时间）

rise, fall, turn-off output transitions (turn-off delay is

the time for a tri-state primitive to transition to Z )

strength (optional) is specified as (strength1, strength0) or (strength0, strength1). The default is (strong1, strong0). Refer to section 4.9 for strength keywords.
（可选）强度以(strength1, strength0)或(strength0, strength1)形式指定。默认为(strong1, strong0)。强度关键字详见第 4.9 节。
Only gate primitives may have the output drive strength specified. Switch primitives pass the input strength level to the output. Resistive switches reduce the strength level as it passes through.
仅门级原语可指定输出驱动强度。开关原语将输入强度级别传递至输出。电阻式开关在传递过程中会降低强度级别。
instance_name (optional) may used to reference specific primitives in configurations, debugging tools, schematic diagrams, etc.
（可选）实例名称可用于在配置、调试工具、原理图等中引用特定原语。

20 Verilog HDL Quick Reference Guide
Verilog HDL 快速参考指南 20

instance_array_range (optional) instantiates multiple primitives, each instance is connected to different bits of a vector.
instance_array_range（可选）用于实例化多个原语，每个实例连接到向量的不同位。
The range is specified as [left-hand-index : right-hand-index].
范围指定为 [左端索引 : 右端索引]。
Primitive instances are connected with the right-most instance index connected to the right-most bit of each vector, and progressing to the left.
原语实例的连接方式为：最右侧的实例索引连接到每个向量的最右位，并依次向左推进。
Vector signals must be the same size as the array.
向量信号必须与数组大小相同。
Scalar signals are connected to all instances in the array.
标量信号会连接到数组中的所有实例。
Instance arrays were added in Verilog-1995, but many software tools did not support them until Verilog-2001.
实例数组在 Verilog-1995 中引入，但许多软件工具直到 Verilog-2001 才支持该功能。
Multiple instances of a primitive can also be created using a generate block (see section 9.0).
也可以通过生成块创建原语的多个实例（参见第 9.0 节）。

Primitive Instance Examples 原语实例示例	Notes 注释
and i1 (out,in1,in2);	zero delay gate primitive 零延迟门原语
and #5 (o,i1, i2,i3,i4); 与门 #5 (o,i1,i2,i3,i4);	same delay for all transitions 所有转换具有相同延迟
not #(2,3) u7 (out, in) ; 非门 #(2,3) u7 (输出, 输入) ;	separate rise & fall delays 分离上升与下降延迟
buf (pull0, strong1)(y,a); 缓冲器 (弱 0, 强 1)(y,a);	output drive strengths 输出驱动强度
wire [31:0] y, a; buf #2.7 i[31:0] (y,a); 线型 [31:0] y, a; 缓冲器 #2.7 i[31:0] (y,a);	array of 32 buffers 32 个缓冲器的数组

9.0 Generate Blocks 9.0 生成块

genvar genvar_name, ...;
generate
    genvar genvar_name, ... ;
    generate_items
endgenerate

Generate blocks provide control over the creation of many types of module items. A generate block must be defined within a module, and is used to generate code within that module. Generate blocks were added in Verilog-2001.
生成块提供了对多种模块项创建过程的控制。生成块必须在模块内定义，用于在该模块中生成代码。生成块功能是在 Verilog-2001 中新增的。

genvar is an integer variable which must be a positive value. They may only be used within a generate block. Genvar variables only have a value during elaboration, and do not exist during simulation. Genvar variables must be declared within the module where the genvar is used. They may be declared either inside or outside of a generate block.
genvar 是一种整型变量，其值必须为正数。它们只能在 generate 块中使用。Genvar 变量仅在代码综合阶段具有值，在仿真时并不存在。Genvar 变量必须在使用了该 genvar 的模块内声明，可以在 generate 块内部或外部进行声明。
generate_items are:  generate_items 包括：
genvar_name = constant_expression;
genvar 名称 = 常量表达式；
net_declaration  网络声明
variable_declaration  变量声明
module_instance  模块实例化
primitive_instance  原语实例化
continuous_assignment  连续赋值
procedural_block  过程块
task_definition  任务定义
function_definition  函数定义
if (constant_expression)
如果（常量表达式）
generate_item or generate_item_group
生成项或生成项组
if (constant_expression)
如果（常量表达式）
generate_item or generate_item_group
生成项或生成项组
else  否则
generate_item or generate_item_group
生成项或生成项组
case (constant_expression)
case (常量表达式)
genvar_value : generate_item or generate_item_group
生成变量值 : 生成项或生成项组
genvar_value : generate_item or generate_item_group
生成变量值 : 生成项或生成项组
default: generate_item or generate_item_group
默认：generate_item 或 generate_item_group
endcase  结束 case 语句
for (genvar_name = constant_expression; constant_expression;
for (生成变量名 = 常量表达式; 常量表达式;
genvar_name = constant_expression)
生成变量名 = 常量表达式)
generate_item or generate_item_group
生成项或生成项组
generate_item_group is:  生成项组定义为：
begin: generate_block_name
开始：生成块名称
generate_item  生成项
generate_item  生成项
end  结束

22 Verilog HDL Quick Reference Guide
22 Verilog HDL 快速参考指南

A generate for loop permits one or more generate items to be instantiated multiple times. The index loop variable must be a genvar.
生成 for 循环允许一个或多个生成项被多次实例化。索引循环变量必须是 genvar 类型。
A generate if-else or case permits generate items to be conditionally instantiated based on an expression that is deterministic at the time the design is elaborated.
生成 if-else 或 case 结构允许根据设计展开时可确定的表达式条件化实例化生成项。
generate_block_name (optional) is used to create a unique instance name for each generated item.
generate_block_name（可选）用于为每个生成的项创建唯一的实例名称。
Task and function definitions are permitted within the generate scope, but not in a generate for-loop. That is, only one definition of the task or function can be generated.
任务和函数定义允许在生成作用域内，但不允许在生成 for 循环中。也就是说，只能生成任务或函数的一个定义。

10.0 Procedural Blocks 10.0 过程块

type_of_block @(sensitivity_list)
    statement_group :group_name
        local_variable_declarations
        time_control procedural statements
    end_of_statement_group

type_of_block is either initial or always
type_of_block 可以是 initial 或 always 类型
initial blocks process statements one time.
initial 块会一次性处理语句。
always blocks are an infinite loop which process statements repeatedly.
always 块是一个无限循环，会重复处理语句。
sensitivity list (optional) is an event time control that controls when all statements in the procedural block will be evaluated (refer to section 10.2)
敏感列表（可选）是一种事件时间控制，用于控制程序块中所有语句何时被评估（参见第 10.2 节）。
statement_group - end_of_statement_group controls the execution order of two or more procedural statements. A statement group is not required if there is only one procedural statement.
语句组 - 语句组结束符控制两个或更多程序语句的执行顺序。如果只有一个程序语句，则不需要语句组。
begin-end groups two or more statements together sequentially, so that statements are evaluated in the order they are listed. Each time control in the group is relative to previous time controls.
begin-end 将两个或多个语句按顺序组合在一起，使得语句按照列出的顺序依次执行。组内每次时间控制都是相对于前一个时间控制的。
fork-join groups two or more statements together in parallel, so that all statements are evaluated concurrently. Each time control in the group is absolute to the time the group started.
fork-join 将两个或多个语句并行组合在一起，使得所有语句同时执行。组内每次时间控制都是相对于该组启动时的绝对时间。
group_name (optional) creates a local hierarchy scope. Named groups may have local variables, and may be aborted with a disable statement.
group_name（可选）创建一个局部层次作用域。命名的组可以包含局部变量，并且可以通过 disable 语句中止。
local_variable_declarations (optional) must be a variable data type (may only be declared in named statement groups).
local_variable_declarations（可选）必须是变量数据类型（只能在命名的语句组中声明）。
time_control is used to control when the next statement in a procedural block is executed (refer to section 10.1).
time_control 用于控制程序块中下一条语句的执行时机（参见第 10.1 节）。
procedural_statement is either an assignment statement or a programming statement (refer to sections 10.3 and 10.4).
procedural_statement 可以是赋值语句或编程语句（参见第 10.3 和 10.4 节）。

Procedural Block Examples
程序块示例

Notes 注释

初始块开始：test_loop 整型变量 i；for 循环（i=0; i<=15; i=i+1;

# 5

test_in = i;结束

initial

begin: test_loop

integer i;

for (i=0; i<=15; i=i+1;

# 5

test_in = i;

end

初始过程一次性执行语句；命名块允许声明局部变量。

initial procedure executes

statements one time; the named

group allows a local variable to be

declared.

初始并行块 bus = 16'h0000;

# 10 b u s = 16^{'} h C 5 A 5;

# 20 b u s = 16^{'} h F F A A;

结束并行块

initial

fork

bus = 16'h0000;

# 10 b u s = 16^{'} h C 5 A 5;

# 20 b u s = 16^{'} h F F A A;

join

初始过程一次性执行语句；fork-join 并行块将语句并行执行（每条语句前的延迟为绝对时间）。

initial procedure executes

statements one time; the fork-

join group places statements in

parallel (the delays before each

statement are in absolute times).

每当 a、b 或 ci 变化时执行 begin sum = a + b + ci; end

always @(a or b or ci) begin

sum = a + b + ci;

end

always 过程根据敏感列表控制重复执行语句。

always procedure executes

statements repeatedly, controlled

by the sensitivity list.

在时钟上升沿触发时执行 q

=

data;

always @(posedge clk)

=

data;

当只有一条语句时，语句组不是必需的。

a statement group is not required

when there is only one statement.

10.1 Procedural Time Controls
10.1 过程时间控制

#delay

Delays execution of the next statement for a specific amount of time. The delay may be a literal number, a variable, or an expression.
延迟执行下一条语句指定的时间量。延迟可以是字面数字、变量或表达式。
@ (edge signal or edge signal or … )
@(信号边沿或信号边沿或 … )
@(edge signal, edge signal, … )
@(信号边沿, 信号边沿, … )
@(*)
Delays execution of the next statement until there is a transition on a signal.
延迟执行下一条语句，直到信号发生跳变。

edge (optional) maybe either posedge or negedge. If no edge is specified, then any logic transition is used.
边沿（可选）可以是上升沿（posedge）或下降沿（negedge）。如果未指定边沿，则使用任何逻辑跳变。
Either a comma or the keyword or may be used to specify events on any of several signals. The use of commas was added in Verilog-2001.
可以使用逗号或关键字“or”来指定多个信号中的任一事件。逗号用法是在 Verilog-2001 中新增的。
signal may be a net type or variable type, and may be any vector size.
信号可以是线网类型或变量类型，且可以是任意位宽的向量。
An asterisk in place of the list of signals indicates sensitivity to any edge of all signals that are read in the statement or statement group that follows. @* was added in Verilog-2001.
用星号代替信号列表表示对后续语句或语句组中读取的所有信号的任何边沿变化敏感。@*语法是在 Verilog-2001 中引入的。
Parenthesis are not required when there is only one signal in the list and no edge is specified.
当列表中仅有一个信号且未指定边沿时，括号不是必需的。

wait (expression) 等待（表达式）

Delays execution of the next statement until the expression evaluates as true.
延迟执行下一条语句，直到表达式求值为真。

10.2 Sensitivity Lists 10.2 敏感列表

The sensitivity list is used at the beginning of an always procedure to infer combinational logic or sequential logic behavior in simulation.
敏感列表用于 always 过程的开头，以在仿真中推断组合逻辑或时序逻辑行为。

always @(signal, signal, … ) infers combinational logic if the list of signals contains all signals read within the procedure.
always @(信号, 信号, … ) 如果信号列表包含过程中读取的所有信号，则推断为组合逻辑。
always @* infers combinational logic. Simulation and synthesis will automatically be sensitive to all signals read within the procedure. @* was added in Verilog-2001.
always @* 推断为组合逻辑。仿真和综合将自动对过程中读取的所有信号敏感。@*是在 Verilog-2001 中新增的。
always @(posedge signal, negedge signal, … ) infers sequential logic. Either the positive or negative edge can be specified for each signal in the list. A specific edge should be specified for each signal in the list.
always @(posedge 信号, negedge 信号, … ) 推断为时序逻辑。可以为列表中的每个信号指定上升沿或下降沿。应为列表中的每个信号指定特定的边沿。

NOTE: The Verilog language does not have a true “sensitivity list”. Instead, the @ time control at the beginning of a procedure delays the execution of all statements within the procedure until an edge occurs on the signals listed. Thus, if the @ control is the first thing in the procedure, the entire procedure appears to be sensitive to changes in the signals listed. The @ token is a time control, however, and not a true sensitivity list. An edge-sensitive time control is only sensitive to changes when the procedure is suspended at that control. If the procedure is suspended at another time control inside the procedure, it will not be sensitive to changes at the time control in the pseudo sensitivity list.
注意：Verilog 语言并不具备真正的“敏感列表”。实际上，过程块开头的@时间控制会延迟过程内所有语句的执行，直到所列信号出现边沿变化。因此，若@控制位于过程块起始位置，整个过程块看似对所列信号的变化敏感。但@符号本质上是时间控制，而非真正的敏感列表。边沿敏感的时间控制仅当过程挂起于该控制点时才对变化敏感。若过程挂起于内部另一时间控制点，则不会对伪敏感列表中的时间控制点变化作出响应。

10.3 Procedural Assignment Statements
10.3 过程赋值语句

variable = expression; 变量 = 表达式;

Blocking procedural assignment. Expression is evaluated and assigned when the statement is encountered. In a begin-end sequential statement group, execution of the next statement is blocked until the assignment is complete. In the sequence begin

m = n

;

n = m

; end, the first assignment changes

m

before the second assignment reads m .
阻塞式过程赋值。遇到该语句时立即对表达式求值并赋值。在 begin-end 顺序语句组中，后续语句的执行会被阻塞直至当前赋值完成。例如序列 begin

m = n

;

n = m

; end 中，首个赋值会在第二个赋值读取 m 之前改变

m

的值。
variable <= expression; 变量 <= 表达式;
Non-blocking procedural assignment. Expression is evaluated when the statement is encountered, and assignment is postponed until the end of the simulation time-step. In a begin-end sequential statement group, execution of the next statement is not blocked; and will be evaluated before the assignment is complete. In the sequence begin

m <= n

;

n <= m

; end, both assignments will be evaluated before m or n changes.
非阻塞过程赋值。表达式在遇到该语句时被评估，而赋值被推迟到仿真时间步的末尾。在 begin-end 顺序语句组中，下一条语句的执行不会被阻塞；并且将在赋值完成之前被评估。在序列 begin

m <= n

;

n <= m

; end 中，两个赋值都将在 m 或 n 改变之前被评估。

MODELING TIP: To avoid potential simulation race conditions in zero-delay models:
建模提示：为避免零延迟模型中的潜在仿真竞争条件：

Use blocking assignments ( = ) to model combinational logic.
使用阻塞赋值（=）来建模组合逻辑。
Use non-blocking assignments ( <= ) to model sequential logic.
使用非阻塞赋值（<=）来建模时序逻辑。
timing_control variable = expression;
时序控制变量 = 表达式;
timing_control variable <= expression;
时序控制变量 <= 表达式;
Delayed procedural assignments. Evaluation of the expression on the righthand side is delayed by the timing control.
延迟过程赋值。右侧表达式的评估被时序控制所延迟。
variable $=$ timing_control expression;
变量 $=$ 时序控制表达式;
Blocking intra-assignment delay. Expression is evaluated in the time-step in which the statement is encountered, and assigned in the time-step specified by the timing control. In a begin-end sequence, execution of the next statement in the sequence is blocked until the assignment is completed (which is when the delay time has elapsed).
阻塞式内部赋值延迟。表达式在遇到该语句的时间步中被评估，并在由时序控制指定的时间步中进行赋值。在 begin-end 序列中，序列中下一条语句的执行会被阻塞，直到赋值完成（即延迟时间已过去）。
variable <= timing_control expression;
变量 <= 时序控制表达式;
Non-blocking intra-assignment delay. Expression is evaluated in the time-step in which the statement is encountered, and assigned at the end of the timestep specified by the timing control. In a begin-end sequence, execution of the next statement(s) in the sequence are not blocked, and can execute before the delay has elapsed. Models transport delay.
非阻塞式内部赋值延迟。表达式在遇到该语句的时间步中被评估，并在时序控制指定的时间步结束时进行赋值。在 begin-end 序列中，序列中下一条（或多条）语句的执行不会被阻塞，可以在延迟未完成前执行。用于建模传输延迟。
assign variable $=$ expression;
assign 变量 $=$ 表达式;
Procedural continuous assignment. Overrides any other procedural assignments to a variable.
过程性连续赋值。覆盖对变量的任何其他过程性赋值。
deassign variable; 取消变量赋值（deassign variable）;
De-activates a procedural continuous assignment.
停用过程性连续赋值。
force net_or_variable = expression;
强制网络或变量赋值（force net_or_variable = expression）;
Forces any data type to a value, overriding all other logic.
强制将任何数据类型转换为特定值，覆盖所有其他逻辑。
release net_or_variable;
释放网络或变量；
Removes the effect of a force.
取消强制操作的效果。

26

10.4 Procedural Programming Statements
10.4 过程编程语句

if ( expression ) statement or statement_group
如果（表达式）语句或语句组
Executes the next statement or statement group if the expression evaluates as true.
如果表达式结果为真，则执行下一条语句或语句组。
if ( expression ) statement or statement_group
如果（表达式）语句或语句组

else statement or statement_group
否则语句或语句组

Executes the first statement or statement group if the expression evaluates as true. Executes the second statement or statement group if the expression evaluates as false or unknown.
若表达式求值为真，则执行第一个语句或语句组；若表达式求值为假或未知，则执行第二个语句或语句组。
case ( expression) case (表达式)
case_item: statement or statement_group
case 项: 语句或语句组
case_item, case_item: statement or statement_group
case 项, case 项: 语句或语句组
default: statement or statement_group
默认：语句或语句组

endcase 结束 case 语句

Compares the value of the expression to each case item and executes the statement or statement group associated with the first matching case. Executes the default if none of the cases match (the default case is optional).
将表达式的值与每个 case 项进行比较，并执行第一个匹配 case 关联的语句或语句组。若无匹配 case 则执行 default 分支（default 分支为可选项）。

casez ( expression )
casez（表达式）

Special version of the case statement which uses a Z logic value to represent don’t-care bits in either the case expression or a case item. (the

Z

can also be represented as a ? ).
case 语句的特殊版本，使用 Z 逻辑值表示 case 表达式或 case 项中的无关位（也可以用?代替

Z

）。
casex ( expression )
casex (表达式)
Special version of the case statement which uses

Z

X

logic values to represent don’t-care bits in either the case expression or a case item. (the

Z

can also be represented as a ? ).
case 语句的特殊版本，使用

Z

或

X

逻辑值表示 case 表达式或 case 项中的无关位（也可以用?代替

Z

）。
for ( initial_assignment; expression; step_assignment )
for (初始赋值; 表达式; 步进赋值)

statement or statement group
语句或语句组

Executes initial_assignment once, when the loop starts.
在循环开始时执行初始赋值一次。
Executes the statement or statement group as long as expression evaluates as true.
只要表达式评估为真，就执行该语句或语句组。
Executes step_assignment at the end of each pass through the loop.
在每次循环结束时执行步进赋值。
while ( expression ) statement or statement group
当（表达式）为真时执行语句或语句组
A loop that executes a statement or statement group as long as an expression evaluates as true. The expression is evaluated at the start of each pass of the loop.
一种循环结构，只要表达式结果为真就持续执行语句或语句组。每次循环开始时都会重新评估表达式。
repeat ( number ) statement or statement_group
重复（次数）执行语句或语句组
A loop that executes the statement or statement group a set number of times. The number may be an expression (the expression is only evaluated when the loop is first entered).
一种按设定次数执行语句或语句组的循环。次数可以是表达式（该表达式仅在首次进入循环时被评估一次）。
forever statement or statement_group
forever 语句或语句组
An infinite loop that continuously executes the statement or statement group.
一个无限循环，持续执行该语句或语句组。

disable group_name; 禁用组名；

Discontinues execution of a named group of statements. Simulation of that group jumps to the end of the group without executing any scheduled events.
终止执行一个命名的语句组。该组的仿真会直接跳转到组末尾，不执行任何已调度的事件。

11.0 Continuous Assignments
11.0 连续赋值

Explicit Continuous Assignment
显式连续赋值

net_type [size] net_name;
网络类型 [大小] 网络名称;

assign #(delay) net_name = expression;
assign #(延迟) 网络名称 = 表达式;

Implicit Continuous Assignment
隐式连续赋值

net_type (strength) [size] # (delay) net_name = expression;
网络类型（强度）[大小] #（延迟）网络名称 = 表达式;

Continuous assignments drive net types with the result of an expression. The result is automatically updated anytime a value on the right-hand side changes.
连续赋值通过表达式的结果驱动网络类型。当右侧任一值发生变化时，结果会自动更新。

Explicit continuous assignments use the assign keyword to continuously assign a value to a net.
显式连续赋值使用 assign 关键字持续为网络分配一个值。
The net can be explicitly declared in a separate statement (see section 6.1).
网络可以通过单独的语句显式声明（参见第 6.1 节）。
A net will be inferred if an undeclared name appears on the left side of the assignment, and the name is declared as a port of the module containing the continuous assignment. The net vector size will be the size of the port.
如果一个未声明的名称出现在赋值语句的左侧，并且该名称被声明为包含连续赋值的模块的端口，则将推断出一个网络。网络向量的大小将与端口的大小相同。
New in Verilog-2001: A 1-bit net will be inferred if an undeclared name appears on the left side of the assignment, and the name is not a port of the module containing the continuous assignment.
Verilog-2001 新增特性：如果一个未声明的名称出现在赋值语句的左侧，并且该名称不是包含连续赋值的模块的端口，则将推断出一个 1 位网络。
Implicit continuous assignments combine the net declaration and continuous assignment into one statement, omitting the assign keyword.
隐式连续赋值将网络声明和连续赋值合并为一个语句，省略了 assign 关键字。
net_type may be any of the net data types except trireg.
net_type 可以是除 trireg 之外的任何网络数据类型。
strength (optional) may only be specified when the continuous assignment is combined with a net declaration. The default strength is (strong1, strong0).
strength（可选）仅在连续赋值与网络声明结合时才能指定。默认强度为(strong1, strong0)。
delay (optional) follows the same syntax as primitive delays (refer to section 8.0). The default delay is zero.
delay（可选）遵循与原始延迟相同的语法（参见第 8.0 节）。默认延迟为零。
expression may include any data type, any operator, and calls to functions.
expression 可以包含任何数据类型、任何运算符以及函数调用。
Continuous assignments model combinational logic. Each time a signal changes on the right-hand side, the right-hand side is re-evaluated, and the result is assigned to the net on the left-hand side.
连续赋值用于建模组合逻辑。每当右侧信号发生变化时，右侧表达式会被重新计算，并将结果赋值给左侧的网络。
Continuous assignments are declared outside of procedural blocks. They automatically become active at time zero, and are evaluated concurrently with procedural blocks, module instances, and primitive instances.
连续赋值在过程块外部声明。它们会在时间零点自动激活，并与过程块、模块实例和原语实例并发执行。

Continuous Assignment Examples
连续赋值示例

/ /

Explicit continuous assignment

/ /

显式连续赋值

wire [31:0] mux_out; 线型 [31:0] mux_out;

assign mux_out = sel? a : b;
赋值 mux_out = sel ? a : b;

// Implicit continuous assignment; the net declaration
// 隐式连续赋值；网络声明

/ /

and the continuous assignment are combined

/ /

与连续赋值被合并

tri [0:15] #2.8 buf_out = en? in: 16 ' bz;
三态[0:15] #2.8 缓冲输出 = 使能? 输入 : 16'b 高阻;

// Implicit continuous assignment with strengths
// 带强度的隐式连续赋值

wire [63:0] (strong1, pull0) alu_out =
线型[63:0] (强 1, 弱 0) 算术逻辑单元输出 =

alu_function(opcode, a,b);
算术逻辑函数(操作码, 输入 a, 输入 b);

12.0 Operators 12.0 运算符

For most operations, the operands may be nets, variables, constants or function calls. Some operations are not legal on real (floating-point) values.
对于大多数运算，操作数可以是网络、变量、常量或函数调用。某些运算不适用于实数（浮点）值。
Operators which return a true/false result will return a 1-bit value where 1 represents true, 0 represents false, and $X$ represents indeterminate.
返回真/假结果的运算符将返回一个 1 位值，其中 1 表示真，0 表示假， $X$ 表示不确定。

Bitwise Operators 位运算符
$\sim$	~m	invert each bit of m 对 m 的每一位取反
&	m & n m 与 n	AND each bit of $m$ with each bit of $n$ 将 $m$ 的每一位与 $n$ 的每一位进行 AND 运算
\|	$m ∣ n$	OR each bit of $m$ with each bit of $n$ 将 $m$ 的每一位与 $n$ 的每一位进行或运算
$\land$	$m \land n$	exclusive-OR each bit of $m$ with $n$ 将 $m$ 的每一位与 $n$ 进行异或运算
$\sim \land$ or ^~ $\sim \land$ 或 ^~	$m \sim \land n$	exclusive-NOR each bit of m with $n$ 将 m 的每一位与 $n$ 进行同或运算
<<	m << n	shift m left n-times and fill with zeros 将 m 左移 n 次并用零填充
>>	$m ≫ n$	shift m right n-times and fill with zeros 将 m 右移 n 次并用零填充
Unary Reduction Operators 一元归约运算符
&	&m	AND all bits in m together (1-bit result) 对 m 中的所有位进行与运算（结果为 1 位）
~&	$\sim$ - $^{m}$	NAND all bits in m together (1-bit result) 对 m 中的所有位进行与非运算（结果为 1 位）
1	\|m	OR all bits in m together (1-bit result) 对 m 的所有位进行或运算（1 位结果）
$\sim$	$\sim 1 m$	NOR all bits in m together (1-bit result) 对 m 的所有位进行或非运算（1 位结果）
$\land$	$\land m$	exclusive-OR all bits in m (1-bit result) 对 m 的所有位进行异或运算（1 位结果）
$\sim \land$ or ^~ $\sim \land$ 或 ^~	$\sim \land m$	exclusive-NOR all bits in m (1-bit result) 对 m 中所有位进行同或运算（结果为 1 位）
Logical Operators 逻辑运算符
!	! m	is m not true? (1-bit True/False result) m 不为真吗？（1 位真/假结果）
&&	m & $^{n}$	are both m and n true? (1-bit True/False result) m 和 n 都为真吗？（1 位真/假结果）
\|\|	$m ‖ n$	are either m or n true? (1-bit True/False result) m 或 n 是否为真？（1 位真/假结果）

Equality and Relational Operators (return

X

if an operand has

X

Z

)
相等与关系运算符（若操作数含

X

或

X

则返回

Z

）

==	m == n	is m equal to n? (1-bit True/False result) m 是否等于 n？（1 位真/假结果）
!=	$m! = n$	is m not equal to n? (1-bit True/False result) m 不等于 n 吗？（1 位真/假结果）
<	$m < n$	is $m$ less than n ? (1-bit True/False result) $m$ 小于 n 吗？（1 位真/假结果）
>	$m > n$	is m greater than n ? (1-bit True/False result) m 大于 n 吗？（1 位真/假结果）
<= 小于等于	$m <= n$	is m less than or equal to n? (1-bit True/False result) m 是否小于或等于 n？（1 位真/假结果）
>= 大于等于	$m ≫ n$	is m greater than or equal to n ? (1-bit True/False result) m 是否大于或等于 n？（1 位真/假结果）
Identity Operators (compare logic values $0, 1, X$ , and Z ) 恒等运算符（比较逻辑值 $0, 1, X$ 和 Z）
===	$m === n$	is m identical to n? (1-bit True/False results) m 与 n 是否相同？（1 位真/假结果）
!==	m ! $=$ n	is m not identical to n? (1-bit True/False result) m 与 n 是否不相同？（1 位真/假结果）
Miscellaneous Operators 杂项运算符
?: ？：	sel?m: $n$ 选择？m: $n$	conditional operator; if sel is true, return m: else return n 条件运算符；若 sel 为真，则返回 m：否则返回 n
{}	{m, n}	concatenate m to n , creating a larger vector 将 m 到 n 连接起来，形成一个更大的向量
{ 4 $}$	{n{ }}	replicate inner concatenation n-times 将内部连接重复 n 次
->	->	trigger an event on an event data type 在事件数据类型上触发事件

Arithmetic Operators 算术运算符
+	$m + n$	add n to m 将 n 加到 m
-	m - n m 减去 n	subtract n from m 从 m 中减去 n
-	-m 负 m	negate m (2's complement) 对 m 取反（二进制补码）
*	$m$ * n	multiply m by $n$ 将 m 乘以 $n$
1	$m / n$	divide m by $n$ 将 m 除以 $n$
%	m % n m 取模 n	modulus of m/n m/n 的模数
**	m ** n m 的 n 次方	$m$ to the power $n$ (new in Verilog-2001) $m$ 的 $n$ 次方（Verilog-2001 新增）
<<<	$m ⋘ n$	shift m left n-times, filling with 0 (new in Verilog-2001) 将 m 左移 n 次，用 0 填充（Verilog-2001 新增）
>>>	m >>> n	shift $m$ right $n$ -times; fill with value of sign bit if expression is signed, otherwise fill with 0 (Verilog-2001) 右移 $m$ 位 $n$ 次；若表达式为有符号数则用符号位填充，否则用 0 填充（Verilog-2001 标准）

12.1 Operator Expansion Rules
12.1 运算符扩展规则

As a general rule, all operands in an expression are first expanded to the size of the largest vector in the statement (including both sides of an assignment statement). Concatenate and replicate operations are evaluated before the expansion, and represent a new vector size.
通用规则是，表达式中的所有操作数首先扩展至语句中最大向量的尺寸（包括赋值语句的两侧）。连接与复制操作在扩展前执行，并形成新的向量尺寸。

Unsigned operands are expanded by left-extending with zero.
无符号操作数通过在左侧补零进行扩展。
Signed operands are expanded by left-extending with the value of the mostsignificant bit (the sign bit).
有符号操作数通过左扩展最高有效位（符号位）的值进行扩展。

12.2 Arithmetic Operation Rules
12.2 算术运算规则

For most operators (there are exceptions) all operands in the expression are used to determine how the operation is performed:
对于大多数运算符（存在例外情况），表达式中的所有操作数都用于确定运算的执行方式：

If any operand is real, then floating-point arithmetic will be performed.
如果任一操作数为实数，则将执行浮点算术运算。
If any operand is unsigned, then unsigned arithmetic will be performed.
如果任一操作数为无符号数，则将执行无符号算术运算。
If all operands are signed, then signed arithmetic will be performed.
若所有操作数均为有符号数，则执行有符号算术运算。
An operand can be “cast” to signed or unsigned using the $signed and $unsigned system functions (added in Verilog-2001).
可通过 Verilog-2001 新增的系统函数$signed 和$unsigned 将操作数“强制转换”为有符号或无符号类型。

12.3 Operator Precedence
12.3 运算符优先级

Compound expressions are evaluated in the order of operator precedence. Operators within parenthesis have a higher precedence and are evaluated first.
复合表达式按照运算符优先级顺序求值。括号内的运算符具有更高优先级，会优先计算。

!	$\sim$	+	- (unary) -（一元）	highest precedence 最高优先级
{}	{ $}}$
( )
**
*	/	%
+	-		(binary) （二元）
<< 左移	>>	$⋘$	>>> 右移
<	<= 小于等于	$>$	>= 大于等于
==	! =	===	! ==
&	$\sim$ &
$\land$	$\sim \land$
\|	$\sim 1$
&&				$↓$
\| 1 1
? :				lowest precedence 最低优先级

13.0 Task Definitions 13.0 任务定义

        ANSI-C Style Task Declaration (added in Verilog-2001)
task automatic task_name (
    port_declaration port_name, port_name, ... ,
    port_declaration port_name, port_name, ... );
    local variable declarations
    procedural_statement or statement_group
endtask
Old Style Task Declaration
(port declarations determine the order signals are passed in/out of the task)
task automatic task_name,
port_declaration port_name, port_name, ...;
port_declaration port_name, port_name, ...;
local variable declarations
procedural_statement or statement_group
endtask

Tasks are analogous to subroutines in other languages.
任务类似于其他语言中的子程序。

Must be declared within a module, and are local to that module.
必须在模块内声明，且仅在该模块内局部有效。
Must be called from an initial procedure, an always procedure or another task.
必须从 initial 过程、always 过程或其他任务中调用。
May have any number of input, output or inout ports, including none.
可以包含任意数量的输入、输出或双向端口，也可以没有端口。
Tasks may contain time controls (#, @, or wait).
任务可能包含时间控制（#、@或 wait）。
automatic (optional) allocates storage space each time the task is called, allowing the task to be re-entrant (the task can be called while previous calls to the task are still executing). Automatic tasks were added in Verilog-2001.
自动（可选）在每次调用任务时分配存储空间，使任务可重入（在先前对该任务的调用仍在执行时，可以再次调用该任务）。自动任务是在 Verilog-2001 中新增的。
port_declaration can be:
端口声明可以是：
port_direction signed range
端口方向有符号范围
port_direction reg signed range
端口方向寄存器有符号范围
port_direction port_type port_direction can be input, output or inout.
端口方向端口类型端口方向可以是输入(input)、输出(output)或双向(inout)。
range (optional) is a range from [msb :/sb] (most-significant-bit to least-significant-bit). msb and Isb must be a literal number, a constant, an expression, or a call to a constant function. If no range is specified, the ports are 1-bit wide. port_type can be integer, time, real or realtime.
范围（可选）表示从[最高有效位:最低有效位]的区间。msb 和 lsb 必须是字面数字、常量、表达式或对常量函数的调用。若未指定范围，则端口默认为 1 位宽。端口类型可以是整型(integer)、时间型(time)、实数型(real)或实时型(realtime)。
signed (optional) indicates that values are interpreted as 2 's complement signed values.
有符号（可选）表示数值按 2 的补码有符号格式解析。

Example of a Task
任务示例

//TASK DEFINITION (must be declared within a module)
//任务定义（必须在模块内声明）

task read_mem (input [15:0] address,
任务 read_mem（输入 [15:0] 地址，

begin output [31:0] data );
开始输出 [31:0] 数据）；

read_request = 1; 读取请求 = 1;

wait (read_grant) addr_bus = address;
等待（读取授权）地址总线 = 地址;

data = data_bus; 数据 = 数据总线;

#5 addr_bus = 16'bz; read_request = 0;
#5 地址总线 = 16'bz; 读取请求 = 0;

end 结束

endtask 任务结束

//TASK CALL //任务调用

always @(posedge clock) 始终@(时钟上升沿)

read_mem(PC, IR); 读取内存(PC, IR);

14.0 Function Definitions
14.0 函数定义

            ANSI-C Style Function Declaration (added in Verilog-2001)
function automatic range_or_type function_name (
    input range_or_type port_name, port_name, ... ,
    input range_or_type port_name, port_name, ... );
    local variable declarations
    procedural_statement or statement_group
endfunction
Old Style Function Declaration
(port declarations determine the order signals are passed into the function)
function automatic [range_or_type] function_name;
input range_or_type port_name, port_name, ... ;
input range_or_type port_name, port_name, ... ;
local variable declarations
procedural_statement or statement_group
endfunction

Functions: 函数：

Must be declared within a module, and are local to that module.
必须在模块内声明，且仅在该模块内局部有效。
Return the value assigned to the function name.
返回赋给函数名的值。
May be called any place an expression value can be used.
可在任何允许使用表达式值的地方调用。
Must have at least one input; may not have outputs or inouts.
必须至少有一个输入；不能有输出或双向端口。
May not contain time controls or non-blocking assignments.
不得包含时间控制或非阻塞赋值。
automatic (optional) allocates storage space for each function call, allowing recursive function calls. Automatic functions were added in Verilog-2001.
automatic（可选）为每次函数调用分配存储空间，允许递归函数调用。自动函数是在 Verilog-2001 中新增的。
range_or_type (optional) is the function return type or input type. The default is a 1-bit reg. range_or_type can be:
range_or_type（可选）是函数的返回类型或输入类型。默认为 1 位 reg。range_or_type 可以是：
signed [msb:/sb] 有符号 [msb:lsb]
reg signed [msb:lsb] 有符号寄存器 [msb:lsb]
integer, time, real or realtime
整数、时间、实数或实数时间
signed (optional) indicates that the return value or input values are interpreted as 2’s complement signed values. Signed functions were added in Verilog-2001.
signed（可选）表示返回值或输入值被解释为 2 的补码有符号值。有符号函数是在 Verilog-2001 中新增的。

14.1 Constant Functions 14.1 常量函数

Constant functions (new in Verilog-2001) are functions with restrictions so that the function can be evaluated at elaboration (before simulation starts running).
常量函数（Verilog-2001 新增特性）是指具有特定限制的函数，使得该函数能在仿真开始前的编译阶段被求值。

Only locally declared variables can be referenced. Net types cannot be used.
只能引用局部声明的变量，不能使用网络类型。
Parameter values used within the function must be defined before the function is called. Parameter values should not be redefined using defparam.
函数内使用的参数值必须在调用函数前定义，且不应通过 defparam 重新定义参数值。
Can call other constant functions, but not in a context where a constant expression is required (such as to declare port sizes).
可以调用其他常量函数，但不能在需要常量表达式的上下文中调用（例如声明端口大小时）。
System function calls are illegal. System task calls are ignored.
系统函数调用是非法的，系统任务调用会被忽略。
Hierarchical references are illegal.
层次化引用是非法的。

15.0 Specify Blocks 15.0 指定块

specify
    specparam_declarations (see 6.3)
    simple_pin-to-pin_path_delay
    edge-sensitive_pin-to-pin_path_delay
    state-dependent_pin-to-pin_path_delay
    timing_constraint_checks
endspecify

15.1 Pin-to-pin Path Delays
15.1 引脚到引脚的路径延迟

Simple path delay statement:
简单的路径延迟语句：
(input_port polarity:path_token output_port ) = (delay);
(输入端口极性:路径标记输出端口) = (延迟);
Edge-sensitive path delay:
边沿敏感路径延迟：
(edge input_port path_token (output_port polarity:source)) = (delay);
(边沿输入端口路径标记 (输出端口极性:源)) = (延迟);
edge (optional) may be either posedge or negedge. If not specified, all input transitions are used.
边沿（可选）可以是上升沿（posedge）或下降沿（negedge）。如未指定，则使用所有输入跳变。
source (optional) is the input port or value the output will receive. The source is ignored by most logic simulators, but may be used by timing analyzers.
源（可选）是指输出将接收的输入端口或值。大多数逻辑模拟器会忽略此源，但时序分析工具可能会用到它。
State-dependent path delay:
状态相关路径延迟：
if (first_condition) simple_or_edge-sensitive_path_delay
如果（第一个条件）简单或边沿敏感路径延迟
if (next_condition) simple_or_edge-sensitive_path_delay
如果（下一个条件）简单或边沿敏感路径延迟
ifnone simple_path_delay
如果无简单路径延迟
Different delays for the same path can be specified.
可以为同一路径指定不同的延迟。
condition may only be based on input ports.
条件只能基于输入端口。
Most operators may be used, but should resolve to true/false ( $X$ or $Z$ is considered true; if the condition resolves to a vector, only the $I s b$ is used).
可以使用大多数运算符，但应解析为真/假（ $X$ 或 $Z$ 视为真；若条件解析为向量，则仅使用 $I s b$ ）。
Each delay for the same path must have a different condition or a different edge-sensitive edge.
同一路径的每个延迟必须具有不同的条件或不同的边沿敏感边。
The ifnone condition (optional) may only be a simple path delay, and serves as a default if no other condition evaluates as true.
ifnone 条件（可选）只能是一个简单的路径延迟，并在其他条件均不成立时作为默认值使用。
polarity (optional) is either + or - . A - indicates the input will be inverted. Polarity is ignored by most simulators, but may be used by timing analyzers.
极性（可选）为+或-，-表示输入将被反转。大多数仿真器会忽略极性，但时序分析工具可能会使用它。
path_token is either *> for full connection or $=>$ for parallel connection.
path_token 可以是*>表示全连接，或 $=>$ 表示并行连接。
Parallel connection indicates each input bit of a vector is connected to its corresponding output bit (bit 0 to bit 0 , bit 1 to bit 1, …)
并行连接表示向量的每个输入位与其对应的输出位相连（位 0 对位 0，位 1 对位 1，依此类推）
Full connection indicates an input bit may propagate to any output bit.
全连接表示输入位可以传播到任意输出位。
Separate delay sets for $1, 2, 3, 6$ or 12 transitions may be specified.
可为 $1, 2, 3, 6$ 或 12 转换指定独立的延迟设置。
Each delay set may have a single delay or a min:typ:max delay range.
每个延迟设置可以包含单一延迟或最小:典型:最大延迟范围。

Delays 延迟	Transitions represented (in order) 按顺序表示的转换
1	all output transitions 所有输出转换
2	rise, fall output transitions 上升、下降输出转换
3	rise, fall, turn-off output transitions 上升、下降、关闭输出转换
6	rise, fall, 0->Z, $Z - > 1, 1 - > Z, Z - > 0$ 上升、下降、0->高阻, $Z - > 1, 1 - > Z, Z - > 0$
12	rise, fall, 0->Z, Z->1, 1->Z, Z->0, 上升、下降、0->高阻、高阻->1、1->高阻、高阻->0 $0 - > x, x - > 1, 1 - > x, x - > 0, x - > z, z - > x$

Path Delay Examples 路径延迟示例

Notes 注释

(

a => b

)

= 1.8

;

parallel connection path; one delay for all output transitions
并行连接路径；所有输出转换共用一个延迟

(a -*> b) = 2:3:4;

full connection path; one min:typ:max delay range for all output transitions;

b

receives the inverted value of

a

完整连接路径；所有输出转换共用一个最小:典型:最大延迟范围；

b

接收

a

的反相值

\begin{aligned} specparam t1 = 3 : 4 : 6, \\ t2 = 2 : 3 : 4; \\ (a => y) = (t 1, t 2); \end{aligned}

different path delays for rise, fall transitions
上升、下降沿转换的不同路径延迟

\begin{aligned} (posedge clk => (q b - : d)) \\ = (2.6, 1.8); \end{aligned}

edge-sensitive path delay; timing path is positive edge of clock to

q b; q b

receives the inverted value of data
边沿敏感路径延迟；时序路径为时钟上升沿至

q b; q b

接收数据的反相值

若(rst && pst)成立，则(时钟上升沿=>q+:d)

= 2

；

if (rst && pst)

(posedge clk=>(q +: d))

= 2

;

state-dependent edge sensitive path delay
状态相关的边沿敏感路径延迟

\begin{aligned} if (opcode = 3^{'} b 000) \\ (a, b^{2} + 0) = 15; \\ if (opcode = 3^{'} b 001) \\ (a, b * > o) = 25; \\ ifnone (a, b * > 0) = 10; \end{aligned}

state-dependent path delays; an ALU with different delays for certain operations (default delay has no condition)
状态相关的路径延迟；针对特定操作的 ALU 具有不同延迟（默认延迟无条件）

15.2 Path Pulse (Glitch) Detection
15.2 路径脉冲（毛刺）检测

A pulse is a glitch on the inputs of a module path that is less than the delay of the path. A special specparam constant can be used to control whether the pulse will propagate to the output (transport delay), not propagate to the output (inertial delay), or result in a logic X on the output.
脉冲是指模块路径输入端的毛刺，其持续时间小于路径延迟。可通过特殊 specparam 常量控制该脉冲是否传播至输出端（传输延迟）、不传播至输出端（惯性延迟）或在输出端产生逻辑 X 值。

specparam PATHPULSE$input$output = (reject_limit, error_limit);
specparam PATHPULSE$ = (reject_limit, error_limit);

reject_limit is a delay value, or min:typ:max delay set, that is less than or equal to the delay of a module path. Any pulse on the input that is less than or equal to the reject limit will be cancelled (not propagate to the output).
reject_limit（拒绝限值）是一个延迟值或最小:典型:最大延迟集合，其值小于或等于模块路径的延迟。任何输入端的脉冲若小于或等于该拒绝限值，将被取消（不会传播至输出端）。
error_limit is a delay value, or min:typ:max delay set, that is greater than or equal to the reject_limit and less than or equal to the delay of a module path. Any pulse on the input greater than the error_limit will propagate to the output. Any pulse less than or equal to the error_limit and greater than the reject_limit will be propagated as a logic X to the output.
error_limit（错误限值）是一个延迟值或最小:典型:最大延迟集合，其值大于等于 reject_limit 且小于等于模块路径延迟。输入端脉冲若超过 error_limit 将传播至输出端；若大于 reject_limit 但小于等于 error_limit，则输出端会以逻辑 X 形式传播该脉冲。
A PATHPULSE$ specparam with no input to output path applies to all module paths that do not have a specific PATHPULSE$ specparam.
未指定输入到输出路径的 PATHPULSE$ specparam 参数将适用于所有未设置特定 PATHPULSE$ specparam 的模块路径。
A single limit can be specified, in which case the reject and error limits will be the same. The parenthesis can be omitted when there is a single value.
可指定单一限值，此时拒绝限值与错误限值相同。若仅有一个数值，括号可省略。

Verilog-2001 adds the following reserved words which can be used within a specify block for greater pulse propagation accuracy.
Verilog-2001 新增了以下保留字，可在指定块（specify block）中使用，以实现更精确的脉冲传播精度。
pulsestyle_onevent list_of_path_outputs;
pulsestyle_onevent 路径输出列表;
Indicates that a pulse propagates to a path output as an X , with the same delay as if a valid input change had propagated to the output. This is the default behavior, and matches Verilog-1995.
表示脉冲以 X 值传播至路径输出端，其延迟与有效输入变化传播至输出端时相同。此为默认行为，与 Verilog-1995 保持一致。
pulsestyle_ondetect list_of_path_outputs;
pulsestyle_ondetect 路径输出列表;
Indicates that as soon as a pulse is detected, a logic X is propagated to a path output, without the path delay.
表示一旦检测到脉冲，逻辑 X 会立即传播到路径输出端，不经过路径延迟。
(continued on next page)
（下页续）
showcancelled list_of_path_outputs;
showcancelled 路径输出列表;
Indicates that a negative pulse, where the trailing edge of the pulse occurs before the leading edge, will not propagate to the output. This is the default behavior, and matches Verilog-1995.
表示负脉冲（即脉冲后沿先于前沿出现的情况）不会传播到输出端。此为默认行为，与 Verilog-1995 标准一致。
noshowcancelled list_of_path_outputs;
不显示已取消的路径输出列表;
Indicates that negative pulses propagate to the output as a logic X.
表示负脉冲会以逻辑 X 的形式传播至输出端。

15.3 Timing Constraint Checks
15.3 时序约束检查

Timing constraint checks are special tasks that model restrictions on input changes, such as setup times and hold times.
时序约束检查是模拟输入变化限制（如建立时间和保持时间）的特殊任务。

$setup(data_event, reference_event, limit, notifier); $setup(数据事件, 参考事件, 限制值, 通知器);
$hold(reference_event, data_event, limit, notifier) ; $hold(参考事件, 数据事件, 限制值, 通知器);
$setuphold (reference_event, data_event, setup_limit, hold_limit, notifier, stamptime_condition, checktime_condition, delayed_ref, delayed_data); $setuphold(参考事件, 数据事件, 建立限制, 保持限制, 通知器, 时间戳条件, 检查时间条件, 延迟参考, 延迟数据);
$recovery (reference_event, data_event, limit, notifier); $recovery(参考事件, 数据事件, 限制值, 通知器);
$removal(reference_event, data_event, limit, notifier); $removal(参考事件, 数据事件, 限制值, 通知器);
$recrem(reference_event, data_event, recovery_limit, removal_limit, notifier, stamptime_cond, checktime_cond, delayed_ref, delayed_data); $recrem(参考事件, 数据事件, 恢复限制, 移除限制, 通知器, 时间戳条件, 检查时间条件, 延迟参考, 延迟数据);
$skew(reference_event, data_event, limit, notifier); $skew(参考事件, 数据事件, 限制值, 通知器);
$timeskew (reference_event, data_event, limit, notifier, event_based_flag, remain_active_flag); $timeskew(参考事件, 数据事件, 限制值, 通知器, 基于事件的标志, 保持活跃标志);
$fullskew(reference_event, data_event, data_skew_limit, ref_skew_limit, notifier, event_based_flag, remain_active_flag); $全偏移(参考事件, 数据事件, 数据偏移限制, 参考偏移限制, 通知器, 基于事件的标志, 保持活跃标志);
$period(reference_event, limit, notifier); $周期(参考事件, 限制, 通知器);
$width (reference_event, limit, width_threshold, notifier); $宽度(参考事件, 限制, 宽度阈值, 通知器);
	$nochange (reference_event, data_event, start_edge_offset, end_edge_offset, notifier); $无变化(参考事件, 数据事件, 起始边沿偏移, 结束边沿偏移, 通知器);

Timing checks measure the delta between a reference_event and a data_event.
时序检查测量参考事件(reference_event)与数据事件(data_event)之间的时间差。

data_event and reference_event signals must be module input ports.
数据事件(data_event)和参考事件(reference_event)信号必须是模块的输入端口。
limit is a constant expression that represents the amount of time that must be met for the constraint. The expression can be a min:typ:max delay set.
限制条件(limit)是一个常量表达式，表示约束必须满足的时间量。该表达式可以是最小:典型:最大延迟集合。
notifier (optional) is a 1-bit reg variable that is automatically toggled whenever the timing check detects a violation.
通知器(notifier，可选)是一个 1 位寄存器变量，当时序检查检测到违规时会自动翻转。
stamptime_condition (optional) and checktime_condition (optional) are conditions for enabling or disabling negative timing checks. These arguments were added in Verilog-2001.
stamptime_condition（可选）和 checktime_condition（可选）是用于启用或禁用负时序检查的条件。这些参数在 Verilog-2001 中新增。
delayed_ref (optional) and delayed_data (optional) are delayed signals for negative timing checks. These arguments were added in Verilog-2001.
delayed_ref（可选）和 delayed_data（可选）是用于负时序检查的延迟信号。这些参数在 Verilog-2001 中新增。
event_based_flag (optional) when set, causes the timing check to be event based instead of timer based. This argument was added in Verilog-2001.
event_based_flag（可选）当设置时，会使时序检查基于事件而非定时器。此参数在 Verilog-2001 中新增。
remain_active_flag (optional) wen set, causes the timing check to not become inactive after the first violation is reported. This argument was added in Verilog-2001.
remain_active_flag（可选）当设置时，时序检查在首次报告违规后不会变为非活动状态。此参数在 Verilog-2001 中新增。
start_edge_offset and end_edge_offset are delay values (either positive or negative) which expand or reduce the time in which no change can occur.
start_edge_offset 和 end_edge_offset 是延迟值（可为正或负），用于扩展或缩小不允许发生变化的时段。
$recrem, $timeskew and $fullskew were added in Verilog-2001.
$recrem、$timeskew 和$fullskew 是在 Verilog-2001 版本中新增的。

16.0 User Defined Primitives (UDPs
16.0 用户自定义原语（UDPs）

User Defined Primitives define new primitives, which are used exactly the same as built-in primitives.
用户自定义原语用于定义新的原语，其使用方式与内置原语完全相同。

                    ANSI-C Style Port List (added in Verilog-2001)
primitive primitive_name
    ( output reg=logic_value terminal_declaration,
        input terminal_declarations );
    table
        table_entry;
        table_entry;
    endtable
endprimitive
                    Old Style Port List
primitive primitive_name (output, input, input, ... );
    output terminal_declaration;
    input terminal_declarations;
    reg output_terminal;
    initial output_terminal = logic_value;
    table
        table_entry;
        table_entry;
    endtable
endprimitive

All terminals must be scalar (1-bit).
所有终端必须为标量（1 位）。
Only one output is allowed, which must be the first terminal.
只允许一个输出，且必须作为首个终端。
The maximum number of inputs is at least 9 inputs for a sequential UDP and 10 inputs for a combinational UDP.
最大输入数量至少为：时序 UDP 支持 9 个输入，组合 UDP 支持 10 个输入。
Logic levels of $0, 1, X$ and transitions between those values may be represented in the table. The logic value Z is not supported with UDPs. A Z value on a UDP input is treated as an X value.
表中可表示逻辑电平 $0, 1, X$ 及其间的状态转换。UDP 不支持 Z 值逻辑，输入端的 Z 值将被视为 X 值处理。
reg declaration (optional) defines a sequential UDP by creating internal storage. Only the output may be declared a reg.
reg 声明（可选）通过创建内部存储定义一个时序 UDP。只有输出可以被声明为 reg。
initial (optional) is used to define the initial (power-up) state for sequential UDP’s. Only the logic values 0,1 , and X may be used. The default state is X . In Verilog-2001, the initial value can be assigned in the declaration.
initial（可选）用于定义时序 UDP 的初始（上电）状态。只能使用逻辑值 0、1 和 X。默认状态为 X。在 Verilog-2001 中，初始值可以在声明时赋值。

16.1 UDP Table Entries
16.1 UDP 表条目

input_logic_values : output_logic_value ;
输入逻辑值 : 输出逻辑值 ;

Combinational logic table entry. Only logic level values may be specified ( $0, 1, X$ and don’t cares).
组合逻辑表条目。仅可指定逻辑电平值（ $0, 1, X$ 和无关项）。
input_logic_values : previous_state : output_logic_value ;
输入逻辑值 : 前一状态 : 输出逻辑值 ;
Sequential logic table entry. May only be used when the output is also declared as a reg data type. Both input logic level and input logic transition values may be specified.
时序逻辑表条目。仅当输出也被声明为 reg 数据类型时使用。可同时指定输入逻辑电平值和输入逻辑跳变值。
A white space must separate each input value in the table.
表格中每个输入值之间必须用空白字符分隔。
The input values in the table must be listed in the same order as the terminal list in the primitive statement.
表格中的输入值必须按照原始语句中终端列表的相同顺序列出。
Any combination of input values not specified in the table will result in a logic X (unknown) value on the output.
表格中未指定的任何输入值组合将导致输出逻辑 X（未知值）。
Only one signal may have an edge transition specified for each table entry.
每个表格条目中只能有一个信号可以指定边沿转换。
If an edge transition is specified for one input, the UDP becomes sensitive to transitions on all inputs. Therefore, all other inputs must have table entries to cover transitions, or when the transition occurs the UDP will output an X.
如果为一个输入指定了边沿转换，UDP 将对所有输入的转换变得敏感。因此，所有其他输入必须有表格条目来覆盖转换，否则当转换发生时 UDP 将输出 X。
Level sensitive entries have precedence over edge sensitive table entries.
电平敏感项优先于边沿敏感表项。
16.2 UDP Table Symbols
16.2 用户定义原语表符号

真值表符号

Truth Table

Symbol

Definition 定义

0

logic 0 on input or output
输入或输出端的逻辑 0

1

logic 1 on input or output
输入或输出端的逻辑 1

x

X

x

或

X

unknown on input or output
输入或输出端的未知状态

no change on output (sequential UDPs only)
输出无变化（仅适用于时序 UDP）

?

don't care if an input is 0, 1, or X
输入为 0、1 或 X 时无关紧要

b

B

b

或

B

don't care if and input is 0 or 1
输入为 0 或 1 时无关紧要

(v w)

输入从逻辑

v

到逻辑

w

的转换，例如：(01)表示从 0 到 1 的转换

input transition from logic

v

to logic

w

e.g.: (01) represents a transition from 0 to 1

r

R

r

或

R

rising input transition: same as (01)
上升沿输入转换：同(01)

f

F

f

或

F

falling input transition: same as (10)
输入下降沿：同(10)

p

P

p

或

P

positive input transition: (01), (0X) or (X1)
输入上升沿：(01)、(0X)或(X1)

n

N

n

或

N

negative input transition: (10), (1X) or (X0)
负向输入转换：(10)、(1X) 或 (X0)

Any possible input transition: same as (??)
任何可能的输入转换：同 (??)

UDP Examples UDP 示例

primitive mux (y, a, b, sel); //COMBINATIONAL UDP output y; input sel, a, b; table //Table order for inputs // a b sel : y //matches primitive statement 0 ? 0 : 0; //select a; don't care on b 1 ? 0 : 1; //select a; don't care on b ? 0 1 : 0; //select b; don't care on a ? 1 1 : 1; //select b; don't care on a endtable endprimitive

primitive dff //SEQUENTIAL UDP (output reg q = 0, input clk, rst, d ); table // d clk rst:state:q ? ? 0 : ? :0; //low true reset 0 R 1 : ? :0; //clock in a 0 :1: //clock in a 1 :-; //ignore negedge of clk :-; //ignore all edges on d :-; //ignore posedge of rst :-; //reduce pessimism :-; //reduce pessimism endtable endprimitive

17.0 Common System Tasks and Functions
17.0 常用系统任务与函数

System tasks and functions begin with a $ (dollar sign).
系统任务和函数以$（美元符号）开头。
The IEEE 1364 Verilog standard defines a number of standard system task and system functions.
IEEE 1364 Verilog 标准定义了一系列标准的系统任务和系统函数。
Software tool vendors may define additional proprietary system tasks and functions specific to their tool, such as for waveform displays.
软件工具供应商可能会针对其工具定义额外的专有系统任务和函数，例如用于波形显示。
Simulator users may define additional system tasks and functions using the Verilog Programming Language Interface (PLI).
模拟器用户可以使用 Verilog 编程语言接口（PLI）定义额外的系统任务和函数。

17.1 Text Output System Tasks
17.1 文本输出系统任务

$display(“text_with_format_specifiers”, list_of_arguments); $displayb(“text_with_format_specifiers”, list_of_arguments); $displayo( “text_with_format_specifiers”, list_of_arguments); $displayh( “text_with_format_specifiers”, list_of_arguments); Prints the formatted message when the statement is executed. A newline is automatically added to the message. If no format is specified, the routines default to decimal, binary, octal and hexadecimal formats, respectively.
$display("带格式说明符的文本", 参数列表); $displayb("带格式说明符的文本", 参数列表); $displayo("带格式说明符的文本", 参数列表); $displayh("带格式说明符的文本", 参数列表); 执行语句时打印格式化消息。消息末尾会自动添加换行符。若未指定格式，各函数默认分别采用十进制、二进制、八进制和十六进制格式。
$write(“text_with_format_specifiers”, list_of_arguments);
$write("带格式说明符的文本", 参数列表);
$writeb( “text_with_format_specifiers”, list_of_arguments) ;
$writeb("带格式说明符的文本", 参数列表);
$writeo(“text_with_format_specifiers”, list_of_arguments);
$writeo("带格式说明符的文本", 参数列表);
$writeh(“text_with_format_specifiers”, list_of_arguments); Like $display statement, except that no newline is added.
$writeh("带格式说明符的文本", 参数列表); 类似于$display 语句，但不添加换行符。
$strobe(“text_with_format_specifiers”, list_of_arguments);
$strobe("带格式说明符的文本", 参数列表);
$strobeb(“text_with_format_specifiers”, list_of_arguments);
$strobeb("带格式说明符的文本", 参数列表);
$strobeo (“text_with_format_specifiers”, list_of_arguments);
$strobeo（“带格式说明符的文本”，参数列表）;
$strobeh(“text_with_format_specifiers”, list_of_arguments);
$strobeh（“带格式说明符的文本”，参数列表）;
Like the $display statement, except that the printing of the text is delayed until all simulation events in the current simulation time have executed.
与$display 语句类似，不同之处在于文本的打印会延迟到当前仿真时间内的所有仿真事件执行完毕后才进行。
$monitor (“text_with_format_specifiers”, list_of_arguments);
$monitor（“带格式说明符的文本”，参数列表）;
$monitorb (“text_with_format_specifiers”, list_of_arguments) ;
$monitorb("带格式说明符的文本", 参数列表);
$monitoro( “text_with_format_specifiers”, list_of_arguments);
$monitoro("带格式说明符的文本", 参数列表);
$monitorh(“text_with_format_specifiers”, list_of_arguments);
$monitorh("带格式说明符的文本", 参数列表);
Invokes a background process that continuously monitors the arguments listed, and prints the formatted message whenever one of the arguments changes. A newline is automatically added to the message.
调用一个后台进程持续监控列出的参数，每当任一参数发生变化时打印格式化消息。消息末尾会自动添加换行符。

Text Formatting Codes 文本格式化代码
%b	binary values 二进制值	%m	hierarchical name of scope 作用域的分层名称
%o	octal values 八进制值	%l	configuration library binding 配置库绑定
%d	decimal values 十进制值	\t	print a tab 打印一个制表符
%h	hex values 十六进制值	\n	print a newline 打印换行符
%e	real values-exponential 实数值-指数形式	"	print a quote 打印引号
%f 浮点数格式符	real values-decimal 实数值-十进制	$⋮ ∖$	print a backslash 打印反斜杠
%t 时间格式符	formatted time values 格式化时间值	%%	print a percent sign 打印百分号
%s	character strings 字符串
%0b, %0o, %0d and %0h truncates any leading zeros in the value. %0b、%0o、%0d 和%0h 会截取值中前导的零。
%e and %f may specify field widths (e.g. %5. 2f ). %e 和%f 可以指定字段宽度（例如%5.2f）。
%m and %l do not take an argument; they have an implied argument value. %m 和%l 不接受参数；它们具有隐含的参数值。
The format letters are not case sensitive (i.e. %b and %B are equivalent). 格式字母不区分大小写（即%b 和%B 是等效的）。

17.2 File I/O System Tasks and Functions
17.2 文件输入/输出系统任务与函数

mcd = $fopen(“file_name”) ;
mcd = $fopen("文件名");
fd = $fopen(“file_name”, type);
fd = $fopen("文件名", 类型);
A function that opens a disk file for writing, and returns an integer value.
一个用于打开磁盘文件进行写入并返回整数值的函数。

mcd is a multi-channel-descriptor with a single bit set. Multiple mcd’s can be or’ed together to write to multiple files at the same time. An mod file is always opened as a new file for writing only. Bit 0 is reserved and represents the simulator’s output window. Bit 31 is reserved and represents that the channel is an fd, not an mcd.
mcd（多通道描述符）是一个仅设置单个比特位的标识符。多个 mcd 可通过“或”运算组合，实现同时向多个文件写入数据。mod 文件始终以仅写入模式作为新文件打开。比特 0 为保留位，代表模拟器的输出窗口；比特 31 同为保留位，表示该通道为文件描述符（fd）而非 mcd。
$f d$ is a single-channel descriptor which has multiple bits set; bit 31 and at least one other bit will be set. An fd file can be opened for either reading or writing, and can be opened in append mode. Only one file can be read or written to at a time using an fd . The fd was added in Verilog-2001.
$f d$ 是单通道描述符，其多个比特位被置位（比特 31 及至少一个其他比特位必被置位）。fd 文件支持读写两种模式，并可以追加模式打开。每次仅能通过一个 fd 读取或写入单个文件。该功能于 Verilog-2001 标准中新增。
type is one of the following character strings:
类型为下列字符串之一：

"r" or "rb" "r" 或 "rb"	open for reading 以读取方式打开
"w" or "wb" "w" 或 "wb"	truncate to zero length or create for writing 截断为零长度或创建以写入
"a" or "ab" "a" 或 "ab"	append; open for writing at end of file 追加；以写入模式打开文件，在文件末尾进行操作
"r+", "r+b", or "rb+" "r+"、"r+b"或"rb+"	open for update (reading and writing) 以更新模式打开（可读取和写入）
"w+", "w+b", or "wb+" "w+"、"w+b"或"wb+"	truncate or create for update 截断或创建以更新
"a+", "a+b", or "ab+" "a+"、"a+b"或"ab+"	append; open or create for update at end-of-file 追加；打开或创建以在文件末尾更新

$fclose(mcd_or_fd);

Closes a disk file that was opened by $fopen.
关闭由$fopen 打开的磁盘文件。
$fmonitor (mcd_or_fd, “text with format specifiers”, signal, signal,…) ;
$fmonitor (mcd_or_fd, "带格式说明符的文本", signal, signal,…) ;
$fdisplay (mcd_or_fd, “text with format specifiers”, signal, signal,…) ;
$fdisplay (mcd_or_fd, "带格式说明符的文本", signal, signal,…) ;
$fwrite(mcd_or_fd, “text with format specifiers”, signal, signal,…);
$fwrite(mcd_or_fd, "带格式说明符的文本", signal, signal,…);
$fstrobe (mcd_or_fd, “text with format specifiers”, signal, signal,…); Variations of the text display tasks that write to files.
$fstrobe (mcd_or_fd, "带格式说明符的文本", signal, signal,…); 写入文件的文本显示任务变体。

Verilog-2001 adds several system functions similar to C file I/O functions:
Verilog-2001 新增了若干类似 C 语言文件 I/O 功能的系统函数：

c=$fgetc(fd);
code = $ungetc(c,fd);
code = $fgets(str, fd);
code = $fscanf(fd, format, arguments);
code = $fread(reg_variable, fd);
code = $fread(memory_array, fd, start, count);
position = $ftell(fd);
code = $fseek (fd, offset, operation);
code = $rewind(fd);
errno = $ferror(fd, str);
$fflush(mcd_or_fd);

17.3 Other Common System Tasks and Functions
17.3 其他常见系统任务与函数

$finish( $n$ );

Finishes a simulation and exits the simulation process.

n

(optional) is 0,1 or 2 , and may cause extra information about the simulation to be displayed.
结束仿真并退出仿真进程。

n

（可选参数）取值为 0、1 或 2，可能用于显示关于仿真的额外信息。

$stop( $n$ );

Halts a simulation and enters an interactive debug mode.
停止仿真并进入交互式调试模式。

$time
$stime
$realtime

Returns the current simulation time as a 64 -bit vector, a 32 -bit integer or a real number, respectively.
分别返回当前仿真时间作为 64 位向量、32 位整数或实数。
$timeformat (unit, precision, “suffix”, min_field_width);
$timeformat（单位，精度，“后缀”，最小字段宽度）;
Controls the format used by the %t text format specifier.
控制由%t 文本格式说明符使用的格式。

unit is the base that time is to be displayed in, where:
单位是时间显示的基础单位，其中：

$0 = 1 \sec$	-4 = 100us -4 = 100 微秒	-7 = 100ns -7 = 100 纳秒	$- 10 = 100 ps$	-13 = 100fs -13 = 100 飞秒
$- 1 = 100 ms$	$- 5 = 10 us$	$- 8 = 10 ns$	$- 11 = 10 ps$	$- 14 = 10 fs$
$- 2 = 10 ms$	$- 6 = 1 us$	$- 9 = 1 ns$	$- 12 = 1 ps$	$- 15 = 1 fs$
$- 3 = 1 ms$

precision is the number of decimal points to display.
精度表示要显示的小数位数。
suffix is a string appended to the time, such as " $n s$ ".
后缀是附加在时间后的字符串，例如“ $n s$ ”。
min_field_width is the minimum number of characters to display.
min_field_width 是显示的最小字符数。

Example: $timeformat (-9, 2, “ns”, 10);
示例：$timeformat (-9, 2, "纳秒", 10);
$printtimescale(module_hierarchical_name);
$printtimescale(模块层次化名称);
Prints the time scale of the specified module, or the scope from which it is called if no module is specified.
打印指定模块的时间尺度，若未指定模块则打印调用该函数的所在作用域的时间尺度。

signed_value = $signed(unsigned_value)
unsigned_value = $unsigned(signed_value)

Converts a value to or from a signed value; affects math operations and sign extension. These system functions were added in Verilog-2001.
将数值转换为有符号数或从有符号数转换；影响数学运算和符号扩展。这些系统函数是在 Verilog-2001 中新增的。
$swrite(reg_variable, format, arguments, format, arguments,…) ;
$swrite(寄存器变量, 格式, 参数, 格式, 参数,…) ;
$swriteb(reg_variable, format, arguments, format, arguments,…) ;
$swriteb(寄存器变量, 格式, 参数, 格式, 参数,…) ;
$swriteo(reg_variable, format, arguments, format, arguments,…);
$swriteo(寄存器变量, 格式, 参数, 格式, 参数,…);
$swrited(reg_variable, format, arguments, format, arguments,…);
$swrited(寄存器变量, 格式, 参数, 格式, 参数,…);
$sformat (reg_variable, format, arguments);
$sformat(寄存器变量, 格式, 参数);
Similar to $write, except that the string is written to the reg variable instead of to a file. These system tasks and functions were added in Verilog-2001.
类似于$write，不同之处在于字符串被写入寄存器变量而非文件。这些系统任务和函数是在 Verilog-2001 中新增的。
code

=

$sscanf(str, format, arguments) ;
代码

=

$sscanf(字符串, 格式, 参数);
Similar to $fscanf, but reads values from a string. Added in Verilog-2001.
类似于$fscanf，但从字符串中读取值。该功能在 Verilog-2001 中新增。
$readmemb (“file_name”, variable_array, start_address, end_address);
$readmemb("文件名", 变量数组, 起始地址, 结束地址);
$readmemh(“file_name”, variable_array, start_address, end_address);
$readmemh("文件名", 变量数组, 起始地址, 结束地址);
Loads the contents of a file into a memory array. The file must be an ASCII file with values represented in binary ($readmemb) or hex ($readmemh). Start and end address are optional.
将文件内容加载到内存数组中。文件必须是 ASCII 格式，其中数值以二进制（$readmemb）或十六进制（$readmemh）表示。起始地址和结束地址为可选参数。
64-bit_reg_variable = $realtobits(real_variable) ;
64 位寄存器变量 = $realtobits(实数变量);
real_variable = $bitstoreal(64-bit_reg_variable);
实数变量 = $bitstoreal(64 位寄存器变量);
Converts double-precision real variables to and from 64 bit reg vectors, so that the real value can be passed through 64-bit ports.
实现双精度实数变量与 64 位寄存器向量之间的相互转换，以便实数值可通过 64 位端口传递。
integer = $test$plusargs( “invocation_option”)
整型数 = $test$plusargs("调用选项")
integer = $value$plusargs (“invocation_option=format”, variable)
整数 = $value$plusargs（“调用选项=格式”，变量）
Tests the invocation command line for the invocation option. The option must begin with a + on the command line, but the + is not included in the string. If found, the routines return a non-zero value. $value$plusargs converts any text following the string up to a white space to the format specified, and puts the value into the second argument. Allowable formats are %b, %o, %d, %h, %e, %f, %g and %s.
测试调用命令行中的调用选项。选项必须以命令行中的+开头，但字符串中不包含+。如果找到，例程返回非零值。$value$plusargs 将字符串后跟的文本转换为指定格式，并将值放入第二个参数中。允许的格式有%b、%o、%d、%h、%e、%f、%g 和%s。

18.0 Common Compiler Directives
18.0 常用编译器指令

Compiler directives provide a method for software tool vendors to control how their tool will interpret Verilog HDL models.
编译器指令为软件工具供应商提供了一种控制其工具如何解释 Verilog HDL 模型的方法。

Compiler directives begin with the grave accent character ( ` ).
编译器指令以重音符号（`）开头。
Compiler directives are not Verilog HDL statements; there is no semi-colon at the end of compiler directives.
编译器指令并非 Verilog HDL 语句，因此指令末尾没有分号。
Compiler directives are not bound by modules or by files. When a tool encounters a compiler directive, the directive remains in effect until another compiler directive either modifies it or turns it off.
编译器指令不受模块或文件的限制。当工具遇到编译器指令时，该指令会一直有效，直到另一个编译器指令修改它或将其关闭。
-resetall
Resets all compiler directives that have a default back to their default. Directives that have no default are not affected.
将所有具有默认值的编译器指令重置为其默认状态。无默认值的指令不受影响。
`timescale time_unit base / precision base
`timescale 时间单位基数 / 精度基数
Specifies the time units and precision for delays:
指定延迟的时间单位和精度：
time_unit is the amount of time a delay of 1 represents. The time unit must be 1,10 , or 100
时间单位是延迟值 1 所代表的时间量。时间单位必须是 1、10 或 100
base is the time base for each unit, ranging from seconds to femtoseconds, and must be: $s m s$ us ns ps or fs
基数是每个单位的时间基准，范围从秒到飞秒，必须是： $s m s$ 微秒纳秒皮秒或飞秒
precision and base represent how many decimal points of precision to use relative to the time units.
精度和基数表示相对于时间单位使用多少位小数精度。
Example: timescale 1 ns / 10 ps Indicates delays are in 1 nanosecond units with 2 decimal points of precision ( 10 ps is .01 ns ). Note: There is no default timescale in Verilog; delays are simply relative numbers until a timescale directive declares the units and base the numbers represent. define macro_name text_string
示例： timescale 1 ns / 10 ps Indicates delays are in 1 nanosecond units with 2 decimal points of precision ( 10 ps is .01 ns ). Note: There is no default timescale in Verilog; delays are simply relative numbers until a timescale directive declares the units and base the numbers represent. 定义宏名称文本字符串
`define macro_name (arguments) text_string (arguments)
`定义宏名称 (参数) 文本字符串 (参数)
Text substitution macro. Allows a text string to be defined as a macro name.
文本替换宏。允许将文本字符串定义为宏名称。
text_string will be substituted in place of the macro_name where ever the macro name is used.
文本字符串将在使用宏名称的任何地方替换宏名称。
text_string is terminated by a carriage return-the string must be on one line.
text_string 以回车符终止——字符串必须位于同一行。
arguments are evaluated before text is substituted.
参数会在文本替换前被求值。
The macro_name must also be preceded by the grave accent mark ( ` ) each time the macro name is used.
每次使用宏名称时，宏名前还必须加上重音符号（`）。
Comments may be used-they are not substituted into the place of the macro name.
可以使用注释——它们不会被替换到宏名称的位置。
Examples: 示例：
define cycle 20 //clock period always \#(cycle/2) clk = ~clk;
define cycle 20 //clock period always \#( 周期/2) clk = ~clk;
`define NAND(dval) nand #(dval)
`定义 NAND(dval) 为 #(dval) 与非门
NAND(3) i1 (y, a,b); NAND(3) 实例 i1 (y, a,b);
NAND(3:4:5) i2 (o,c,d); undef macro_name NAND(3:4:5) i2 (o,c,d); 取消宏名称的定义
Removes the definition of a macro name.
移除宏名称的定义。

`ifdef macro name
`ifndef macro_name
    verilog_source_code
`else
    verilog_source_code
`elsif
    verilog_source_code
`endif

Conditional compilation. Allows Verilog source code to be optionally included, based on whether or not macro_name has been defined using the `define compiler directive or the +define+ invocation option. The 'ifndef and 'elsif directives were added in Verilog-2001.
条件编译。允许根据是否已使用`define 编译器指令或+define+调用选项定义了 macro_name，来选择性地包含 Verilog 源代码。'ifndef 和'elsif 指令是在 Verilog-2001 中新增的。
Example: 示例：

`ifdef RTL
    wire y = a & b;
`else
                    and #1 (y,a,b);
`endif

include "file_name" File inclusion. The contents of another Verilog HDL source file is inserted where the include directive appears.
包含指令出现。
celldefine 单元定义
`endcelldefine 结束单元定义

Flags the Verilog source code between the two directives as a cell. Some tools, such as a delay calculator for an ASIC, need to distinguish between a module that represents an ASIC cell and other modules in the design.
将两个指令之间的 Verilog 源代码标记为一个单元。某些工具（如 ASIC 的延迟计算器）需要区分代表 ASIC 单元的模块与设计中的其他模块。

`default_nettype net_data_type
`default_nettype none

Changes the net data type to be used for implicit net declarations. Any of the net data types may be specified. By default, the implicit net data type is wire. If none is specified, then implicit net declarations are disabled, and all nets must be explicitly declared (specifying none was added in Verilog-2001).
更改用于隐式网络声明的网络数据类型。可以指定任何网络数据类型。默认情况下，隐式网络数据类型为 wire。如果未指定，则禁用隐式网络声明，所有网络必须显式声明（在 Verilog-2001 中新增了不指定选项）。

`unconnected_drive pull1
`unconnected_drive pull0
`nounconnected_drive

Determines what logic value will be applied to unconnected module inputs. The default is

nounconnected_drive, meaning unconnected inputs and nets float at high impedance. 'uselib file=<file> dir=<directory> libext=<extension> Specifies the Verilog source library file or directory in which the compiler should search for the definitions of modules or UDPs instantiated in a design. A

uselib directive with no arguments removes any preceding library search directives. Note: This directive is not part of the IEEE 1364 Verilog standard, but is implemented in most Verilog simulators.
确定将什么逻辑值应用于未连接的模块输入。默认值为

nounconnected_drive, meaning unconnected inputs and nets float at high impedance. 'uselib file=<file> dir=<directory> libext=<extension> Specifies the Verilog source library file or directory in which the compiler should search for the definitions of modules or UDPs instantiated in a design. A

。不带参数的 uselib 指令会移除任何先前的库搜索指令。注意：此指令不属于 IEEE 1364 Verilog 标准，但在大多数 Verilog 模拟器中实现。
Example: 示例：
`uselib file=/models/rtl_lib
ALU i1 (y1,a,b,op); //RTL model
ALU i1 (y1,a,b,op); //RTL 模型

uselib dir=/models/gate_lib libext=.v ALU i2 (y2,a,b,op); //Gate model
uselib dir=/models/gate_lib libext=.v ALU i2 (y2,a,b,op); //门级模型
uselib //turn off uselib searching uselib //turn off 库搜索中

19.0 Configurations 19.0 配置项

Configurations (added in Verilog-2001) are a set of rules to specify the exact source description to be used for each module or primitive instance in a design. The configuration block is Verilog source code; it can be compiled along with the Verilog model source code.
配置（在 Verilog-2001 中新增）是一组规则，用于指定设计中每个模块或原语实例应使用的确切源描述。配置块是 Verilog 源代码的一部分，可以与 Verilog 模型源代码一起编译。

Verilog designs are modeled the same as in Verilog-1995.
Verilog 设计与 Verilog-1995 中的建模方式相同。
Configuration blocks are specified outside of module boundaries. The blocks can be in the same files as the Verilog source code, or they can be in separate files.
配置块在模块边界之外指定。这些块可以与 Verilog 源代码位于同一文件中，也可以位于单独的文件中。
A cell is the name of a module, primitive or another configuration.
单元（cell）是指模块、原语或其他配置的名称。
Symbolic library names are used within the configuration block. A symbolic library is a logical collection of cells. The cell name must be the same as the name of the module, primitive or configuration.
在配置块中使用符号化库名称。符号化库是单元的逻辑集合，单元名称必须与模块、原语或配置的名称相同。
library map files are used to map the symbolic library names to physical file locations.
库映射文件用于将符号化库名称映射到物理文件位置。
The library binding information for module instances can be displayed during simulation using the format specifier %l, which will print the library_name.cell_name of the module containing the print statement.
模块实例的库绑定信息可在仿真期间通过格式说明符%l 显示，该说明符会打印包含打印语句的模块的 library_name.cell_name。

19.1 Configuration Blocks
19.1 配置块

config config_name;
    design lib_name.cell_name;
    default liblist list_of_library_names;
    cell lib_name.cell_name liblist list_of_library_names;
    cell lib_name.cell_name use lib_name.cell_name:config_name;
    instance hierarchy_name liblist list_of_library_names;
    instance hierarchy_name use lib_name.cell_name:config_name;
endconfig

The config-endconfig is a design element, similar to a module, and exists in the same Verilog name space as module and primitive names. The configuration block contains a set of rules for searching for the Verilog source description to bind to a particular instance of the design.
config-endconfig 是一种设计元素，类似于模块，与模块和原语名称存在于相同的 Verilog 命名空间中。配置块包含一组规则，用于搜索 Verilog 源描述以绑定到设计的特定实例。

design specifies the library and cell of the top-level module or modules in the design hierarchy. There can only be one design statement, but multiple top-level modules can be listed. The design statement must the first statement in the configuration.
design 指定设计层次结构中顶层模块或模块的库和单元。只能有一个 design 语句，但可以列出多个顶层模块。design 语句必须是配置中的第一条语句。
lib_name. (optional) specifies which symbolic library contains the cell. If the library name is omitted, then the library which contains the config is used to search for the cell.
lib_name（可选）指定包含该单元的符号库。如果省略库名，则使用包含配置的库来搜索该单元。
cell_name (required) is the name of the module that is the top of the design hierarchy represented by the configuration.
cell_name（必需）是表示配置所代表的设计层次结构顶部的模块名称。
default liblist specifies in which libraries to search for all instances which do not match a more specific selection clause. The libraries are searched in the order listed. For many designs, the default liblist may be all that is needed to specify the configuration.
默认库列表指定了为所有不匹配更具体选择子句的实例搜索哪些库的顺序。对于许多设计而言，默认库列表可能已足够满足配置需求。
list_of_library_names is a comma-separated list of symbolic library names.
库名称列表是一个以逗号分隔的符号化库名集合。
cell specifies a specific set of libraries in which to search for the source code for that module or primitive name, instead of the libraries and order specified in the default statement.
单元（cell）指定了一组特定的库，用于搜索该模块或原语名称的源代码，而非使用默认语句中指定的库及其顺序。
lib_name. (optional) specifies which symbolic library contains the cell.
库名称（可选）指定包含该单元的符号化库。
cell_name (required) is the name of a module or primitive.
cell_name（必填）是模块或原语的名称。
instance specifies a specific set of libraries in which to search for the source code for that specific module or primitive instance, instead of the libraries and/or order specified in the default statement.
instance 指定用于搜索该特定模块或原语实例源代码的一组特定库，而非默认语句中指定的库和/或顺序。
hierarchy_name is the full hierarchy path name of an instance of a module or primitive. The hierarchy path must start with the name specified in the design statement.
hierarchy_name 是模块或原语实例的完整层次路径名称。层次路径必须从设计语句中指定的名称开始。
use (optional) specifies the location for a specific cell or instance of a cell, instead of searching a for the cell in the default libraries.
use（可选）为特定单元或单元实例指定位置，而非在默认库中搜索该单元。
lib_name. (optional) specifies which symbolic library contains the cell.
lib_name（可选）指定包含该单元的符号库。
:config_name (optional) specifies that a different configuration block should be used for the specified instance or cell. The design statement in that configuration specifies the actual binding information.
config_name（可选）指定应为特定实例或单元使用不同的配置块。该配置中的设计语句指定实际的绑定信息。

19.2 Library Map Files
19.2 库映射文件

library lib_name list_of_file_paths, -incdir list_of_file_paths; include library_map_file_path;
library lib_name 文件路径列表, -incdir 文件路径列表; include 库映射文件路径;

A separate file is used to map symbolic libraries to the physical file locations.
使用单独的文件将符号库映射到物理文件位置。

The library map file contains library statements, include statements and Verilog-style comments.
库映射文件包含库声明、包含语句以及 Verilog 风格的注释。
The map file is not Verilog source code.
映射文件并非 Verilog 源代码。
If the source files are moved, only the map file needs to be modified; The Verilog source code and configuration blocks do not need to be changed.
若源文件被移动，只需修改映射文件；Verilog 源代码和配置块无需更改。
lib_name defines the symbolic library name which will be reference in configuration blocks.
lib_name 定义了将在配置块中引用的符号库名称。
list_of_file_paths is a comma-separated list of operating system paths to one or more directories or specific files.
list_of_file_paths 是一个以逗号分隔的操作系统路径列表，指向一个或多个目录或特定文件。
A path which ends in / includes all files in the specified directory (identical to a path which ends with /*).
以/结尾的路径包含指定目录中的所有文件（与以/*结尾的路径效果相同）。
A path which does not begin with / is relative to the directory in which the current library map file is located.
不以/开头的路径相对于当前库映射文件所在目录。
Special symbols can be used in the path:
路径中可使用特殊符号：

$P$	single character wild card (matches any single character) 单字符通配符（匹配任意单个字符）
$*$	multiple character wild card (matches any number of characters) 多字符通配符（匹配任意数量的字符）
$\dots$	hierarchical wild card (matches any number of hierarchical directories) 层级通配符（匹配任意数量的层级目录）
..	specifies the parent directory 指定父目录
.	specifies the directory containing the lib.map 指定包含 lib.map 文件的目录

-incdir specifies where to search for files referenced by `include directives in the Verilog source code.
-incdir 选项用于指定在 Verilog 源代码中通过`include 指令引用的文件的搜索路径。
include library_map_file_path allows one library map file to reference another library map file.
include library_map_file_path 允许一个库映射文件引用另一个库映射文件。

20.0 Synthesis Supported Constructs
20.0 综合支持的语法结构

Following is a list of Verilog HDL constructs supported by most synthesis tools. The list is based on a preliminary draft of the IEEE 1364.1 “Verilog Register Transfer Level Synthesis” standard (this standard was not complete at the time this reference guide was written). The list is not specific to any one tool-each synthesis tool supports a unique subset of the Verilog language.
以下是大多数综合工具支持的 Verilog HDL 语法结构列表。该列表基于 IEEE 1364.1《Verilog 寄存器传输级综合》标准的初步草案（编写本参考指南时该标准尚未完成）。此列表不针对任何特定工具——每种综合工具都支持 Verilog 语言的独特子集。

Verilog HDL Constructs Verilog HDL 语法结构

Notes 注释

module declarations 模块声明

fully supported 完全支持

port declarations input output inout
端口声明输入输出双向

fully supported; any vector size supported
完全支持；支持任意向量大小

net data types wire wand wor supply0 supply1
网络数据类型 wire wand wor supply0 supply1

scalars and vectors fully supported
完全支持标量与向量

variable data types reg integer
变量数据类型 reg integer

- 可以是标量、向量或变量数组 - 可能限制仅允许从一个过程对变量进行赋值 - 整数默认为 32 位

- may be scalar or vector or variable array

- may be restricted to only making assignments to a variable from just one procedure

- integers default to 32 bits

parameter constants 参数常量

limited to integers; parameter redefinition may not be supported
仅限于整数；可能不支持参数重定义

literal integer numbers 字面整数值

fully supported; all sizes and bases
完全支持；所有尺寸和基数

module instances 模块实例

fully supported; both port order and port name instantiation supported
完全支持；既支持端口顺序实例化也支持端口名称实例化

原语实例及与非、或非、异或、缓冲器、非门、带使能的高电平有效缓冲器、带使能的低电平有效缓冲器、带使能的高电平有效非门、带使能的低电平有效非门

primitive instances

and nand

or nor

xor buf not bufif1 bufif0 notif1 notif0

fully supported 完全支持

assign continuous assignment
连续赋值（assign）

fully supported; both explicit and implicit forms are supported
完全支持；显式和隐式形式均受支持

assign procedural continuous assignment
过程连续赋值（procedural continuous assignment）

fully supported, but the deassign keyword may not be supported
完全支持，但可能不支持 deassign 关键字

function definitions 函数定义

may only use supported constructs
只能使用支持的构造

task definitions 任务定义

may only use supported constructs
只能使用支持的构造

always procedural block always 过程块

must have a sensitivity list
必须包含敏感列表

begin-end statement groups
begin-end 语句组

fully supported; both named and unnamed blocks are supported; fork-join statement groups are not supported
完全支持；支持命名和非命名块；不支持 fork-join 语句组

= 阻塞过程赋值 <= 非阻塞过程赋值

= blocking procedural assignment

<= non-blocking procedural assignment

fully supported; may be restricted to using only one type of assignment for all assignments to the same variable
完全支持；可能限制为仅对同一变量的所有赋值使用一种赋值类型

Verilog HDL Constructs Verilog HDL 结构

Notes 注释

if if-else case casex casez decision statements
if if-else case casex casez 决策语句

logic X and Z only supported as "don't care" bits
逻辑 X 和 Z 仅支持作为“无关”位

for loops for 循环

the step assignment must be an increment or decrement (+ -)
步进赋值必须是递增或递减（+ -）

while loops forever loops
while 循环无限循环

loop must take one clock cycle for each loop cycle (i.e.: an @ (posedge clk) or @(negedge clk) must be within the loop)
循环每次迭代必须占用一个时钟周期（即循环内需包含@(posedge clk)或@(negedge clk)）

禁用语句组

disable

statement group

must be used within the same named block that is being disabled
必须用于正在被禁用的同名块内部

operators 运算符

操作数可以是：- 标量或向量 - 常量或变量 - 不支持

===

和

! ==

运算符

operands may be:

- scalar or vector

- constant or variable

- the

===

and

! ==

operators are not supported

vector bit selects vector part selects
向量位选择向量部分选择

fully supported on the right-hand side of an assignment; restricted to constant bit or part selects on the left-hand side of an assignment
在赋值语句右侧完全支持；在赋值语句左侧仅限于常量位或部分选择

New constructs in the Verilog-2001 standard that are expected to be supported by synthesis:
Verilog-2001 标准中预期综合工具将支持的新结构：

Comma-separated sensitivity lists
逗号分隔的敏感列表
@* combinational logic sensitivity
@* 组合逻辑敏感列表
Combined port/data type declaration
合并端口/数据类型声明
ANSI C style port declarations
ANSI C 风格端口声明
Implicit nets with continuous assignments
连续赋值中的隐式网络
Multi-dimensional arrays
多维数组
Array bit and part selects
数组位选与部分选择
Signed data types 有符号数据类型
Signed literal numbers 有符号字面量数值
<<<, >>> arithmetic shifts
<<<, >>> 算术移位运算符
** power operator (may have restrictions)
** 幂运算符（可能存在限制）
Recursive functions (the number of recursions must be able to be determined at elaboration time)
递归函数（递归次数必须在设计阶段能够确定）
Sized parameters 带尺寸的参数
Explicit in-line parameter passing
显式内联参数传递
‘ifndef and ‘elsif compiler directives
‘ifndef 和 ‘elsif 编译器指令

INDEX 48 索引 48
Symbols 符号	\| .............................................. 28
! ............................................. 28	\|\| ............................................. 28
!= ............................................ 28	28
!== .......................................... 28	~& .......................................... 28
# ........................................16, 23	~^ ........................................... 28
$ (system tasks/functions) ............ 37 $（系统任务/函数） ............ 37	~\| ............................................ 28
$ (timing checks) ....................... 34 $（时序检查）....................... 34	' (compiler directives) ................ 40 '（编译器指令）................ 40
% (modulus operator) ................. 29 %（取模运算符）................. 29	A
% (text format codes) .................. 37 %（文本格式代码）.................. 37	always 22
& ........................................... 28
&& ......................................... 28	arrays of instances 4, 16, 19 实例数组 4, 16, 19
(* ............................................. 3	arrays of nets ..........................11, 15 网络数组 ..........................11, 15
. 29	arrays of variables ...........................12, 15 变量数组 ...........................12, 15
*) ................................................ 3	$assign ............................................ 24$
. 29	attributes 4 属性 4
*/ ............................................. 3	automatic 30, 31 自动 30, 31
*> ........................................... 32
+ ........................................29, 32	B
..29, 32	base .............................................. 6 基础 .............................................. 6
-> ........................................... 28 指向 ........................................... 28	begin ....................................... 22 开始 ....................................... 22
-incdir ...................................... 43 包含目录 ...................................... 43	binary radix ............................6, 37 二进制基数 ............................6, 37
/ ............................................. 29	blocking assignment .................... 24 阻塞赋值 .................... 24
/* ............................................. 3	buf .......................................... 18 缓冲器 .......................................... 18
// ............................................. 3	bufif0 ...................................... 18 低电平使能缓冲器 ...................................... 18
< ........................................... 28	bufif1 ...................................... 18
<< ........................................... 28	C
<<< ......................................... 29	case ........................................ 25
<= ......................................24, 28	casex ....................................... 25
..... 24	casez ....................................... 25
.. 28	cell .....................................41, 42 单元 .....................................41, 42
.... 28	cmos ........................................ 18 互补金属氧化物半导体 ........................................ 18
.... 32	comments ................................... 3 注释 ................................... 3
.. 28	compiler directives ..................... 40 编译器指令 ..................... 40
.. 28	concurrency ............................... 3 并发处理 ............................... 3
..... 28	config ...................................... 42 配置 ...................................... 42
...... 29	configuration blocks ................... 42 配置块 ................... 42
? ............................................... 6	constant functions ...................... 31 常量函数 ...................... 31
?: ............................................. 28	continuous assignment ................ 27 连续赋值 ................ 27
@ ............................................. 23
@* .......................................... 23	data type declarations 10 数据类型声明 10
\ (escaped identifiers) ..................... 4 \（转义标识符）..................... 4	data types 10, 12 数据类型 10, 12
$\land$ ............................................ 28	deassign 24 取消分配 24
^~ ........................................... 28	decimal radix 十进制基数 $.6, 37$
{ } ........................................... 28
{ { }} ........................................ 28	defparam ...................................................... 16 参数重定义 ...................................................... 16

INDEX 48 Symbols | .............................................. 28 ! ............................................. 28 || ............................................. 28 != ............................................ 28 28 !== .......................................... 28 ~& .......................................... 28 # ........................................16, 23 ~^ ........................................... 28 $ (system tasks/functions) ............ 37 ~| ............................................ 28 $ (timing checks) ....................... 34 ' (compiler directives) ................ 40 % (modulus operator) ................. 29 A % (text format codes) .................. 37 always qquad 22 & ........................................... 28 && ......................................... 28 arrays of instances qquad 4, 16, 19 (* ............................................. 3 arrays of nets ..........................11, 15 . 29 arrays of variables ...........................12, 15 *) ................................................ 3 " assign ............................................ "24 . 29 attributes qquad 4 */ ............................................. 3 automatic qquad 30, 31 *> ........................................... 32 + ........................................29, 32 B ..29, 32 base .............................................. 6 -> ........................................... 28 begin ....................................... 22 -incdir ...................................... 43 binary radix ............................6, 37 / ............................................. 29 blocking assignment .................... 24 /* ............................................. 3 buf .......................................... 18 // ............................................. 3 bufif0 ...................................... 18 < ........................................... 28 bufif1 ...................................... 18 << ........................................... 28 C <<< ......................................... 29 case ........................................ 25 <= ......................................24, 28 casex ....................................... 25 ..... 24 casez ....................................... 25 .. 28 cell .....................................41, 42 .... 28 cmos ........................................ 18 .... 32 comments ................................... 3 .. 28 compiler directives ..................... 40 .. 28 concurrency ............................... 3 ..... 28 config ...................................... 42 ...... 29 configuration blocks ................... 42 ? ............................................... 6 constant functions ...................... 31 ?: ............................................. 28 continuous assignment ................ 27 @ ............................................. 23 @* .......................................... 23 data type declarations qquad 10 \ (escaped identifiers) ..................... 4 data types qquad 10, 12 ^^............................................ 28 deassign qquad 24 ^~ ........................................... 28 decimal radix .6,37 { } ........................................... 28 https://cdn.mathpix.com/cropped/2025_03_30_f3dfba74bf818b9befeag-52.jpg?height=50&width=491&top_left_y=2258&top_left_x=1100 { { }} ........................................ 28 defparam ...................................................... 16

| INDEX 48 | | | :---: | :---: | | Symbols | \| .............................................. 28 | | ! ............................................. 28 | \|| ............................................. 28 | | != ............................................ 28 | 28 | | !== .......................................... 28 | ~& .......................................... 28 | | # ........................................16, 23 | ~^ ........................................... 28 | | $ (system tasks/functions) ............ 37 | ~\| ............................................ 28 | | $ (timing checks) ....................... 34 | ' (compiler directives) ................ 40 | | % (modulus operator) ................. 29 | A | | % (text format codes) .................. 37 | always $\qquad$ 22 | | & ........................................... 28 | | | && ......................................... 28 | arrays of instances $\qquad$ 4, 16, 19 | | (* ............................................. 3 | arrays of nets ..........................11, 15 | | . 29 | arrays of variables ...........................12, 15 | | *) ................................................ 3 | $\text { assign ............................................ } 24$ | | . 29 | attributes $\qquad$ 4 | | */ ............................................. 3 | automatic $\qquad$ 30, 31 | | *> ........................................... 32 | | | + ........................................29, 32 | B | | ..29, 32 | base .............................................. 6 | | -> ........................................... 28 | begin ....................................... 22 | | -incdir ...................................... 43 | binary radix ............................6, 37 | | / ............................................. 29 | blocking assignment .................... 24 | | /* ............................................. 3 | buf .......................................... 18 | | // ............................................. 3 | bufif0 ...................................... 18 | | < ........................................... 28 | bufif1 ...................................... 18 | | << ........................................... 28 | C | | <<< ......................................... 29 | case ........................................ 25 | | <= ......................................24, 28 | casex ....................................... 25 | | ..... 24 | casez ....................................... 25 | | .. 28 | cell .....................................41, 42 | | .... 28 | cmos ........................................ 18 | | .... 32 | comments ................................... 3 | | .. 28 | compiler directives ..................... 40 | | .. 28 | concurrency ............................... 3 | | ..... 28 | config ...................................... 42 | | ...... 29 | configuration blocks ................... 42 | | ? ............................................... 6 | constant functions ...................... 31 | | ?: ............................................. 28 | continuous assignment ................ 27 | | @ ............................................. 23 | | | @* .......................................... 23 | data type declarations $\qquad$ 10 | | \ (escaped identifiers) ..................... 4 | data types $\qquad$ 10, 12 | | $\wedge$............................................ 28 | deassign $\qquad$ 24 | | ^~ ........................................... 28 | decimal radix $.6,37$ | | { } ........................................... 28 | ![](https://cdn.mathpix.com/cropped/2025_03_30_f3dfba74bf818b9befeag-52.jpg?height=50&width=491&top_left_y=2258&top_left_x=1100) | | { { }} ........................................ 28 | defparam ...................................................... 16 |

delays ..................11, 18, 23, 32, 40 延迟 ..................11, 18, 23, 32, 40	J
design ...................................... 42 设计 ...................................... 42	join 2......................................... 2 连接 2......................................... 2
disable ..................................... 25 禁用 ..................................... 25	K
E	keywords, list of .......................... 2 关键词列表 .......................... 2
else .......................................... 25 否则 .......................................... 25	L
end .......................................... 22 结束 .......................................... 22	large ......................................... 5 大的 ......................................... 5
endcase .................................... 25 结束 case .................................... 25	liblist ...................................... 42 库列表 ...................................... 42
endconfig ................................ 42	library ..................................... 43
endgenerate ............................... 20	localparam .............................. 14
endprimitive ............................. 35 结束原语 ............................. 35	logic strengths ............................ 5 逻辑强度 ............................ 5
endspecify ............................... 32 结束指定块 ............................... 32	logic values ............................... 5 逻辑值 ............................... 5
endtask ...............................30, 31
escaped identifiers ........................ 4 转义标识符 ........................ 4	M
event ....................................... 14	medium 5
	memories ...................12, 15, 38, 39 存储器 ...................12, 15, 38, 39
F	module definitions ....................... 7 模块定义 ....................... 7
for ........................................... 25 for 循环 ........................................... 25	module instances ....................... 16 模块实例 ....................... 16
force ........................................ 24
forever ..................................... 25	N
fork .......................................... 22	name space ................................... 4 命名空间 ................................... 4
function .................................... 31 函数 .................................... 31	names ........................................... 4 名称 ........................................... 4
	nand ........................................ 18 与非 ........................................ 18
	negedge .............................. 23, 32 负边沿 .............................. 23, 32
generate ............................. 生成 .............................	net data types ............................ 10 网络数据类型 ............................ 10
genvar ................................14, 20 生成变量 ................................14, 20	nets ........................................ 10 网络 ........................................ 10
H	nmos ....................................... 18 nmos 晶体管....................................... 18
hexadecimal ............................... 6 十六进制....................................... 6	non-blocking assignment ............. 24 非阻塞赋值............................. 24
hexadecimal radix ...................... 37 十六进制基数............................... 37	nor ........................................... 18 或非门 ........................................... 18
hierarchical path names ................ 4 层次化路径名称 ................ 4	not ........................................... 18 非门 ........................................... 18
hierarchy ................................... 4 层次结构 ................................... 4	notif0 ...................................... 18
highz0...................................... 15	notif1 ...................................... 18
highz1....................................... 15	0
I	octal radix .............................6, 37 八进制基数 .............................6, 37
identifiers ................................... 4 标识符 ................................... 4	operator precedence .................... 29 运算符优先级 .................... 29
....25, 32	operators, list of ......................... 28 运算符列表 ......................... 28
ifnone ...................................... 32	or .................................. 18, 23, 28 或 .................................. 18, 23, 28
include ..................................... 43 包含 ..................................... 43	output ........................................ 8 输出 ........................................ 8
initial .......................................... 22 初始值 .......................................... 22
inout ........................................ 8 双向端口 ........................................ 8	parameter 14, 16 参数 14, 16
input .......................................... 8 输入端口 .......................................... 8	path delays ............................... 32 路径延迟............................... 32
instance .................................... 42 实例.................................... 42	path names .4 路径名称 .4
instance name ........................16, 18 实例名称........................16, 18
integer data type ......................... 12 整数数据类型 ......................... 12	polarity ........................................... 32 极性 ........................................... 32
integer numbers ............................. 6 整数 ............................. 6	port declarations 端口声明
intra-assignment delay ................ 24 内部赋值延迟 ................ 24	posedge ............................... 23, 32 上升沿 ............................... 23, 32

delays ..................11, 18, 23, 32, 40 J design ...................................... 42 join 2......................................... 2 disable ..................................... 25 K E keywords, list of .......................... 2 else .......................................... 25 L end .......................................... 22 large ......................................... 5 endcase .................................... 25 liblist ...................................... 42 endconfig ................................ 42 library ..................................... 43 endgenerate ............................... 20 localparam .............................. 14 endprimitive ............................. 35 logic strengths ............................ 5 endspecify ............................... 32 logic values ............................... 5 endtask ...............................30, 31 escaped identifiers ........................ 4 M event ....................................... 14 medium 5 memories ...................12, 15, 38, 39 F module definitions ....................... 7 for ........................................... 25 module instances ....................... 16 force ........................................ 24 forever ..................................... 25 N fork .......................................... 22 name space ................................... 4 function .................................... 31 names ........................................... 4 nand ........................................ 18 https://cdn.mathpix.com/cropped/2025_03_30_f3dfba74bf818b9befeag-53.jpg?height=19&width=40&top_left_y=1359&top_left_x=489 negedge .............................. 23, 32 generate ............................. net data types ............................ 10 genvar ................................14, 20 nets ........................................ 10 H nmos ....................................... 18 hexadecimal ............................... 6 non-blocking assignment ............. 24 hexadecimal radix ...................... 37 nor ........................................... 18 hierarchical path names ................ 4 not ........................................... 18 hierarchy ................................... 4 notif0 ...................................... 18 highz0...................................... 15 notif1 ...................................... 18 highz1....................................... 15 0 I octal radix .............................6, 37 identifiers ................................... 4 operator precedence .................... 29 ....25, 32 operators, list of ......................... 28 ifnone ...................................... 32 or .................................. 18, 23, 28 include ..................................... 43 output ........................................ 8 initial .......................................... 22 inout ........................................ 8 parameter qquad 14, 16 input .......................................... 8 path delays ............................... 32 instance .................................... 42 path names qquad .4 instance name ........................16, 18 integer data type ......................... 12 polarity ........................................... 32 integer numbers ............................. 6 port declarations intra-assignment delay ................ 24 posedge ............................... 23, 32

INDEX 50 索引 50
precision ................................... 40 精度 ................................... 40	timing checks ............................ 34 时序检查 ............................ 34
primitive definitions .................... 35 原语定义 .................... 35	tran .......................................... 18 传输门 .......................................... 18
primitive instances ..................... 18 原语实例 ..................... 18	tranif0 ..................................... 18
procedural blocks ....................... 22 过程块 ..................................... 22	tranif1 ..................................... 18
pull0 ......................................... 5	transport delay .......................... 24 传输延迟 .......................... 24
pull1 ......................................... 5 上拉 1 ......................................... 5	tri ........................................... 10 三态 ........................................... 10
pulldown .................................. 18 下拉 .................................. 18	tri0 ......................................... 10
pullup ...................................... 18 上拉电阻 ...................................... 18	tri1 ......................................... 10
R	triand ...................................... 10 线与逻辑 ...................................... 10
radix ......................................... 6 基数 ......................................... 6	trior ............................................. 10 三态或门 ............................................. 10
rcmos ....................................... 18 电阻电容 MOS ....................................... 18	trireg ....................................... 10 三态寄存器 ....................................... 10
re-entrant tasks .......................... 30 可重入任务 .......................... 30	U
real ......................................... 12 实数 ......................................... 12	use ........................................... 42 使用 ........................................... 42
realtime ................................... 12 实时 ................................... 12	User Defined Primitives ........18, 35 用户自定义原语 ........18, 35
recursive functions ..................... 31 递归函数 ..................... 31	V
reg ......................................... 12 寄存器 ......................................... 12	variables ................................... 12 变量 ................................... 12
release ........................................ 24 发布 ........................................ 24
repeat ....................................... 25 重复 ....................................... 25	W
rnmos ...................................... 18	wait ....................................... 23 等待 ....................................... 23
rpmos ...................................... 18	wand ...................................... 10
rtran ......................................... 18	weak0 ...................................... 5
rtranif0 .................................... 18	weak1 ...................................... 5
rtranif1 .................................... 18	while ........................................ 25
	wire ......................................... 10 线网 ......................................... 10
scientific notation 科学计数法	wor ....................................
scopes ........................................ 4 作用域 ........................................ 4	X
sensitivity list ........................... 22 敏感度列表 ........................... 22	xnor ..................................... 18, 28 同或门..................................... 18, 28
signed ...............8, 11, 12, 14, 30, 31 有符号数...............8, 11, 12, 14, 30, 31	xor ......................................18, 28 异或门......................................18, 28
signed arithmetic ........................ 29 有符号算术 ........................ 29
small ......................................... 5 小 ......................................... 5
specify blocks ........................... 32 指定块 ........................... 32
specparam ................................ 14
strength .......................5, 11, 18, 27 强度 .......................5, 11, 18, 27
strong0 ...................................... 5
strong1 ...................................... 5
supply0 .................................5, 10
supply1 .................................5, 10
synthesis ................................... 44 综合 ................................... 44
system tasks/functions ................ 37 系统任务/函数 ................ 37
T
task ......................................... 30 任务 ......................................... 30
time controls ............................. 23 时间控制 ............................. 23
time data type ............................ 12 时间数据类型 ............................ 12
time units .................................. 40 时间单位 .................................. 40

INDEX 50 precision ................................... 40 timing checks ............................ 34 primitive definitions .................... 35 tran .......................................... 18 primitive instances ..................... 18 tranif0 ..................................... 18 procedural blocks ....................... 22 tranif1 ..................................... 18 pull0 ......................................... 5 transport delay .......................... 24 pull1 ......................................... 5 tri ........................................... 10 pulldown .................................. 18 tri0 ......................................... 10 pullup ...................................... 18 tri1 ......................................... 10 R triand ...................................... 10 radix ......................................... 6 trior ............................................. 10 rcmos ....................................... 18 trireg ....................................... 10 re-entrant tasks .......................... 30 U real ......................................... 12 use ........................................... 42 realtime ................................... 12 User Defined Primitives ........18, 35 recursive functions ..................... 31 V reg ......................................... 12 variables ................................... 12 release ........................................ 24 repeat ....................................... 25 W rnmos ...................................... 18 wait ....................................... 23 rpmos ...................................... 18 wand ...................................... 10 rtran ......................................... 18 weak0 ...................................... 5 rtranif0 .................................... 18 weak1 ...................................... 5 rtranif1 .................................... 18 while ........................................ 25 wire ......................................... 10 scientific notation qquad wor .................................... scopes ........................................ 4 X sensitivity list ........................... 22 xnor ..................................... 18, 28 signed ...............8, 11, 12, 14, 30, 31 xor ......................................18, 28 signed arithmetic ........................ 29 small ......................................... 5 specify blocks ........................... 32 specparam ................................ 14 strength .......................5, 11, 18, 27 strong0 ...................................... 5 strong1 ...................................... 5 supply0 .................................5, 10 supply1 .................................5, 10 synthesis ................................... 44 system tasks/functions ................ 37 T task ......................................... 30 time controls ............................. 23 time data type ............................ 12 time units .................................. 40

| INDEX 50 | | | :---: | :---: | | precision ................................... 40 | timing checks ............................ 34 | | primitive definitions .................... 35 | tran .......................................... 18 | | primitive instances ..................... 18 | tranif0 ..................................... 18 | | procedural blocks ....................... 22 | tranif1 ..................................... 18 | | pull0 ......................................... 5 | transport delay .......................... 24 | | pull1 ......................................... 5 | tri ........................................... 10 | | pulldown .................................. 18 | tri0 ......................................... 10 | | pullup ...................................... 18 | tri1 ......................................... 10 | | R | triand ...................................... 10 | | radix ......................................... 6 | trior ............................................. 10 | | rcmos ....................................... 18 | trireg ....................................... 10 | | re-entrant tasks .......................... 30 | U | | real ......................................... 12 | use ........................................... 42 | | realtime ................................... 12 | User Defined Primitives ........18, 35 | | recursive functions ..................... 31 | V | | reg ......................................... 12 | variables ................................... 12 | | release ........................................ 24 | | | repeat ....................................... 25 | W | | rnmos ...................................... 18 | wait ....................................... 23 | | rpmos ...................................... 18 | wand ...................................... 10 | | rtran ......................................... 18 | weak0 ...................................... 5 | | rtranif0 .................................... 18 | weak1 ...................................... 5 | | rtranif1 .................................... 18 | while ........................................ 25 | | | wire ......................................... 10 | | scientific notation $\qquad$ | wor .................................... | | scopes ........................................ 4 | X | | sensitivity list ........................... 22 | xnor ..................................... 18, 28 | | signed ...............8, 11, 12, 14, 30, 31 | xor ......................................18, 28 | | signed arithmetic ........................ 29 | | | small ......................................... 5 | | | specify blocks ........................... 32 | | | specparam ................................ 14 | | | strength .......................5, 11, 18, 27 | | | strong0 ...................................... 5 | | | strong1 ...................................... 5 | | | supply0 .................................5, 10 | | | supply1 .................................5, 10 | | | synthesis ................................... 44 | | | system tasks/functions ................ 37 | | | T | | | task ......................................... 30 | | | time controls ............................. 23 | | | time data type ............................ 12 | | | time units .................................. 40 | |

Verilog $^{*}$ HDL

Quick Reference Guide 快速参考指南

based on the Verilog-2001 standard
基于 Verilog-2001 标准
(IEEE Std 1364-2001) （IEEE 标准 1364-2001）

Abstract 摘要

A complete reference on the Verilog Hardware Description Language, covering the syntax and semantics of the Verilog HDL. Many examples illustrate how to use Verilog. Includes synthesis supported constructs, common system tasks and a list of what is new in the Verilog-2001 standard. Fully indexed for easy reference.
关于 Verilog 硬件描述语言的完整参考指南，涵盖 Verilog HDL 的语法和语义。通过大量示例说明如何使用 Verilog。包括综合支持的构造、常见系统任务以及 Verilog-2001 标准中的新增内容列表。完全索引，便于查阅。

published by 出版于

SUTHERLAND $H_{D}$ 萨瑟兰 $H_{D}$

Sutherland HDL, Incorporated 22805 SW 92

^{nd}

Place
萨瑟兰 HDL 公司，地址：22805 SW 92

^{nd}

Place
Tualatin, OR 97062 图拉丁市，俄勒冈州 97062
(503) 692-0898
www.sutherland-hdI.com 网站：www.sutherland-hdI.com
Sutherland HDL, Inc. provides expert Verilog and SystemVerilog training workshops
萨瑟兰 HDL 公司提供专业的 Verilog 和 SystemVerilog 培训课程

Sutherland HDL also sells the Verilog PLI Quick Reference Guide, covering the Verilog Programming Language Interface.
萨瑟兰 HDL 还销售《Verilog PLI 快速参考指南》，涵盖 Verilog 编程语言接口相关内容

$^{†}$ indicates new reserved words that were added in the Verilog-2001 standard.
$^{†}$ 表示在 Verilog-2001 标准中新增的保留字。

Verilog ® ® ^(®){ }^{\circledR} HDL Verilog ® ® ^(®){ }^{\circledR} 硬件描述语言

Quick Reference Guide 快速参考指南

by Stuart Sutherland SUTHERLAND SUTHERLAND H D H D H_(D)H_{D} www.sutherland-hdl.com 作者：斯图尔特·萨瑟兰 SUTHERLAND SUTHERLAND H D H D H_(D)H_{D} www.sutherland-hdl.com

Copyright © 2001, Sutherland HDL, Inc., all rights reserved.版权所有 © 2001，Sutherland HDL 公司，保留所有权利。

Verilog ® HDL ® HDL ^(®)HDL{ }^{\circledR} \mathrm{HDL} Quick Reference Guide Verilog ® HDL ® HDL ^(®)HDL{ }^{\circledR} \mathrm{HDL} 快速参考指南

Verilog HDL Quick Reference GuideVerilog HDL 快速参考指南

1.0 New Features In Verilog-20011.0 Verilog-2001 的新特性

3.0 Concurrency 3.0 并发性

4.0 Lexical Conventions 4.0 词法约定

4.1 Case Sensitivity 4.1 大小写敏感性

4.2 White Space Characters4.2 空白字符

4.3 Comments 4.3 注释

4.4 Attributes 4.4 属性

4.5 Identifiers (names) 4.5 标识符（名称）

4.6 Hierarchical Path Names4.6 层次化路径命名

4.7 Hierarchy Scopes and Name Spaces4.7 层次化作用域与命名空间

4.8 Logic Values 4.8 逻辑值

4.9 Logic Strengths 4.9 逻辑强度

4.11 Literal Integer Numbers4.11 字面整型数

5.0 Module Definitions 5.0 模块定义

5.1 Module Items 5.1 模块项

5.2 Port Declarations 5.2 端口声明

10 VEriLog HDL QUick Reference GuideVerilog HDL 快速参考指南 10

6.0 Data Type Declarations6.0 数据类型声明

6.1 Net Data Types6.1 网络数据类型

6.2 Variable Data Types6.2 变量数据类型

14 VERILOG HDL QUICK REFERENCE GUIDE14 Verilog HDL 快速参考指南

6.3 Other Data Types6.3 其他数据类型

6.4 Vector Bit Selects and Part Selects6.4 向量位选择与部分选择

6.5 Array Selects 6.5 数组选择

6.6 Reading and Writing Arrays6.6 数组的读取与写入

7.0 Module Instances 7.0 模块实例

18 Verilog HDL Quick Reference Guide18 Verilog HDL 快速参考指南

8.0 Primitive Instances 8.0 基本元件实例

20 Verilog HDL Quick Reference GuideVerilog HDL 快速参考指南 20

9.0 Generate Blocks 9.0 生成块

22 Verilog HDL Quick Reference Guide22 Verilog HDL 快速参考指南

10.0 Procedural Blocks 10.0 过程块

10.1 Procedural Time Controls10.1 过程时间控制

#delay

wait (expression) 等待（表达式）

10.2 Sensitivity Lists 10.2 敏感列表

10.3 Procedural Assignment Statements10.3 过程赋值语句

variable = expression; 变量 = 表达式;

26

10.4 Procedural Programming Statements10.4 过程编程语句

else statement or statement_group否则 语句或语句组

endcase 结束 case 语句

casez ( expression )casez（表达式）

statement or statement group语句或语句组

disable group_name; 禁用组名；

11.0 Continuous Assignments11.0 连续赋值

12.0 Operators 12.0 运算符

12.1 Operator Expansion Rules12.1 运算符扩展规则

12.2 Arithmetic Operation Rules12.2 算术运算规则

12.3 Operator Precedence12.3 运算符优先级

13.0 Task Definitions 13.0 任务定义

14.0 Function Definitions14.0 函数定义

14.1 Constant Functions 14.1 常量函数

15.0 Specify Blocks 15.0 指定块

15.1 Pin-to-pin Path Delays15.1 引脚到引脚的路径延迟

15.2 Path Pulse (Glitch) Detection15.2 路径脉冲（毛刺）检测

15.3 Timing Constraint Checks15.3 时序约束检查

16.0 User Defined Primitives (UDPs16.0 用户自定义原语（UDPs）

16.1 UDP Table Entries16.1 UDP 表条目

17.0 Common System Tasks and Functions17.0 常用系统任务与函数

17.1 Text Output System Tasks17.1 文本输出系统任务

17.2 File I/O System Tasks and Functions17.2 文件输入/输出系统任务与函数

$fclose(mcd_or_fd);

17.3 Other Common System Tasks and Functions17.3 其他常见系统任务与函数

$finish( n n nn );

$stop( n n nn );

$time $stime $realtime

18.0 Common Compiler Directives18.0 常用编译器指令

19.0 Configurations 19.0 配置项

19.1 Configuration Blocks19.1 配置块

19.2 Library Map Files19.2 库映射文件

library lib_name list_of_file_paths, -incdir list_of_file_paths; include library_map_file_path;library lib_name 文件路径列表, -incdir 文件路径列表; include 库映射文件路径;

20.0 Synthesis Supported Constructs20.0 综合支持的语法结构

Verilog ∗ ∗ ^(**){ }^{*} HDL

Verilog $^{®}$ HDL Verilog $^{®}$ 硬件描述语言

by
Stuart Sutherland

SUTHERLAND

SUTHERLAND $H_{D}$
www.sutherland-hdl.com
作者：斯图尔特·萨瑟兰 SUTHERLAND SUTHERLAND $H_{D}$ www.sutherland-hdl.com

Copyright © 2001, Sutherland HDL, Inc., all rights reserved.
版权所有 © 2001，Sutherland HDL 公司，保留所有权利。

Verilog $^{®} HDL$ Quick Reference Guide
Verilog $^{®} HDL$ 快速参考指南

Verilog HDL Quick Reference Guide
Verilog HDL 快速参考指南

1.0 New Features In Verilog-2001
1.0 Verilog-2001 的新特性

4.2 White Space Characters
4.2 空白字符

4.6 Hierarchical Path Names
4.6 层次化路径命名

4.7 Hierarchy Scopes and Name Spaces
4.7 层次化作用域与命名空间

4.11 Literal Integer Numbers
4.11 字面整型数

10 VEriLog HDL QUick Reference Guide
Verilog HDL 快速参考指南 10

6.0 Data Type Declarations
6.0 数据类型声明

6.1 Net Data Types
6.1 网络数据类型

6.2 Variable Data Types
6.2 变量数据类型

14 VERILOG HDL QUICK REFERENCE GUIDE
14 Verilog HDL 快速参考指南

6.3 Other Data Types
6.3 其他数据类型

6.4 Vector Bit Selects and Part Selects
6.4 向量位选择与部分选择

6.6 Reading and Writing Arrays
6.6 数组的读取与写入

18 Verilog HDL Quick Reference Guide
18 Verilog HDL 快速参考指南

20 Verilog HDL Quick Reference Guide
Verilog HDL 快速参考指南 20

22 Verilog HDL Quick Reference Guide
22 Verilog HDL 快速参考指南

10.1 Procedural Time Controls
10.1 过程时间控制

10.3 Procedural Assignment Statements
10.3 过程赋值语句

10.4 Procedural Programming Statements
10.4 过程编程语句

else statement or statement_group
否则语句或语句组

casez ( expression )
casez（表达式）

statement or statement group
语句或语句组

11.0 Continuous Assignments
11.0 连续赋值

12.1 Operator Expansion Rules
12.1 运算符扩展规则

12.2 Arithmetic Operation Rules
12.2 算术运算规则

12.3 Operator Precedence
12.3 运算符优先级

14.0 Function Definitions
14.0 函数定义

15.1 Pin-to-pin Path Delays
15.1 引脚到引脚的路径延迟

15.2 Path Pulse (Glitch) Detection
15.2 路径脉冲（毛刺）检测

15.3 Timing Constraint Checks
15.3 时序约束检查

16.0 User Defined Primitives (UDPs
16.0 用户自定义原语（UDPs）

16.1 UDP Table Entries
16.1 UDP 表条目

17.0 Common System Tasks and Functions
17.0 常用系统任务与函数

17.1 Text Output System Tasks
17.1 文本输出系统任务

17.2 File I/O System Tasks and Functions
17.2 文件输入/输出系统任务与函数

17.3 Other Common System Tasks and Functions
17.3 其他常见系统任务与函数

$finish( $n$ );

$stop( $n$ );

$time
$stime
$realtime

18.0 Common Compiler Directives
18.0 常用编译器指令

19.1 Configuration Blocks
19.1 配置块

19.2 Library Map Files
19.2 库映射文件

library lib_name list_of_file_paths, -incdir list_of_file_paths; include library_map_file_path;
library lib_name 文件路径列表, -incdir 文件路径列表; include 库映射文件路径;

20.0 Synthesis Supported Constructs
20.0 综合支持的语法结构

Verilog $^{*}$ HDL

SUTHERLAND $H_{D}$ 萨瑟兰 $H_{D}$