After I published my $1 MCU write-up, several readers suggested I look at application processors — the MMU-endowed chips necessary to run real operating systems like Linux.
在我发布了我的 1 美元微控制器书写之后，几位读者建议我关注应用处理器——那些必要的 MMU 加持芯片，以运行像 Linux 这样的真实操作系统。💻
Massive shifts over the last few years have seen internet-connected devices become more featureful (and hopefully, more secure), and I’m finding myself putting Linux into more and more places.
过去几年中，大规模的变化使得互联网连接的设备变得功能更加丰富（并且希望更加安全），我发现自己将 Linux 应用于越来越多的地方。📱

Among beginner engineers, application processors supplicate reverence: one minor PCB bug and your $10,000 prototype becomes a paperweight.
在初学工程师中，应用处理器备受敬畏：一个小小的 PCB 故障，你的$10,000 原型就会变成一个废纸镇 😟。
There’s an occult consortium of engineering pros who drop these chips into designs with utter confidence, while the uninitiated cower for their Raspberry Pis and overpriced industrial SOMs.
有一个神秘的工程师联盟，他们自信地将这些芯片融入设计中，而外行人却为他们的树莓派和价格过高的工业 SOM 感到畏惧。🛠️

This article is targeted at embedded engineers who are familiar with microcontrollers but not with microprocessors or Linux, so I wanted to put together something with a quick primer on why you’d want to run embedded Linux, a broad overview of what’s involved in designing around application processors, and then a dive into some specific parts you should check out — and others you should avoid — for entry-level embedded Linux systems.
这篇文章是针对那些熟悉微控制器但对微处理器或 Linux 不太了解的嵌入式工程师，因此我想整理一些内容，以快速介绍为什么你会想要运行嵌入式 Linux，概述一下设计应用处理器时需要涉及的内容，然后深入探讨一些你应该关注的特定部分——以及一些你应该避免的部分——以便于入门级嵌入式 Linux 系统。🌟

Just like my microcontroller article, the parts I picked range from the well-worn horses that have pulled along products for the better part of this decade, to fresh-faced ICs with intriguing capabilities that you can keep up your sleeve.
就像我的微控制器文章一样，我挑选的部件涵盖了从这一整个十年中一直在推动产品发展的老将，到那些具有令人着迷能力的新面孔集成电路，可以随着你的需要灵活运用。🔧

If my mantra for the microcontroller article was that you should pick the right part for the job and not be afraid to learn new software ecosystems, my argument for this post is even simpler: once you’re booted into Linux on basically any of these parts, they become identical development environments.
如果我在微控制器文章中的座右铭是你应该选择合适的零件来完成工作，并且不要害怕学习新的软件生态系统，那么我对这篇帖子论点就更简单了：一旦你在这些零件上的 Linux 系统启动，你会发现它们变成了相同的开发环境。💻

That makes chips running embedded Linux almost a commodity product: as long as your processor checks off the right boxes, your application code won’t know if it’s running on an ST or a Microchip part — even if one of those is a brand-new dual-core Cortex-A7 and the other is an old ARM9.
这使得运行嵌入式 Linux 的芯片几乎成为一种商品产品：只要你的处理器符合正确的标准，您的应用代码就不会知道它是运行在 ST 还是 Microchip 的产品上——即使其中一个是全新的双核 Cortex-A7，而另一个是旧的 ARM9。💻
Your I2C drivers, your GPIO calls — even your V4L-based image processing code — will all work seamlessly.
您的 I2C 驱动程序、GPIO 调用——甚至基于 V4L 的图像处理代码——都将无缝工作。 😊

At least, that’s the sales pitch. Getting a part booted is an entirely different ordeal altogether — that’s what we’ll be focused on. Except for some minor benchmarking at the end, once we get to a shell prompt, we’ll consider the job completed.
至少，这就是销售宣传。启动一个部件完全是另一回事——这就是我们将要关注的内容。除了最后的几项小基准测试，一旦我们进入命令行提示符，我们将认为任务已经完成。💻

As a departure from my microcontroller review, this time I’m focusing heavily on hardware design: unlike the microcontrollers I reviewed, these chips vary considerably in PCB design difficulty — a discussion I would be in error to omit.
此次我将重点关注硬件设计，作为我微控制器评测的一个转变：与我评测的微控制器不同，这些芯片在 PCB 设计的难度上差异较大——这是我在讨论中不应遗漏的内容。🔧
To this end, I designed a dev board from scratch for each application processor reviewed. Well, actually, many dev boards for each processor: roughly 25 different designs in total. This allowed me to try out different DDR layout and power management strategies — as well as fix some bugs along the way.
为此，我为每个审查过

I intentionally designed these boards from scratch rather than starting with someone else’s CAD files. This helped me discover little “gotchas” that each CPU has, as well as optimize the design for cost and hand-assembly.
我故意从零开始设计这些电路板，而不是使用其他人的 CAD 文件。💻 这帮助我发现了每个 CPU 的小“陷阱”，并优化了成本和手工组装设计。💡
Each of these boards was designed across one or two days’ worth of time and used JLC’s low-cost 4-layer PCB manufacturing service.
每块电路板的设计耗时一到两天，并使用了 JLC 的低成本 4 层 PCB 制造服务。🛠️

These boards won’t win any awards for power consumption or EMC: to keep things easy, I often cheated by combining power rails together that would typically be powered (and sequenced!) separately.
这些电路板在功耗或电磁兼容性方面不会获得任何奖项：为了让事情更简单，我经常通过将通常需要单独供电（并且需要按顺序供电！）的电源轨合并在一起来作弊。⚡️
Also, I limited the on-board peripherals to the bare minimum required to boot, so there are no audio CODECs, little I2C sensors, or Ethernet PHYs on these boards.
此外，我将板载外围设备限制到引导所需的最低限度，因此这些板上没有音频编码解码器、很少的 I2C 传感器或以太网物理层接口。📉

As a result, the boards I built for this review are akin to the notes from your high school history class or a recording you made of yourself practicing a piece of music to study later.
因此，我为这次评测制作的电路板就像你高中历史课的笔记，或者你为以后复习而录的自己练习音乐的录音。📚
So while I’ll post pictures of the boards and screenshots of layouts to illustrate specific points, these aren’t intended to serve as reference designs or anything; the whole point of the review is to get you to a spot where you’ll want to go off and design your own little Linux boards. Teach a person to fish, you know?
所以虽然我会发布一些电路板的图片和布局的截图以说明特定的观点，但这些并不打算作为参考设计或其他什么；这次评测的整个目的就是让你达到一个你想自己设计小型 Linux 电路板的地方。教人钓鱼，你懂的？🐟

Microcontroller vs Microprocessor: Differences
微控制器与微处理器：区别 🔍

Coming from microcontrollers, the first thing you’ll notice is that Linux doesn’t usually run on Cortex-M, 8051, AVR, or other popular microcontroller architectures. Instead, we use application processors — popular ones are the Arm Cortex-A, ARM926EJ-S, and several MIPS iterations.
来自于微控制器，你会首先注意到 Linux 通常不运行在 Cortex-M、8051、AVR 或其他流行的微控制器架构上。🔍相反，我们使用应用处理器——流行的有 Arm Cortex-A、ARM926EJ-S 和几个 MIPS 变种。📱

The biggest difference between these application processors and a microcontroller is quite simple: microprocessors have a memory management unit (MMU), and microcontrollers don’t. Yes, you can run Linux without an MMU, but you usually shouldn’t: Cortex-M7 parts that can barely hit 500 MHz routinely go for double or quadruple the price of faster Cortex-A7s. They’re power-hungry: microcontrollers are built on larger processes than application processors to reduce their leakage current.
这些应用处理器和微控制器之间最大的区别非常简单：微处理器拥有内存管理单元（MMU），而微控制器没有。💡 是的，你可以在没有 MMU 的情况下运行 Linux，但通常不应该：那些几乎只能达到 500 MHz 的 Cortex-M7 部件，价格往往是更快的 Cortex-A7 的两倍或四倍。💰 它们耗电较大：微控制器的制造工艺比应用处理器更大，以减少漏电流。⚡️
And without an MMU and generally-low clock speeds, they’re downright slow.
没有内存管理单元（MMU）和通常较低的时钟速度，它们的速度确实很慢。🐢

Other than the MMU, the lines between MCUs and MPUs are getting blurred. Modern application processors often feature a similar peripheral complement as microcontrollers, and high-end Cortex-M7 microcontrollers often have similar clock speeds as entry-level application processors.
除了内存管理单元（MMU）之外，微控制器（MCU）和微处理器（MPU）之间的界限越来越模糊。现代应用处理器通常具有与微控制器相似的外设配置，而高端 Cortex-M7 微控制器的时钟速度通常与入门级应用处理器相似。🔗

Why would you want to Linux?
为什么你想使用 Linux 呢？🐧

When your microcontroller project outgrows its super loop and the random ISRs you’ve sprinkled throughout your code with care, there are many bare-metal tasking kernels to turn to — FreeRTOS, ThreadX (now Azure RTOS), RT-Thread, μC/OS, etc. By an academic definition, these are operating systems. However, compared to Linux, it’s more useful to think of these as a framework you use to write your bare-metal application inside.
当你的微控制器项目超出了超级循环以及你在代码中精心植入的随机中断服务例程的范围时，有许多裸机任务内核可供选择——FreeRTOS、ThreadX（现在称为 Azure RTOS）、RT-Thread、μC/OS 等。从学术的定义来看，这些都是操作系统。然而，与 Linux 相比，将这些视为一个框架，用于在其中编写你的裸机应用程序，会更有用。🛠️
They provide the core components of an operating system: threads (and obviously a scheduler), semaphores, message-passing, and events. Some of these also have networking, filesystems, and other libraries.
它们提供了操作系统的核心组件：线程（显然还有一个调度程序）、信号量、消息传递和事件。某些组件还包括网络功能、文件系统和其他库。🖥️

Comparing bare-metal RTOSs to Linux simply comes down to the fundamental difference between these and Linux: memory management and protection.
将裸机实时操作系统（RTOS）与 Linux 进行比较，归根结底是这两者与 Linux 之间的根本区别：内存管理和保护。🛡️
This one technical difference makes Linux running on an application processor behave quite differently from your microcontroller running an RTOS.((Before the RTOS snobs attack with pitchforks, yes, there are large-scale, well-tested RTOSes that are usually run on application processors with memory management units.
这个技术差异使得运行在应用处理器上的 Linux 与运行在实时操作系统（RTOS）上的微控制器表现得截然不同。🔧（在 RTOS 爱好者来攻击之前，是的，确实有大规模且经过充分测试的 RTOS，通常运行在带有内存管理单元的应用处理器上。）📊
Look at RTEMS as an example. They don’t have some of the limitations discussed below, and have many advantages over Linux for safety-critical real-time applications.))
将 RTEMS 作为一个例子。它们没有下面讨论的一些限制，并且在安全关键型实时应用中比 Linux 有许多优势。🚀

Dynamic memory allocation
动态内存分配🛠️

Small microcontroller applications can usually get by with static allocations for everything, but as your application grows, you’ll find yourself calling malloc() more and more, and that’s when weird bugs will start creeping up in your application.
小型微控制器应用通常可以用静态分配来解决所有问题，但随着应用程序的增长，你会发现自己越来越多地调用 malloc()，这时奇怪的错误将开始在你的应用中出现。🛠️
With complex, long-running systems, you’ll notice things working 95% of the time — only to crash at random (and usually inopportune) times.
在复杂且长期运行的系统中，你会发现其工作正常的概率为 95%——但却会在随机（通常不合时宜）的时刻崩溃。💻
These bugs evade the most javertian developers, and in my experience, they almost always stem from memory allocation issues: usually either memory leaks (that can be fixed with appropriate free() calls), or more serious problems like memory fragmentation (when the allocator runs out of appropriately-sized free blocks).
这些错误使得最严格的开发者都无法发现，根据我的经验，它们几乎总是源于内存分配问题：通常要么是内存泄漏（可以通过适当的 free() 调用来修复），要么是更严重的问题，如内存碎片（当分配器耗尽了合适大小的空闲块时）。🛠️

Because Linux-capable application processors have a memory management unit, *alloc() calls execute swiftly and reliably. Physical memory is only reserved (faulted in) when you actually access a memory location. Memory fragmentation is much less an issue since Linux frees and reorganizes pages behind the scenes. Plus, switching to Linux provides easier-to-use diagnostic tools (like valgrind) to catch bugs in your application code in the first place. And finally, because applications run in virtual memory, if your app does have memory bugs in it, Linux will kill it — leaving the rest of your system running. ((As a last-ditch kludge, it’s not uncommon to call your app in a superloop shell script to automatically restart it if it crashes without having to restart the entire system.))
因为支持 Linux 的应用处理器具有内存管理单元，因此*alloc()调用执行得迅速而可靠。💻 物理内存仅在您实际访问某个内存位置时才会被保留（发生故障）。🛠️ 由于 Linux 在后台释放和重组页面，内存碎片化问题大大减少。📉 而且，切换到 Linux 提供了更易于使用的诊断工具（如 valgrind），从而能更早地发现应用代码中的 BUG。🐞最后，由于应用程序在虚拟内存中运行，如果您的应用程序确实存在内存 BUG，Linux 将会终止它——使您的系统其他部分继续运行。⚙️（作为一个最后的应急措施，通常会在超级循环 shell 脚本中调用您的应用程序，以便在崩溃时自动重启，而不需要重启整个系统。）🔄

Networking & Interoperability
网络与互操作性 🌐

Running something like lwIP under FreeRTOS on a bare-metal microcontroller is acceptable for a lot of simple applications, but application-level network services like HTTP can burden you to implement in a reliable fashion.
在裸机微控制器上，使用 FreeRTOS 运行像 lwIP 这样的东西对许多简单应用来说是可以接受的，但应用层网络服务如 HTTP 可能会使您在实现可靠性时感到压力。🌐
Stuff that seems simple to a desktop programmer — like a WebSockets server that can accept multiple simultaneous connections — can be tricky to implement in bare-metal network stacks.
对桌面程序员来说似乎很简单的事情，比如一个可以接受多个同时连接的 WebSockets 服务器，在裸机网络堆栈中实现起来可能会很棘手。💻
Because C doesn’t have good programming constructs for asynchronous calls or exceptions, code tends to contain either a lot of weird state machines or tons of nested branches. It’s horrible to debug problems that occur.
由于 C 语言对异步调用或异常处理没有良好的编程结构，代码往往包含大量奇怪的状态机或成吨的嵌套分支。调试出现的问题非常困难。😩
In Linux, you get a first-class network stack, plus tons of rock-solid userspace libraries that sit on top of that stack and provide application-level network connectivity.
在 Linux 中，您可以获得一流的网络栈，以及许多可靠的用户空间库，这些库位于该网络栈之上，提供应用级的网络连接。🌐
Plus, you can use a variety of high-level programming languages that are easier to handle the asynchronous nature of networking.
另外，您可以使用多种高层次的编程语言，这些语言更容易处理网络的异步特性。💻

Somewhat related is the rest of the standards-based communication / interface frameworks built into the kernel. I2S, parallel camera interfaces, RGB LCDs, SDIO, and basically all those other scary high-bandwidth interfaces seem to come together much faster when you’re in Linux.
与内核中内置的其他基于标准的通信/接口框架有些相关。🔗 I2S、并行摄像头接口、RGB LCD、SDIO 以及基本上所有其他那些令人畏惧的高带宽接口，当你在 Linux 中时似乎能更快地整合在一起。🚀
But the big one is USB host capabilities. On Linux, USB devices just work. If your touchscreen drivers are glitching out and you have a client demo to show off in a half-hour, just plug in a USB mouse until you can fix it (I’ve been there before). Product requirements change and now you need audio?
但最重要的是 USB 主机功能。在 Linux 系统中，USB 设备可以轻松使用。如果你的触摸屏驱动出现故障，而你还有半小时的客户演示要展示，只需插入一个 USB 鼠标，直到你能解决这个问题（我经历过这样的情况）。产品需求会改变，现在你需要音频功能了吗？🖥️
Grab a $20 USB dongle until you can respin the board with a proper audio codec. On many boards without Ethernet, I just use a USB-to-Ethernet adapter to allow remote file transfer and GDB debugging.
抓一个 20 美元的 USB 加密狗，直到你能够重新设计电路板，使用合适的音频编码器。🌐 在许多没有以太网的电路板上，我只是使用 USB 转以太网适配器来进行远程文件传输和 GDB 调试。🔌
Don’t forget that, at the end of the day, an embedded Linux system is shockingly similar to your computer.
别忘了，归根结底，嵌入式 Linux 系统与你的电脑惊人地相似。💻

Security 安全 🔒

When thinking about embedded device security, there are usually two things we’re talking about: device security (making sure the device can only boot from verified firmware), and network security (authentication, intrusion prevention, data integrity checks, etc).
在考虑嵌入式设备安全时，我们通常谈论两个方面：设备安全（确保设备只能从经过验证的固件启动）🔐，以及网络安全（身份验证、入侵防御、数据完整性检查等）🌐。

Device security is all about chain of trust: we need a bootloader to read in an encrypted image, decrypt and verify it, before finally executing it. The bootloader and keys need to be in ROM so that they cannot be modified.
设备安全完全依赖于信任链：我们需要一个引导加载程序来读取加密的映像，解密并验证它，然后最终执行它。引导加载程序和密钥需要存储在只读存储器中，以防止它们被修改。🔐
Because the image is encrypted, nefarious third-parties won’t be able to install the firmware on cloned hardware. And since the ROM authenticates the image before executing, people won’t be able to run custom firmware on the hardware.
因为图像是加密的，恶意的第三方将无法在克隆硬件上安装固件。🔒 而且由于 ROM 在执行之前会验证图像，人们无法在硬件上运行自定义固件。🚫

Network security is about limiting software vulnerabilities and creating a trusted execution environment (TEE) where cryptographic operations can safely take place. The classic example is using client certificates to authenticate our client device to a server.
网络安全是限制软件漏洞并创建一个可信执行环境（TEE），在这个环境中，可以安全地进行加密操作。🔐 经典的例子是使用客户端证书来验证我们的客户端设备与服务器的身份。🔒
If we perform the cryptographic hashing operation in a secure environment, even an attacker who has gained total control over our normal execution environment would be unable to read our private key.
如果我们在安全环境中执行加密哈希操作，即使攻击者完全控制了我们的正常执行环境，也无法读取我们的私钥。🔒

In the world of microcontrollers, unless you’re using one of the newer Cortex-M23/M33 cores, your chip probably has a mishmash of security features that include hardware cryptographic support, (notoriously insecure) flash read-out protection, execute-only memory, write protection, TRNG, and maybe a memory protection unit.
在微控制器的世界中，除非你使用的是较新的 Cortex-M23/M33 核心，否则你的芯片可能混合了多种安全特性，包括硬件加密支持、（臭名昭著的不安全）闪存读取保护、只读内存、写保护、真随机数生成器（TRNG），以及可能的内存保护单元。🔒
While vendors might have an app note or simple example, it’s usually up to you to get all of these features enabled and working properly, and it’s challenging to establish a good chain of trust, and nearly impossible to perform cryptographic operations in a context that’s not accessible by the rest of the system.
尽管供应商可能提供应用说明或简单的示例，但通常还是需要你自己来使所有这些功能启用并正常工作，而建立良好的信任链是很具挑战性的，在不让系统其他部分访问的上下文中几乎不可能进行加密操作。🛠️

Secure boot isn’t available on every application processor reviewed here, it’s much more common.
安全启动并不是所有这里评测的应用处理器都有，但它更为常见。🔐
While there are still vulnerabilities that get disclosed from time to time, my non-expert opinion is that the implementations seem much more robust than on Cortex-M parts: boot configuration data and keys are stored in one-time-programmable memory that is not accessible from non-privileged code.
虽然仍然不时有漏洞被披露，但我作为非专家的看法是，实施似乎比 Cortex-M 部件更为稳健：启动配置数据和密钥存储在一次性可编程内存中，无法从非特权代码访问。🔒
Network security is also more mature and easier to implement using Linux network stack and cryptography support, and OP-TEE provides a ready-to-roll secure environment for many parts reviewed here.
网络安全也更加成熟，并且在使用 Linux 网络栈和加密支持方面更易于实施，OP-TEE 为这里审查的许多部分提供了一个现成的安全环境。🔒

Filesystems & Databases 文件系统与数据库 📁📊

Imagine that you needed to persist some configuration data across reboot cycles. Sure, you can use structs and low-level flash programming code, but if this data needs to be appended to or changed in an arbitrary fashion, your code would start to get ridiculous.
想象一下，你需要在重启周期中保持一些配置数据。🖥️ 当然，你可以使用结构体和低级的闪存编程代码，但如果这些数据需要以任意方式追加或更改，你的代码就会变得复杂且难以维护。😅
That’s why filesystems (and databases) exist. Yes, there are embedded libraries for filesystems, but these are way clunkier and more fragile than the capabilities you can get in Linux with nothing other than ticking a box in menuconfig. And databases?
这就是文件系统（和数据库）存在的原因。📁 是的，确实有嵌入式库用于文件系统，但这些库比在 Linux 中仅需在 menuconfig 中勾选一个选项所能获得的功能要笨重得多且更脆弱。💻 那数据库呢？📊
I’m not sure I’ve ever seen an honest attempt to run one on a microcontroller, while there’s a limitless number available on Linux.
我不确定我是否见过在微控制器上运行它的诚实尝试，而在 Linux 上则有无数可用的选项。🤖

Multiple Processes 多个进程 🌀

In a bare-metal environment, you are limited to a single application image. As you build out the application, you’ll notice things get kind of clunky if your system has to do a few totally different things simultaneously.
在裸机环境中，您仅限于一个应用程序镜像。🖥️ 随着您构建应用程序，您会注意到，如果系统必须同时执行几项完全不同的任务，情况会变得有些笨重。⚙️
If you’re developing for Linux, you can break this functionality into separate processes, where you can develop, debug, and deploy separately as separate binary images.
如果您正在为 Linux 开发，可以将此功能拆分为不同的进程，您可以分开开发、调试和部署，作为独立的二进制映像。💻

The classic example is the separation between the main app and the updater. Here, the main app runs your device’s primary functionality, while a separate background service can run every day to phone home and grab the latest version of the main application binary.
经典例子是主应用和更新程序之间的分离。📱在这里，主应用运行设备的主要功能，而一个独立的后台服务可以每天运行，联系主服务器获取主应用的最新版本。🔄
These apps do not have to interact at all, and they perform completely different tasks, so it makes sense to split them up into separate processes.
这些应用程序不需要相互互动，并且它们执行的任务完全不同，因此将它们分成单独的进程是合理的。💻

Language and Library Support
语言和库支持 📚

Bare-metal MCU development is primarily done in C and C++. Yes, there are interesting projects to run Python, Javascript, C#/.NET, and other languages on bare metal, but they’re usually focused on implementing the core language only; they don’t provide a runtime that is the same as a PC. And even their language implementation is often incompatible. That means your code (and the libraries you use) have to be written specifically for these micro-implementations. As a result, just because you can run MicroPython on an ESP32 doesn’t mean you can drop Flask on it and build up a web application server. By switching to embedded Linux, you can use the same programming languages and software libraries you’d use on your PC.
裸机微控制器开发主要使用 C 和 C++进行。💻 是的，确实有一些有趣的项目可以在裸机上运行 Python、Javascript、C#/.NET 和其他语言，但它们通常仅专注于实现核心语言；它们并不提供与 PC 相同的运行时环境。🔍 即使它们的语言实现通常也不兼容。⚠️ 这意味着你编写的代码（以及你使用的库）必须专门为这些微型实现编写。✍️ 因此，仅仅因为你可以在 ESP32 上运行 MicroPython，并不意味着你可以在上面运行 Flask 并构建一个 Web 应用服务器。🌐 通过切换到嵌入式 Linux，你可以使用与在 PC 上相同的编程语言和软件库。📦

Brick-wall isolation from the hardware
硬件的砖墙隔离 🧱

Classic bare-metal systems don’t impose any sort of application separation from the hardware. You can throw a random I2C_SendReceive() function in anywhere you’d like.
经典的裸机系统并不对硬件和应用程序之间进行任何形式的分离。您可以随意在任何地方放置一个随机的 I2C_SendReceive() 函数。🎉

In Linux, there is a hard separation between userspace calls and the underlying hardware driver code.
在 Linux 中，用户空间调用与底层硬件驱动代码之间有严格的分离。🔧
One key advantage of this is how easy it is to move from one hardware platform to another; it’s not uncommon to only have to change a couple of lines of code to specify the new device names when porting your code.
这一点的一个主要优点是从一个硬件平台迁移到另一个平台是多么简单；在移植代码时，只需更改几行代码来指定新设备名称的情况并不少见。🚀

Yes, you can poke GPIO pins, perform I2C transactions, and fire off SPI messages from userspace in Linux, and there are some good reasons to use these tools during diagnosing and debugging.
是的，您可以在 Linux 中从用户空间操作 GPIO 引脚、执行 I2C 交易并发送 SPI 消息，而且在诊断和调试过程中使用这些工具有一些很好的理由。🔧
Plus, if you’re implementing a custom I2C peripheral device on a microcontroller, and there’s very little configuration to be done, it may seem silly to write a kernel driver whose only job is to expose a character device that basically passes on whatever data directly to the I2C device you’ve built.
此外，如果您在微控制器上实现一个自定义的 I2C 外设设备，而配置工作非常有限，那么编写一个内核驱动程序的唯一工作是暴露一个字符设备，这个设备基本上就是直接将任何数据传递给您构建的 I2C 设备，这似乎显得有些愚蠢。😅

But if you’re interfacing with off-the-shelf displays, accelerometers, IMUs, light sensors, pressure sensors, temperature sensors, ADCs, DACs, and basically anything else you’d toss on an I2C or SPI bus, Linux already has built-in support for this hardware that you can flip on when building your kernel and configure in your DTS file.
但是如果你是在与现成的显示器、加速度计、IMU、光传感器、压力传感器、温度传感器、ADC、DAC，以及基本上任何你会挂在 I2C 或 SPI 总线上的设备进行接口，Linux 已经内置了对这些硬件的支持，你可以在构建内核时开启并在 DTS 文件中进行配置。🛠️

Developer Availability and Cost
开发者的可用性和成本 💼

When you combine all these challenges together, you can see that building out bare-metal C code is challenging (and thus expensive).
当你将所有这些挑战结合在一起时，你会发现构建裸机 C 代码是具有挑战性的（因此成本高昂）。💻
If you want to be able to staff your shop with lesser-experienced developers who come from web-programming code schools or otherwise have only basic computer science backgrounds, you’ll need an architecture that’s easier to develop on.
如果您想能将您的商店配备经验较少的开发人员，这些开发人员可能来自网页编程的编码学校或仅具备基本计算机科学背景，您将需要一个更易于开发的架构。🛠️

This is especially true when the majority of the project is hardware-agnostic application code, and only a minor part of the project is low-level hardware interfacing.
这尤其适用于大部分项目是与硬件无关的应用代码，而只有一小部分是低层次的硬件接口。⚙️

Why shouldn’t you Linux? 你为什么不应该使用 Linux 呢？🤔

There are lots of good reasons not to build your embedded system around Linux:
有很多好的理由不把你的嵌入式系统建立在 Linux 之上：🤔

Sleep-mode power consumption. First, the good news: active mode power consumption of application processors is quite good when compared to microcontrollers. These parts tend to be built on smaller process nodes, so you get more megahertz for your ampere than the larger processes used for Cortex-M devices.
睡眠模式下的功耗。首先，好消息是：与微控制器相比，应用处理器在工作模式下的功耗相当不错。 🔋 这些部件往往采用更小的工艺节点制造，因此在使用的每安培中，你可以获得比 Cortex-M 设备所用的较大工艺更多的兆赫兹。 ⚡️
Unfortunately, embedded Linux devices have a battery life that’s measured in hours or days, not months or years.
不幸的是，嵌入式 Linux 设备的电池寿命以小时或天来计算，而不是以月或年来计算。🔋

Modern low-power microcontrollers have a sleep-mode current consumption in the order of 1 μA — and that figure includes SRAM retention and usually even a low-power RTC oscillator running.
现代低功耗微控制器的睡眠模式电流消耗大约在 1 μA 左右——这个数字包括了 SRAM 保持，并且通常还包括一个低功耗的 RTC 振荡器运行。💡
Low-duty-cycle applications (like a sensor that logs a data point every hour) can run off a watch battery for a decade.
低占空比应用（比如每小时记录一个数据点的传感器）可以用手表电池持续运行十年。⌚

Application processors, however, can use 300 times as much power while asleep (that leaky 40 nm process has to catch up with us eventually!), but even that pales in comparison to the SDRAM, which can eat through 10 mA (yes mA, not μA) or more in self-refresh mode. Sure, you can suspend-to-flash (hibernate), but that’s only an option if you don’t need responsive wake-up.
应用处理器在休眠时的功耗可以高达 300 倍（那种漏电的 40 纳米工艺总有一天会追上我们！）⚡，但即便如此，与 SDRAM 相比仍显得微不足道，SDRAM 在自刷新模式下的功耗可以达到 10 毫安（没错，是毫安，不是微安）或更多。💡当然，你可以选择挂起到闪存（休眠），但这仅在你不需要快速唤醒的情况下才是一个选项。🌙

Even companies like Apple can’t get around these fundamental limitations: compare the 18-hour battery life of the Apple Watch (which uses an application processor) to the 10-day life of the Pebble (which uses an STM32 microcontroller with a battery half the size of the Apple Watch).
即使是像苹果这样的公司也无法克服这些基本限制：比较一下苹果手表的 18 小时电池续航（使用应用处理器）与 Pebble 的 10 天续航（使用尺寸只有苹果手表一半的 STM32 微控制器的电池）。⌚️

Boot time. Embedded Linux systems can take several seconds to boot up, which is orders of magnitude longer than a microcontroller’s start-up time.
启动时间。嵌入式 Linux 系统的启动时间可能需要几秒钟，这比微 controller 的启动时间长几个数量级。⏱️
Alright, to be fair, this is a bit of an apples-to-oranges comparison: if you were to start initializing tons of external peripherals, mount a filesystem, and initialize a large application in an RTOS on a microcontroller, it could take several seconds to boot up as well.
好吧，公平地说，这有点像苹果对橘子的比较：如果你开始初始化大量外部外设，挂载文件系统，并在微控制器上的实时操作系统中初始化一个大型应用程序，启动也可能需要几秒钟的时间。🍏🍊
While boot time is a culmination of tons of different components that can all be tweaked and tuned, the fundamental limit is caused by application processors’ inability to execute code from external flash memory; they must copy it into RAM first ((unless you’re running an XIP kernel)).
启动时间是许多不同组件调整和优化的结果，但根本限制源于应用处理器无法直接从外部闪存执行代码；它们必须先将代码复制到 RAM 中（除非你正在运行 XIP 内核）。⏱️

Responsiveness. By default, Linux’s scheduler and resource system are full of unbounded latencies that under weird and improbable scenarios may take a long time to resolve (or may actually never resolve). Have you ever seen your mouse lock up for 3 seconds randomly? There you go. If you’re building a ventilator with Linux, think carefully about that. To combat this, there’s been a PREEMPT_RT patch for some time that turns Linux into a real-time operating system with a scheduler that can basically preempt anything to make sure a hard-real-time task gets a chance to run.
响应性。默认情况下，Linux 的调度器和资源系统充满了不受限制的延迟，在奇怪且不太可能的情况下，可能需要很长时间才能解决（或者实际上可能永远无法解决）。你是否曾经看到过你的鼠标随机卡住 3 秒钟？就是这样。如果你正在用 Linux 构建一台呼吸机，请仔细考虑这一点。为了应对这一问题，已经有一段时间存在 PREEMPT_RT 补丁，将 Linux 转变为实时操作系统，其调度器基本上可以中断任何任务，以确保硬实时任务有机会运行。🕒

Also, when many people think they need a hard-real-time kernel, they really just want their code to be low-jitter.
此外，当许多人认为他们需要一个硬实时内核时，他们实际上只希望他们的代码具有低抖动。🌟
Coming from Microcontrollerland, it feels like a 1000 MHz processor should be able to bit-bang something like a 50 kHz square wave consistently, but you would be wrong.
来自微控制器的世界，感觉像是一个 1000 MHz 的处理器应该能够稳定地生成 50 kHz 的方波，但你会错的。⚙️
The Linux scheduler is going to give you something on the order of ±10 µs of jitter for interrupts, not the ±10 ns jitter you’re used to on microcontrollers.
Linux 调度程序将为中断提供大约 ±10 微秒的抖动，而不是您在微控制器上习惯的 ±10 纳秒的抖动。⌛
This can be remedied too, though: while Linux gobbles up all the normal ARM interrupt vectors, it doesn’t touch FIQ, so you can write custom FIQ handlers that execute completely outside of kernel space.
这也可以解决：虽然 Linux 会吞噬所有正常的 ARM 中断向量，但它不触及 FIQ，因此你可以编写自定义的 FIQ 处理程序，这些处理程序完全在内核空间之外执行。💻

Honestly, in practice, it’s much more common to just delegate these tasks to a separate microcontroller. Some of the parts reviewed here even include a built-in microcontroller co-processor designed for controls-oriented tasks, and it’s also pretty common to just solder down a $1 microcontroller and talk to it over SPI or I2C.
说实话，在实际应用中，将这些任务委托给一个独立的微控制器要普遍得多。🔧 这里评审的一些部件甚至包括一个内置的微控制器协处理器，旨在处理控制相关的任务，而且仅仅焊接一个 1 美元的微控制器，通过 SPI 或 I2C 与其通信也是相当常见的。💻

Design Workflow 设计工作流程🔄

The first step is to architect your system.
第一步是设计你的系统。🛠️
This is hard to do unless what you’re building is trivial or you have a lot of experience, so you’ll probably start by buying some reference hardware, trying it out to see if it can do what you’re trying to do (both in terms of hardware and software), and then using that as a jumping-off point for your own designs.
这很难做到，除非你正在构建的东西是微不足道的，或者你有丰富的经验，因此你可能会先购买一些参考硬件，尝试一下看看它是否能实现你想做的事情（无论是硬件还是软件），然后以此为基础开始你的设计。🔧

I want to note that many designers focus too heavily on the hardware peripheral selection of the reference platform when architecting their system, and don’t spend enough time thinking about software early on.
我想指出，许多设计师在构建系统时过于关注参考平台的硬件外设选择，而没有花足够的时间在早期思考软件。💻
Just because your 500 MHz Cortex-A5 supports a parallel camera sensor interface doesn’t mean you’ll be able to forward-prop images through your custom SegNet implementation at 30 fps, and many parts reviewed here with dual Ethernet MACs would struggle to run even a modest web app.
仅仅因为你的 500 MHz Cortex-A5 支持并行相机传感器接口，并不意味着你能够以 30 帧每秒的速度通过自定义的 SegNet 实现传输图像，许多这里评论的具备双以太网 MAC 的部件甚至难以运行一个适度的网页应用程序。📸

Figuring out system requirements for your software frameworks can be rather unintuitive. For example, doing a multi-touch-capable finger-painting app in Qt 5 is actually much less of a resource hog than running a simple backend server for a web app written in a modern stack using a JIT-compiled language.
为您的软件框架确定系统需求可能会相当不直观。🛠️ 例如，在 Qt 5 中开发一个支持多点触控的指绘应用实际上比运行一个简单的后端服务器（为使用 JIT 编译语言现代技术栈编写的 web 应用）消耗的资源要少得多。🌐
Many developers familiar with traditional Linux server/desktop development assume they’ll just throw a .NET Core web app on their rootfs and call it a day — only to discover that they’ve completely run out of RAM, or their app takes more than five minutes to launch, or they discover that Node.js can’t even be compiled for the ARM9 processor they’ve been designing around.
许多熟悉传统 Linux 服务器/桌面开发的开发者认为，他们只需将一个.NET Core 网页应用程序放到他们的根文件系统中就可以了——结果却发现他们的 RAM 完全用完了，或者他们的应用程序启动时间超过五分钟，或者他们发现 Node.js 甚至无法为他们一直设计的 ARM9 处理器编译。💻

The best advice I have is to simply try to run the software you’re interested in using on target hardware and try to characterize the performance as much as possible. Here are some guidelines for where to begin:
我最好的建议就是尽量在目标硬件上运行你感兴趣的软件，并尽可能地对性能进行表征。💻 下面是一些开始的指导原则：📋

• Slower ARM9 cores are for simple headless gadgets written in C/C++. Yes, you can run basic, animation-free low-resolution touch linuxfb apps with these, but blending and other advanced 2D graphics technology can really bog things down.
  较慢的 ARM9 内核适用于简单的无头设备，这些设备是用 C/C++编写的。🖥️ 是的，您可以在这些设备上运行基本的、没有动画的低分辨率触控 Linux 帧缓冲应用，但融合和其他高级 2D 图形技术确实会拖慢性能。🎨
  And yes, you can run very simple Python scripts, but in my testing, even a “Hello, World!” Flask app took 38 seconds from launch to actually spitting out a web page to my browser on a 300 MHz ARM9.
  是的，您可以运行非常简单的 Python 脚本，但在我的测试中，即使是一个“你好，世界！”的 Flask 应用程序，从启动到实际向我的浏览器输出网页也花了 38 秒，运行在一个 300 MHz 的 ARM9 上。🖥️
  Yes, obviously once the Python file was compiled, it was much faster, but you should primarily be serving up static content using lightweight HTTP servers whenever possible. And, no, you can’t even compile Node.JS or .NET Core for these architectures.
  是的，显然一旦编译了 Python 文件，它会快得多，但你应该尽可能主要使用轻量级 HTTP 服务器来提供静态内容。🚀而且，不，你甚至不能为这些架构编译 Node.JS 或 .NET Core。❌
  These also tend to boot from small-capacity SPI flash chips, which limits your framework choices.
  这些通常也倾向于从小容量的 SPI 闪存芯片启动，这限制了你的框架选择。⚙️
• Mid-range 500-1000 MHz Cortex-A-series systems can start to support interpreted / JIT-compiled languages better, but make sure you have plenty of RAM — 128 MB is really the bare minimum to consider.
  中档的 500-1000 MHz Cortex-A 系列系统可以开始更好地支持解释型/JIT 编译语言，但请确保您有足够的 RAM——128MB 实际上是值得考虑的最低限度。💻
  These have no issues running simple C/C++ touch-based GUIs running directly on a framebuffer but can stumble if you want to do lots of SVG rendering, pinch/zoom gestures, and any other canvas work.
  这些在直接运行简单的基于 C/C++的触摸 GUI 时没有问题，但如果您想进行大量 SVG 渲染、捏合/缩放手势及其他画布工作时，可能会遇到一些困难。🖥️
• Multi-core 1+ GHz Cortex-A parts with 256 MB of RAM or more will begin to support desktop/server-like deployments. With large eMMC storage (4 GB or more), decent 2D graphics acceleration (or even 3D acceleration on some parts), you can build up complex interactive touchscreen apps using native C/C++ programming, and if the app is simple enough and you have sufficient RAM, potentially using an HTML/JS/CSS-based rendering engine.
  多核 1+ GHz Cortex-A 处理器，配备 256 MB 或更多 RAM，将开始支持桌面/服务器级部署。💻 配备大容量 eMMC 存储（4 GB 或更多），良好的 2D 图形加速（甚至在某些部件上提供 3D 加速），您可以使用本地 C/C++编程构建复杂的互动触摸屏应用程序，📱 如果应用程序足够简单且 RAM 充足，可能还可以使用基于 HTML/JS/CSS 的渲染引擎。🌐
  If you’re building an Internet-enabled device, you should have no issues doing the bulk of your development in Node.js, .NET Core, or Python if you prefer that over C/C++.
  如果你正在构建一个支持互联网的设备，使用 Node.js、.NET Core 或者 Python 进行大部分开发应该没有问题，如果你更喜欢这些而不是 C/C++。💻

What about a Raspberry Pi?
树莓派怎么样？🤖

I know that there are lots of people — especially hobbyists but even professional engineers — who have gotten to this point in the article and are thinking, “I do all my embedded Linux development with Raspberry Pi boards — why do I need to read this?” Yes, Raspberry Pi single-board computers, on the surface, look similar to some of these parts: they run Linux, you can attach displays to them, do networking, and they have USB, GPIO, I2C, and SPI signals available.
我知道有很多人——尤其是爱好者，但甚至还有专业工程师——在本文写到这一点时会想：“我所有的嵌入式 Linux 开发都是用树莓派板做的——我为什么需要读这个？”是的，树莓派单板计算机从表面上看与这些部件有些相似：它们运行 Linux，可以连接显示器，进行网络连接，并且提供 USB、GPIO、I2C 和 SPI 信号。🖥️

And for what it’s worth, the BCM2711 mounted on the Pi 4 is a beast of a processor and would easily best any part in this review on that measure. Dig a bit deeper, though: this processor has video decoding and graphics acceleration, but not even a single ADC input.
值得一提的是，搭载在 Pi 4 上的 BCM2711 处理器性能强劲，轻松超越本评测中的任何组件。🐉 不过，深入探讨一下：这个处理器具备视频解码和图形加速功能，但却没有一个 ADC 输入。🔍
It has built-in HDMI transmitters that can drive dual 4k displays, but just two PWM channels.
它内置了 HDMI 发射器，可以驱动双 4k 显示器，但只有两个 PWM 通道。🎮
This is a processor that was custom-made, from the ground up, to go into smart TVs and set-top boxes — it’s not a general-purpose embedded Linux application processor, so it isn’t generally suited for embedded Linux work.
这是一个从零开始定制的处理器，专为智能电视和机顶盒设计——它不是通用的嵌入式 Linux 应用处理器，因此一般不适合嵌入式 Linux 工作。📺

It might be the perfect processor for your particular project, but it probably isn’t; forcing yourself to use a Pi early in the design process will over-constrain things.
它可能是您特定项目中完美的处理器，但它很可能并不是；在设计过程中早早强迫自己使用树莓派会导致过度限制。💻
Yes, there are always workarounds to the aforementioned shortcomings — like I2C-interfaced PWM chips, SPI-interfaced ADCs, or LCD modules with HDMI receivers — but they involve external hardware that adds power, bulk, and cost. If you’re building a quantity-of-one project and you don’t care about these things, then maybe the Pi is the right choice for the job, but if you’re prototyping a real product that’s going to go into production someday, you’ll want to look at the entire landscape before deciding what’s best.
是的，总有解决上述缺点的变通方法——比如使用 I2C 接口的 PWM 芯片、SPI 接口的 ADC 或带 HDMI 接收器的 LCD 模块——但它们涉及增加电源、体积和成本的外部硬件。如果你正在制作一个单独的项目，并且对这些问题不太在意，那么 Raspberry Pi 可能是适合这个工作的选择；但如果你正在为最终将投入生产的真实产品进行原型开发，那么在决定最佳选择之前，你需要全面了解整个市场情况。📦

A note about peripherals 关于外设的说明📝

This article is all about getting an embedded application processor booting Linux — not building an entire embedded system.
这篇文章主要讲的是如何让一个嵌入式应用处理器启动 Linux，而不是构建整个嵌入式系统。🖥️
If you’re considering running Linux in an embedded design, you likely have some combination of Bluetooth, WiFi, Ethernet, TFT touch screen, audio, camera, or low-power RF transceiver work going on.
如果你正在考虑在嵌入式设计中运行 Linux，那么你可能正在进行一些组合的蓝牙、WiFi、以太网、TFT 触摸屏、音频、摄像头或低功耗射频收发器的工作。📡

If you’re coming from the MCU world, you’ll have a lot of catching up to do in these areas, since the interfaces (and even architectural strategies) are quite different.
如果你是来自 MCU 世界的用户，在这些领域你需要做很多跟进，因为接口（甚至架构策略）是相当不同的。🔧
For example, while single-chip WiFi/BT MCUs are common, very few application processors have integrated WiFi/BT, so you’ll typically use external SDIO- or USB-interfaced chipsets. Your SPI-interfaced ILI9341 TFTs will often be replaced with parallel RGB or MIPI models.
例如，单芯片的 WiFi/蓝牙 MCU 很常见，但很少有应用处理器集成 WiFi/蓝牙，因此您通常会使用外部 SDIO 或 USB 接口的芯片组。您的 SPI 接口的 ILI9341 TFT 通常会被并行 RGB 或 MIPI 模型所替代。📡💻
And instead of burping out tones with your MCU’s 12-bit DAC, you’ll be wiring up I2S audio CODECs to your processor.
而不是使用 MCU 的 12 位 DAC 发出噪音，你将会把 I2S 音频 CODEC 连接到你的处理器上。🔌

Hardware Workflow 硬件工作流程 🔧

Processor vendors vigorously encourage reference design modification and reuse for customer designs.
处理器供应商积极鼓励参考设计的修改和再利用，以便于客户的设计。💻
I think most professional engineers are most concerned with getting Rev A hardware that boots up than playing around with optimization, so many custom Linux boards I see are spitting images of off-the-shelf EVKs.
我认为大多数专业工程师更关心的是获得能够启动的 Rev A 硬件，而不是玩优化，因此我看到的许多定制 Linux 板与现成的 EVK 几乎一模一样。🔧

But depending on the complexity of your project, this can become downright absurd.
但根据你项目的复杂性，这可能变得非常荒谬。😅
If you need the massive amount of RAM that some EVKs come with, and your design uses the same sorts of large parallel display and camera interfaces, audio codecs, and networking interfaces on the EVK, then it may be reasonable to use this as your base with little modification.
如果您需要一些开发板配备的大量 RAM，并且您的设计使用相同类型的大型并行显示器和相机接口、音频编解码器以及开发板上的网络接口，那么将其作为基础使用，几乎不作修改，是合理的。💻
However, using a 10-layer stack-up on your simple IoT gateway — just because that’s what the ref design used — is probably not something I’d throw in my portfolio to reflect a shining moment of ingenuity.
然而，在简单的 IoT 网关上使用 10 层堆叠——仅仅因为那是参考设计使用的——可能不是我会放入我的作品集中以体现一个闪耀的创新时刻的东西。💡

People forget that these EVKs are built at substantially higher volumes than prototype hardware is; I often have to explain to inexperienced project managers why it’s going to cost nearly $4000 to manufacture 5 prototypes of something you can buy for $56 each.
人们常常忘记，这些 EVK 的生产量远高于原型硬件的生产量；我经常需要向经验不足的项目经理解释，为什么制造 5 个你可以以每个 56 美元购买的原型，要花近 4000 美元。💵

You may discover that it’s worth the extra time to clean up the design a bit, simplify your stackup, and reduce your BOM — or just start from scratch.
您可能会发现，花额外的时间稍微清理一下设计、简化堆叠并减少 BOM 是值得的——或者干脆从头开始。🛠️
All of the boards I built up for this review were designed in a few days and easily hand-assembled with low-cost hot-plate / hot-air / pencil soldering in a few hours onto cheap 4-layer PCBs from JLC. Even including the cost of assembly labor, it would be hard to spend more than a few hundred bucks on a round of prototypes so long as your design doesn’t have a ton of extraneous circuitry.
我为这次评测组装的所有电路板是在几天内设计的，利用低成本的热板/热风/铅笔焊接，在几个小时内轻松手工组装到 JLC 的便宜四层 PCB 上。即使包括组装劳动力的费用，只要你的设计没有很多多余的电路，花费几百美元做一轮原型也很困难。💰

If you’re just going to copy the reference design files, the nitty-gritty details won’t be important. But if you’re going to start designing from-scratch boards around these parts, you’re going to notice some major differences from designing around microcontrollers.
如果你只是复制参考设计文件，那么细节就不那么重要了。📝 但如果你打算围绕这些组件从零开始设计电路板，你会发现与围绕微控制器设计时有一些重大不同之处。🔍

BGA Packages BGA 封装💻

Most of the parts in this review come in BGA packages, so we should talk a little bit about this. These seem to make less-experienced engineers nervous — both during layout and prototype assembly.
这篇评论中大多数部件都采用 BGA 封装，所以我们应该稍微谈谈这个。这似乎让经验不足的工程师在布线和原型组装时感到紧张。😟
As you would expect, more-experienced engineers are more than happy to gatekeep and discourage less-experienced engineers from using these parts, but actually, I think BGAs are much easier to design around than high-pin-count ultra-fine-pitch QFPs, which are usually your only other packaging option.
正如你所预期的，经验丰富的工程师非常乐意设立门槛，并且劝阻经验较少的工程师使用这些部件，但实际上，我认为 BGA 的设计比高引脚数超细间距 QFP 要容易得多，而 QFP 通常是你唯一的其他封装选择。🛠️

The standard 0.8mm-pitch BGAs that mostly make up this review have a coarse-enough pitch to allow a single trace to pass between two adjacent balls, as well as allowing a via to be placed in the middle of a 4-ball grid with enough room between adjacent vias to allow a track to go between them.
标准的 0.8 毫米间距 BGA 大多构成了本次评审，间距足够大以允许一条单独的引线在两个相邻的焊球之间通过，同时也允许在四球网格的中间放置一个通孔，相邻的通孔之间留有足够的空间以便于引线通过。🛠️
This is illustrated in the image above on the left: notice that the inner-most signals on the blue (bottom) layer escape the BGA package by traveling between the vias used to escape the outer-most signals on the blue layer.
如上图左侧所示：注意到蓝色（底部）层中最内层的信号通过在蓝色层上用于逃逸最外层信号的通孔之间传输，从 BGA 封装中逃逸。🔧

In general, you can escape 4 rows of signals on a 0.8mm-pitch BGA with this strategy: the first two rows of signals from the BGA can be escaped on the component-side layer, while the next two rows of signals must be escaped on a second layer.
一般来说，您可以使用这种策略在 0.8mm 间距的 BGA 上逃离 4 行信号：BGA 的前两行信号可以在元件侧层逃离，而接下来的两行信号必须在第二层上逃离。📏
If you need to escape more rows of signals, you’d need additional layers. IC designers are acutely aware of that; if an IC is designed for a 4-layer board (with two signal layers and two power planes), only the outer 4 rows of balls will carry I/O signals.
如果您需要传输更多行信号，就需要额外的层。🍃 芯片设计师对此非常清楚；如果一个芯片设计用于四层电路板（有两层信号层和两层电源平面），那么只有外侧的四行球体会携带 I/O 信号。🔌
If they need to escape more signals, they can start selectively depopulating balls on the outside of the package — removing a single ball gives space for three or four signals to fit through.
如果他们需要传输更多信号，可以开始选择性地减少封装外部的球 — 移除一个球可以为三个或四个信号提供空间。⚡

For 0.65mm-pitch BGAs (top right), a via can still (barely) fit between four pins, but there’s not enough room for a signal to travel between adjacent vias; they’re just too close.
对于 0.65mm 间距的 BGA（右上角），在四个引脚之间仍然可以（勉强）放置一个通孔，但相邻通孔之间没有足够的空间让信号传输；它们实在是太靠近了。📏
That’s why almost all 0.65mm-pitch BGAs must have selective depopulations on the outside of the BGA.
这就是为什么几乎所有 0.65mm 间距的 BGA 都必须在 BGA 的外侧进行选择性去除。🔧
You can see the escape strategy in the image on the right is much less orderly — there are other constraints (diff pairs, random power nets, final signal destinations) that often muck this strategy up.
你可以看到右侧图像中的逃逸策略显得杂乱无章——还有其他约束（不同的配对、随机的电源网络、最终的信号目标）经常使这一策略变得复杂。😅
I think the biggest annoyance with BGAs is that decoupling capacitors usually end up on the bottom of the board if you have to escape many of the signals, though you can squeeze them onto the top side if you bump up the number of layers on your board (many solder-down SOMs do this).
我认为 BGA 最大的烦恼是，如果你需要逃避许多信号，去耦电容通常会放在电路板的底部，不过如果你增加电路板的层数，就可以把它们挤到顶部（许多焊接型 SOM 也会这样做）。🛠️

Hand-assembling PCBs with these BGAs on them is a breeze. Because 0.8mm-pitch BGAs have such a coarse pitch, placement accuracy isn’t particularly important, and I’ve never once detected a short-circuit on a board I’ve soldered.
手工组装带有这些 BGA 的 PCB 非常简单。由于 0.8mm 间距的 BGA 有着较大的间距，放置精度并不是特别重要，我从未在自己焊接的电路板上发现过短路。😊
That’s a far cry from 0.4mm-pitch (or even 0.5mm-pitch) QFPs, which routinely have minor short-circuits here and there — mostly due to poor stencil alignment. I haven’t had issues soldering 0.65mm-pitch BGAs, either, but I feel like I have to be much more careful with them.
这与 0.4mm 间距（甚至 0.5mm 间距）QFPs 相去甚远，这些 QFP 通常会发生一些小短路——主要是由于模板对准不良。🛠️ 我在焊接 0.65mm 间距的 BGA 时也没有遇到问题，但我觉得我必须更加小心。💡

To actually solder the boards, if you have an electric cooktop (I like the Cuisineart ones), you can hot-plate solder boards with BGAs on them. I have a reflow oven, but I didn’t use it once during this review — instead, I hot-plate the top side of the board, flip it over, paste it up, place the passives on the back, and hit it with a bit of hot air.
要实际焊接电路板，如果你有一个电磁炉（我喜欢 Cuisineart 的），你可以用热板焊接带有 BGA 的电路板。🔥我有一个回流焊炉，但在这次评测中我一次都没有使用它——相反，我是在电路板的顶部热焊，翻过来，贴上胶水，放置被动元件在背面，然后用一点热空气处理。💨
Personally, I wouldn’t use a hot-air gun to solder BGAs or other large components, but others do it all the time. The advantage to hot-plate soldering is that you can poke and nudge misbehaving parts into place during the reflow cycle.
个人来说，我不会用热风枪来焊接 BGA 或其他大组件，但其他人总是这样做。热板焊接的优势在于你可以在回流过程中轻推或调整不听话的部件到位。🔥
I also like to give my BGAs a small tap to force them to self-align if they weren’t already.
我也喜欢给我的 BGA 轻轻一敲，以迫使它们自我对齐，如果它们还没有的话。🔧

Multiple voltage domains 多个电压域 ⚡

Microcontrollers are almost universally supplied with a single, fixed voltage (which might be regulated down internally), while most microprocessors have a minimum of three voltage domains that must be supplied by external regulators: I/O (usually 3.3V), core (usually 1.0-1.2V), and memory (fixed for each technology — 1.35V for DDR3L, 1.5V for old-school DDR3, 1.8V for DDR2, and 2.5V for DDR).
微控制器几乎普遍采用单一的固定电压（可能在内部进行了调节），而大多数微处理器则至少有三个电压域必须由外部稳压器供电： I/O（通常为 3.3V），核心（通常为 1.0-1.2V）和内存（根据每种技术固定 — DDR3L 为 1.35V，老式 DDR3 为 1.5V，DDR2 为 1.8V，DDR 为 2.5V）。⚡️
There are often additional analog supplies, and some higher-performance parts might have six or more different voltages you have to supply.
通常会有额外的模拟电源，一些高性能部件可能需要您提供六种或更多不同的电压。⚡

While many entry-level parts can be powered by a few discrete LDOs or DC/DC converters, some parts have stringent power-sequencing requirements.
虽然许多入门级的组件可以通过几个独立的 LDO 或 DC/DC 转换器供电，但有些组件对电源排序有严格的要求。🔋
Also, to minimize power consumption, many parts recommend using dynamic voltage scaling, where the core voltage is automatically lowered when the CPU idles and lowers its clock frequency.
此外，为了降低功耗，许多

These two points lead designers to I2C-interfaced PMIC (power management integrated circuit) chips that are specifically tailored to the processor’s voltage and sequencing requirements, and whose output voltages can be changed on the fly.
这两个要点使设计师们选择了 I2C 接口的 PMIC（电源管理集成电路）芯片，这些芯片专门针对处理器的电压和序列需求进行了调整，并且其输出电压可以实时更改。⚡
These chips might integrate four or more DC/DC converters, plus several LDOs. Many include multiple DC inputs along with built-in lithium-ion battery charging.
这些芯片可能集成四个或更多的直流/直流转换器，以及多个线性稳压器（LDO）。许多芯片包括多个直流输入，并配有内置锂离子电池充电功能。⚡
Coupled with the large inductors, capacitors, and multiple precision resistors some of these PMICs require, this added circuitry can explode your bill of materials (BOM) and board area.
与这些 PMIC 所需的大型电感、电容和多个精密电阻相结合，这些额外的电路可能会大幅增加你的材料清单（BOM）和电路板面积。💥

Regardless of your voltage regulator choices, these parts gesticulate wildly in their power consumption, so you’ll need some basic PDN design ability to ensure you can supply the parts with the current they need when they need it.
无论你选择什么类型的电压调节器，这些元件在功耗方面的变化都非常明显，因此你需要一些基本的 PDN 设计能力，以确保能在需要时为这些元件提供所需的电流。⚡
And while you won’t need to do any simulation or verification just to get things to boot, if things are marginal, expect EMC issues down the road that would not come up if you were working with simple microcontrollers.
虽然你不需要进行任何仿真或验证就能启动，但如果性能边缘，预计将来会出现 EMC 问题，而这些问题在使用简单微控制器时不会出现。🔧

Non-volatile storage 非易失性存储器🗄️

No commonly-used microprocessor has built-in flash memory, so you’re going to need to wire something up to the MPU to store your code and persistent data.
没有常用的微处理器内置闪存，因此您需要将某些东西连接到 MPU，以存储您的代码和持久数据。💻
If you’ve used parts from fabless companies who didn’t want to pay for flash IP, you’ve probably gotten used to soldering down an SPI NOR flash chip, programming your hex file to it, and moving on with your life.
如果你使用过那些不想为闪存 IP 付费的无晶圆厂公司的部件，你可能已经习惯了焊接一个 SPI NOR 闪存芯片，将十六进制文件烧录到上面，然后继续你的生活。💻
When using microprocessors, there are many more decisions to consider.
在使用微处理器时，还有许多其他决策需要考虑。💡

Most MPUs can boot from SPI NOR flash, SPI NAND flash, parallel, or MMC (for use with eMMC or MicroSD cards). Because of its organization, NOR flash memory has better read speeds but worse write speeds than NAND flash.
大多数 MPU 可以从 SPI NOR 闪存、SPI NAND 闪存、并行接口或 MMC（用于 eMMC 或 MicroSD 卡）启动。😄由于其结构，NOR 闪存的读取速度比 NAND 闪存更快，但写入速度更慢。📉
SPI NOR flash memory is widely used for tiny systems with up to 16 MB of storage, but above that, SPI NAND and parallel-interfaced NOR and NAND flash become cheaper.
SPI NOR 闪存广泛应用于存储容量高达 16 MB 的微型系统，但超过这个容量后，SPI NAND 和并行接口的 NOR 和 NAND 闪存变得更加便宜。💾
Parallel-interfaced NOR flash used to be the ubiquitous boot media for embedded Linux devices, but I don’t see it deployed as much anymore — even though it can be found at sometimes half the price of SPI flash.
并行接口的 NOR 闪存曾是嵌入式 Linux 设备的普遍启动介质，但我发现它现在的应用不如以前了——即使它有时价格仅为 SPI 闪存的一半。💾
My only explanation for its unpopularity is that no one likes wasting lots of I/O pins on parallel memory.
我唯一能解释其不受欢迎的原因是，没有人喜欢在并行内存上浪费大量的 I/O 引脚。🛠️

Above 1 GB, MMC is the dominant technology in use today.
在 1GB 以上，MMC 是目前主流使用的技术。📱
For development work, it’s especially hard to beat a MicroSD card — in low volumes they tend to be cheaper per gigabyte than anything else out there, and you can easily read and write to them without having to interact with the MPU’s USB bootloader; that’s why it was my boot media of choice on almost all platforms reviewed here.
对于开发工作来说，MicroSD 卡几乎无人能敌——在较小的数量中，它们的每千兆字节成本往往比其他任何存储介质都要便宜，而且你可以轻松地读取和写入，无需与 MPU 的 USB 引导加载程序交互；这就是为什么它是我在这里评测的几乎所有平台上的首选启动介质。💾
In production, you can easily switch to eMMC, which is, very loosely speaking, a solder-down version of a MicroSD card.
在生产中，你可以轻松切换到 eMMC，松散地说，它是 MicroSD 卡的一种焊接版本。🔄

Booting 启动 🚀

Back when parallel-interfaced flash memory was the only game in town, there was no need for boot ROMs: unlike SPI or MMC, these devices have address and data pins, so they are easily memory-mapped; indeed, older processors would simply start executing code straight out of parallel flash on reset.
在并行接口闪存还是唯一选择的时候，根本不需要启动 ROM：与 SPI 或 MMC 不同，这些设备拥有地址和数据引脚，因此它们易于进行内存映射；实际上，旧款处理器在重置后会直接开始执行并行闪存中的代码。💾

That’s all changed though: modern application processors have boot ROM code baked into the chip to initialize the SPI, parallel, or SDIO interface, load a few pages out of flash memory into RAM, and start executing it.
不过这一切都改变了：现代应用处理器在芯片中内置了启动 ROM 代码，以初始化 SPI、并行或 SDIO 接口，将几页闪存中的内容加载到 RAM 中，并开始执行。🔧
Some of these ROMs are quite fancy, actually, and can even load files stored inside a filesystem on an MMC device. When building embedded hardware around a part, you’ll have to pay close attention to how to configure this boot ROM.
这些 ROM 实际上相当高级，甚至可以加载存储在 MMC 设备文件系统中的文件。🔧 当围绕一个部件构建嵌入式硬件时，你需要密切关注如何配置这个引导 ROM。📦

While some microprocessors have a basic boot strategy that simply tries every possible flash memory interface in a specified order, others have extremely complicated (“flexible”?) boot options that must be configured through one-time-programmable fuses or GPIO bootstrap pins.
一些微处理器具有基本的启动策略，按照指定的顺序简单地尝试每个可能的闪存接口，而另一些则具有极其复杂的（“灵活的”？）启动选项，这些选项必须通过一次性可编程保险丝或 GPIO 引导引脚进行配置。🔧
And no, we’re not talking about one or two signals you need to handle: some parts have more than 30 different bootstrap signals that must be pulled high or low to get the part booting correctly.
而且，不，我们不是在谈论你需要处理一两个信号：有些部件有超过 30 个不同的引导信号，必须拉高或拉低才能使该部件正确启动。🔧

Console UART 控制台 UART 💻

Unlike MCU-based designs, on an embedded Linux system, you absolutely, positively, must have a console UART available. Linux’s entire tracing architecture is built around logging messages to a console, as is the U-Boot bootloader.
与基于 MCU 的设计不同，在嵌入式 Linux 系统中，您绝对必须有一个可用的控制台 UART。🌟 Linux 的整个追踪架构是围绕将消息记录到控制台而构建的，U-Boot 引导加载程序也是如此。💻

That doesn’t mean you shouldn’t also have JTAG/SWD access, especially in the early stage of development when you’re bringing up your bootloader (otherwise you’ll be stuck with printf() calls).
这并不意味着你不应该拥有 JTAG/SWD 访问权限，尤其是在开发初期，当你在启动引导程序时（否则你将只能使用 printf() 调用）。📡
Having said that, if you actually have to break out your J-Link on your embedded Linux board, it probably means you’re having a really bad day. While you can attach a debugger to an MPU, getting everything set up correctly is extremely clunky when compared to debugging an MCU.
说到这里，如果你实际上需要在嵌入式 Linux 板上使用 J-Link，那可能意味着你正经历一个非常糟糕的一天。🤖 尽管你可以将调试器连接到 MPU，但与调试 MCU 相比，正确设置一切是非常繁琐的。🛠️
Prepare to relocate symbol tables as your code transitions from SRAM to main DRAM memory. It’s not uncommon to have to muck around with other registers, too (like forcing your CPU out of Thumb mode).
准备在代码从 SRAM 切换到主 DRAM 内存时重新定位符号表。💻 处理其他寄存器也是很常见的事情（比如强制你的 CPU 退出 Thumb 模式）。🔧
And on top of that, I’ve found that some U-Boot ports remux the JTAG pins (either due to alternate functionality or to save power), and the JTAG chains on some parts are quite complex and require using less-commonly used pins and features of the interface.
而且，我发现某些 U-Boot 移植会重新映射 JTAG 引脚（要么是由于其他功能，要么是为了节省功耗），并且某些芯片上的 JTAG 链非常复杂，需要使用不常用的引脚和接口特性。🔌
Oh, and since you have an underlying Boot ROM that executes first, JTAG adapters can screw that up, too.
哦，并且由于你有一个首先执行的底层引导 ROM，JTAG 适配器也可能会搞砸这一点。🔧

Sidebar: Gatekeepers and the Myth of DDR Routing Complexity
侧边栏：守门人和 DDR 路由复杂性的神话 🛡️

If you start searching around the Internet, you’ll stumble upon a lot of posts from people asking about routing an SDRAM memory bus, only to be discouraged by “experts” lecturing them on how unbelievably complex memory routing is and how you need a minimum 6-layer stack-up and super precise length-tuning and controlled impedances and $200,000 in equipment to get a design working.
如果你开始在互联网上搜索，你会发现很多人发帖询问如何设计 SDRAM 内存总线，结果却被一些“专家”劝退，他们在讲述内存布线是多么复杂，以及你需要至少 6 层的堆叠、超精确的长度调节、受控的阻抗，以及需要 20 万美元的设备才能使设计正常工作。💻

That’s utter bullshit. In the grand scheme of things, routing memory is, at worst, a bit tedious. Once you’ve had some practice, it should take about an hour or so to route a 16-bit-wide single-chip DDR3 memory bus, so I’d hardly call it an insurmountable challenge.
这完全是胡扯。在大局上，布线内存最多也就是有点繁琐。🕒 一旦你有了一些实践经验，布线一个 16 位宽的单芯片 DDR3 内存总线大概需要一个小时左右，所以我根本不认为这是一项无法克服的挑战。💪
It’s worth investing a bit of time to learn about it since it will give you immense design flexibility when architecting your system (since you won’t be beholden to expensive SoMs or SiP-packaged parts).
值得花一点时间去了解它，因为在构建系统时，它会给你带来巨大的设计灵活性（因为你不必依赖昂贵的系统模块或系统级封装部件）。💡

Let’s get one thing straight: I’m not talking about laying out a 64-bit-wide quad-bank memory bus with 16 chips on an 8-layer stack-up. Instead, we’re focused on a single 16-bit-wide memory chip routed point-to-point with the CPU.
让我们先搞清楚一点：我并不是在谈论设计一个 64 位宽、16 个芯片的四银行内存总线，层数为 8 层。相反，我们关注的是一个 16 位宽的单芯片内存，采用点对点的方式与 CPU 连接。💻
This is the layout strategy you’d use with all the parts in this review, and it is drastically simpler than multi-chip layouts — no address bus terminations, complex T-topology routes, or fly-by write-leveling to worry about.
这是您在本次评审中使用的布局策略，它比多芯片布局简单得多——不需要担心地址总线终端、复杂的 T 型拓扑线路或飞翔写入均衡。📐
And with modern dual-die DRAM packages, you can get up to 2 GB capacity in a single DDR3L chip. In exchange for the markup you’ll pay for the dual-die chips, you’ll end up with much easier PCB routing.
现代双芯片 DRAM 封装可以让您在单个 DDR3L 芯片中获得高达 2GB 的容量。💾 作为购买双芯片的溢价回报，您将能够更轻松地进行 PCB 布线。🛠️

Length Tuning 长度调节 🔧

When most people think of DDR routing, length-tuning is the first thing that comes to mind. If you use a decent PCB design package, setting up length-tuning rules and laying down meandered routes is so trivial to do that most designers don’t think anything of it — they just go ahead and length-match everything that’s relatively high-speed — SDRAM, SDIO, parallel CSI / LCD, etc. Other than adding a bit of design time, there’s no reason not to maximize your timing margins, so this makes sense.
当大多数人想到 DDR 布线时，长度调节是首先浮现在脑海中的事情。🛠️如果你使用一个不错的 PCB 设计软件，设置长度调节规则和绘制曲折走线路径是非常简单的，因此大多数设计师对此并不在意——他们只是继续对相对高速的全部线路进行长度匹配——SDRAM、SDIO、并行 CSI / LCD 等。📏除了增加一些设计时间外，没有理由不去最大化你的时序余量，所以这样做是合乎逻辑的。🔍

But what if you’re stuck in a crappy software package, manually exporting spreadsheets of track lengths, manually determining matching constraints, and — gasp — maybe even manually creating meanders? Just how important is length-matching? Can you get by without it?
但如果你被困在一个糟糕的软件包中，手动导出轨道长度的电子表格，手动确定匹配约束，甚至 — 喘气 — 也许还要手动创建蜿蜒路径呢？长度匹配到底有多重要？没有它可以过得去吗？😱

Most microprocessors reviewed here top out at DDR3-800, which has a bit period of 1250 ps. Slow DDR3-800 memory might have a data setup time of up to 165 ps at AC135 levels, and a hold time of 150 ps. There’s also a worst-case skew of 200 ps.
这里审查的大多数微处理器的最高频率为 DDR3-800，其位周期为 1250 皮秒。😌 缓慢的 DDR3-800 内存在 AC135 水平下的数据准备时间可能高达 165 皮秒，保持时间为 150 皮秒。📊 还有最坏情况下的偏移时间为 200 皮秒。⚠️
Let’s assume our microprocessor has the same specs. That means we have 200 ps of skew from our processor + 200 ps of skew from our DRAM chip + 165 ps setup time + 150 ps of hold time = 715 ps total. That leaves a margin of 535 ps (more than 3500 mil!) for PCB length mismatching.
假设我们的微处理器具有相同的规格。🖥️这意味着我们有来自处理器的 200 ps 的偏差 + 来自 DRAM 芯片的 200 ps 的偏差 + 165 ps 的建立时间 + 150 ps 的保持时间 = 总共 715 ps。📏这为 PCB 长度不匹配留出了 535 ps 的裕度（超过 3500 mil！）。📐

Are our assumptions about the MPU’s memory controller valid? Who knows. One issue I ran into is that there’s a nebulous cloud surrounding the DDR controllers on many application processors. Take the i.MX 6UL as an example: I discovered multiple posts where people add up worst-case timing parameters in the datasheet, only to end up with practically no timing margin. These official datasheet numbers seem to be pulled out of thin air — so much so that NXP literally removed the entire DDR section in their datasheet and replaced it with a boiler-plate explanation telling users to follow the “hardware design guidelines.” Texas Instruments and ST also lack memory controller timing information in their documentation — again, referring users to stringent hardware design rules.
我们对 MPU 内存控制器的假设是否有效？谁知道呢🤔。我遇到的一个问题是，许多应用处理器上的 DDR 控制器都笼罩着一层模糊的云雾☁️。以 i.MX 6UL 为例：我发现有多篇帖子，大家在数据手册中相加最坏情况的时序参数，结果几乎没有时序裕量😞。这些官方数据手册上的数字似乎完全是凭空而来——以至于 NXP 真的将其数据手册中的整个 DDR 部分删除，替换为一段标准文本，告诉用户遵循“硬件设计指南”📜。德州仪器和 ST 在它们的文档中也缺乏内存控制器的时序信息——同样是让用户遵循严格的硬件设计规则🔧。
((Rockchip and Allwinner don’t specify any sort of timing data or length-tuning guidelines for their processors at all.))
Rockchip 和 Allwinner 完全没有为他们的处理器指定任何类型的时序数据或长度调整指南。🕒

How stringent are these rules? Almost all of these companies recommend a ±25-mil match on each byte group. Assuming 150 ps/cm propagation delay, that’s ±3.175 ps — only 0.25% of that 1250ps DDR3-800 bit period. That’s absolutely nuts.
这些规则有多严格？几乎所有这些公司都建议每个字节组匹配±25 毫英寸。💡假设传播延迟为 150 皮秒/厘米，那就是±3.175 皮秒——仅占 1250 皮秒 DDR3-800 位周期的 0.25%。😲这简直太疯狂了。
Imagine if you were told to ensure your breadboard wires were all within half an inch in length of each other before wiring up your Arduino SPI sensor project — that’s the equivalent timing margin we’re talking about.
想象一下，如果有人告诉你在给你的 Arduino SPI 传感器项目接线之前，确保你的面包板电线长度相差不超过半英寸——这就是我们所说的相当于的时间裕度。🕒

To settle this, I empirically tested two DDR3-800 designs — one with and one without length tuning — and they performed identically. In neither case was I ever able to get a single bit error, even after thousands of iterations of memory stress-tests.
为了验证这一点，我通过实验证明了两种 DDR3-800 设计——一种带有长度调节，一种不带——它们的性能完全相同。在这两种情况下，我都没有遇到过任何比特错误，即使经过了数千次的内存压力测试。🔍
Yes, that doesn’t prove that the design would run for 24/7/365 without a bit error, but it’s definitely a start. Just to verify I wasn’t on the margin, or that this was only valid for one processor, I overclocked a second system’s memory controller by two times — running a DDR3-800 controller at DDR3-1600 speeds — and I was still unable to get a single bit error.
是的，这并不能证明该设计可以 24/7/365 地运行而不出现位错误，但这绝对是一个开始。为确保我不是在临界区域，或者此结果仅适用于一台处理器，我将第二套系统的内存控制器超频了两倍——将 DDR3-800 控制器以 DDR3-1600 的速度运行——但我仍然没有遇到任何位错误。💻
In fact, all five of my discrete-SDRAM-based designs violated these length-matching guidelines and all five of them completed memory tests without issue, and in all my other testing, I never experienced a single crash or lock-up on any of these boards.
事实上，我的五个基于离散 SDRAM 的设计都违反了这些长度匹配指南，但它们全部顺利完成了内存测试，而且在我进行的其他所有测试中，这些电路板没有出现过一次崩溃或卡死。💻

My take-away: length-tuning is easy if you have good CAD software, and there’s no reason not to spend an extra 30 minutes length-tuning things to maximize your timing budget.
我的收获是：如果你有好的 CAD 软件，调节长度是很简单的，没有理由不花多 30 分钟调整长度，以最大化你的时间预算。🛠️
But if you use crappy CAD software or you’re rushing to get a prototype out the door, don’t sweat it — especially for Rev A.
但是如果你使用劣质的 CAD 软件或者急于推出原型，不用担心——特别是对于 Rev A。😅

More importantly, a corollary: if your design doesn’t work, length-tuning is probably the last thing you should be looking at. For starters, make sure you have all the pins connected properly — even if the failures appear intermittent. For example, accidentally swapping byte lane strobes / masks (like I’ve done) will cause 8-bit operations to fail without affecting 32-bit operations. Since the bulk of RAM accesses are 32-bit, things will appear to kinda-sorta work.
更重要的是，一个推论：如果你的设计不起作用，长度调整可能是你最后应该关注的事情。🔧 首先，确保所有引脚都正确连接——即使故障看起来是间歇性的。🔌 例如，意外地交换字节通道的时钟/掩码（就像我做过的那样）会导致 8 位操作失败，而不影响 32 位操作。📉 由于大部分内存访问是 32 位的，事情会看起来有点儿正常。💻

Signal Integrity 信号完整性 📶

Instead of worrying about length-tuning, if a design is failing (either functionally or in the EMC test chamber), I would look first at power distribution and signal integrity.
与其担心长度调谐，不如先关注电源分配和信号完整性，如果设计失败（无论是功能上还是在 EMC 测试室中）。🔧
I threw together some HyperLynx simulations of various board designs with different routing strategies to illustrate some of this.
我结合了一些 HyperLynx 模拟，展示了不同布线策略的多种电路板设计，以说明一些相关内容。💻
I’m not an SI expert, and there are better resources online if you want to learn more practical techniques; for more theory, the books that everyone seems to recommend are by Howard Johnson: High Speed Digital Design: A Handbook of Black Magic and High Speed Signal Propagation: Advanced Black Magic, though I’d also add Henry Ott’s Electromagnetic Compatibility Engineering book to that list.
我不是 SI 专家，如果你想学习更多实用技巧，网上有更好的资源；对于更多理论，大家似乎推荐的书是霍华德·约翰逊的《高速数字设计：黑魔法手册》和《高速信号传播：高级黑魔法》，不过我也会将亨利·奥特的《电磁兼容工程》一书加入到这个名单中。📚

Ideally, every signal’s source impedance, trace impedance, and load impedance would match.
理想情况下，每个信号的源阻抗、传输线阻抗和负载阻抗应当匹配。⚡
This is especially important as a trace’s length starts to approach the wavelength of the signal (I think the rule of thumb is 1/20th the wavelength), which will definitely be true for 400 MHz and faster DDR layouts.
这尤其重要，因为当导线的长度接近信号的波长时（我认为经验法则是波长的 1/20），这对于 400 MHz 及更快的 DDR 布局肯定是正确的。📏

Using a proper PCB stack-up (usually a ~0.1mm prepreg will result in a close-to-50-ohm impedance for a 5mil-wide trace) is your first line of defense against impedance issues, and is usually sufficient for getting things working well enough to avoid simulation / refinement.
使用合适的 PCB 叠层（通常约 0.1mm 的预浸料会导致 5mil 宽度的走线接近 50 欧姆的阻抗）是防止阻抗问题的第一道防线，通常足以使系统正常工作，从而避免模拟/优化。📏

For the data groups, DDR3 uses on-die termination (ODT), configurable for 40, 60, or 120 ohm on memory chips (and usually the same or similar on the CPU) along with adjustable output impedance drivers.
对于数据组，DDR3 采用芯片内终端（ODT），可以在内存芯片上配置为 40、60 或 120 欧姆（通常 CPU 上的配置相同或相似），并配有可调输出阻抗驱动器。📊
ODT is only enabled on the receiver’s end, so depending on whether you’re writing data or reading data, ODT will either be enabled on the memory chip, or on the CPU.
ODT 只在接收端启用，因此根据您是写数据还是读数据，ODT 要么在内存芯片上启用，要么在 CPU 上启用。💻

For simple point-to-point routing, don’t worry too much about ODT settings.
对于简单的点对点路由，不用过于担心 ODT 设置。🔧
As can be seen in the above eye diagram, the difference between 33-ohm and 80-ohm ODT terminations on a CPU reading from DRAM is perceivable, but both are well within AC175 levels (the most stringent voltage levels in the DDR3 spec).
从上述眼图可以看出，CPU 从 DRAM 读取时，33 欧姆和 80 欧姆的 ODT 终端之间的差异是可感知的，但它们都在 AC175 等级之内（这是 DDR3 规范中最严格的电压等级）。📊
The BSP for your processor will initialize the DRAM controller with default settings that will likely work just fine.
您的处理器的 BSP 将使用默认设置初始化 DRAM 控制器，这些设置应该可以正常工作。🌟

The biggest source of EMC issues related to DDR3 is likely going to come from your address bus. DDR3 uses a one-way address bus (the CPU is always the transmitter and the memory chip is always the receiver), and DDR memory chips do not have on-chip termination for these signals.
与 DDR3 相关的电磁兼容性（EMC）问题的最大来源很可能来自于你的地址总线。🔌 DDR3 使用单向地址总线（CPU 始终是发送方，内存芯片始终是接收方），并且 DDR 内存芯片对这些信号没有片上终端。🧠
Theoretically, they should be terminated to VTT (a voltage derived from VDDQ/2) with resistors placed next to the DDR memory chip. On large fly-by buses with multiple memory chips, you’ll see these VTT termination resistors next to the last chip on the bus.
理论上，它们应该通过放置在 DDR 内存芯片旁边的电阻接地到 VTT（一个来自 VDDQ/2 的电压）。在多个内存芯片的大型飞线总线上，您会在总线的最后一个芯片旁边看到这些 VTT 终结电阻。📌
The resistors absorb the EM wave propagating from the MPU which reduces the reflections back along the transmission line that all the memory chips would see as voltage fluctuations.
电阻吸收来自 MPU 的电磁波，这减少了在传输线上反射回来的波，所有内存芯片会将其视为电压波动。📡
On small point-to-point designs, the length of the address bus is usually so short that there’s no need to terminate.
在小型点对点设计中，地址总线的长度通常非常短，因此不需要终端。🔌
If you run into EMC issues, consider software fixes first, like using slower slew-rate settings or increasing the output impedance to soften up your signals a bit.
如果你遇到电磁兼容性的问题，首先考虑软件修复，比如使用更慢的率变化设置或增加输出阻抗，以稍微减弱信号。⚡

Another source of SI issues is cross-coupling between traces. To reduce cross-talk, you can put plenty of space between traces — three times the width (3S) is a standard rule of thumb.
另一个 SI 问题的来源是走线之间的串扰。为了减少串扰，您可以在走线之间留出足够的空间——通常是走线宽度的三倍（3S）是一个标准的经验法则。📏
I sound like a broken record, but again, don’t be too dogmatic about this unless you’re failing tests, as the lengths involved with routing a single chip are so short.
我听起来像个老生常谈，但再次提醒，除非你考试不及格，否则不要对此过于死板，因为单个芯片的布线长度非常短。🎶
The above figure illustrates the routing of a DDR bus with no length-tuning but with ample space between traces. Note the eye diagram (below) shows much better signal integrity (at the expense of timing skew) than the first eye diagram presented in this section.
上面的图示说明了一个没有长度调节的 DDR 总线的布线，但信号线之间有足够的间隔。请注意，下面的眼图显示的信号完整性要比本节首次呈现的眼图好得多（尽管牺牲了时序偏差）。📊

Pin Swapping 引脚互换 🔄

Because DDR memory doesn’t care about the order of the bits getting stored, you can swap individual bits — except the least-significant one if you’re using write-leveling — in each byte lane with no issues. Byte lanes themselves are also completely swappable.
因为 DDR 内存不关心存储位的顺序，你可以在每个字节通道中交换单个位——如果使用写入均衡，则最不重要的位除外——而没有任何问题。字节通道本身也是完全可以互换的。💾
Having said that, since all the parts I reviewed are designed to work with a single x16-wide DDR chip (which has an industry-standard pinout), I found that most pins were already balled out reasonably well.
尽管如此，由于我审核的所有部件都是为单个 x16 宽的 DDR 芯片设计的（该芯片具有行业标准的引脚布局），我发现大多数引脚已经合理地进行了引出。🔌
Before you start swapping pins, make sure you’re not overlooking an obvious layout that the IC designers intended.
在开始交换引脚之前，确保你没有忽视集成电路设计师所意图的明显布局。🔄

Recommendations 建议 💡

Instead of worrying about chatter you read on forums or what the HyperLynx salesperson is trying to spin, for simple point-to-point DDR designs, you shouldn’t have any issues if you follow these suggestions:
与其担心你在论坛上看到的闲聊或 HyperLynx 销售人员的推销，不如对简单的点对点 DDR 设计遵循以下建议，这样你就不会遇到任何问题：💡

Pay attention to PCB stack-up. Use a 4-layer stack-up with thin prepreg (~0.1mm) to lower the impedance of your microstrips — this allows the traces to transfer more energy to the receiver. Those inner layers should be solid ground and DDR VDD planes respectively.
注意 PCB 叠层结构。使用四层叠层，薄的预浸料（约 0.1mm）可以降低微带线的阻抗——这样可以使线路更有效地将能量传输到接收器。内层应分别为实心接地层和 DDR VDD 电源层。⚡
Make sure there are no splits under the routes. If you’re nit-picky, pull back the outer-layer copper fills from these tracks so you don’t inadvertently create coplanar structures that will lower the impedance too much.
确保在布线路径下没有分裂。 如果你比较挑剔，拉回这些轨道的外层铜填充，以免无意中创建共面结构，从而降低阻抗过多。 🛤️

Avoid multiple DRAM chips. If you start adding extra DRAM chips, you’ll have to route your address/command signals with a fly-by topology (which requires terminating all those signals — yuck), or a T-topology (which requires additional routing complexity).
避免使用多个 DRAM 芯片。如果你开始添加额外的 DRAM 芯片，你必须以飞行拓扑来布线你的地址/命令信号（这需要终端所有这些信号——真糟糕），或者使用 T 型拓扑（这需要额外的布线复杂性）。💡
Stick with 16-bit-wide SDRAM, and if you need more capacity, spend the extra money on a dual-die chip — you can get up to 2 GB of RAM in a single X16-wide dual-rank chip, which should be plenty for anything you’d throw at these CPUs.
坚持使用 16 位宽的 SDRAM，如果你需要更大的容量，可以花额外的钱购买双晶片芯片——在单个 X16 宽的双排列芯片中，你可以获得高达 2GB 的 RAM，这对于任何你想要使用的这些 CPU 来说应该足够了。🖥️

Faster RAM makes routing easier. Even though our crappy processors reviewed here rarely can go past 400-533 MHz DDR speeds, using 800 or 933 MHz DDR chips will ease your timing budget.
更快的 RAM 使得路由更简单。尽管我们在这里评测的劣质处理器很少能超过 400-533 MHz 的 DDR 速度，使用 800 或 933 MHz 的 DDR 芯片将会减轻你的时序预算。⚡️
The reduced setup/hold times make address/command length-tuning almost entirely unnecessary, and the reduced skew even helps with the bidrectional data bus signals.
减少的设置/保持时间使得地址/命令长度调节几乎完全不必要，而减少的偏斜甚至有助于双向数据总线信号。📉

Software Workflow 软件工作流程 ⚙️

Developing on an MCU is simple: install the vendor’s IDE, create a new project, and start programming/debugging. There might be some .c/.h files to include from a library you’d like to use, and rarely, a precompiled lib you’ll have to link against.
在单片机上开发很简单：安装供应商的集成开发环境，创建一个新项目，然后开始编程/调试。可能需要包含一些你想使用的库中的 .c/.h 文件，偶尔还需要链接一个预编译的库。💻

When building embedded Linux systems, we need to start by compiling all the off-the-shelf software we plan on running — the bootloader, kernel, and userspace libraries and applications.
在构建嵌入式 Linux 系统时，我们需要首先编译所有计划运行的现成软件——引导加载程序、内核以及用户空间库和应用程序。🛠️
We’ll have to write and customize shell scripts and configuration files, and we’ll also often write applications from scratch. It’s really a totally different development process, so let’s talk about some prerequisites.
我们需要编写和定制 shell 脚本和配置文件，通常还会从头开始编写应用程序。这真的是一个完全不同的开发过程，所以让我们谈谈一些前提条件。🛠️

If you want to build a software image for a Linux system, you’ll need a Linux system. If you’re also the person designing the hardware, this is a bit of a catch-22 since most PCB designers work in Windows. While Windows Subsystem for Linux will run all the software you need to build an image for your board, WSL currently has no ability to pass through USB devices, so you won’t be able to use hardware debuggers (or even a USB microSD card reader) from within your Linux system.
如果你想为 Linux 系统构建一个软件镜像，你需要一个 Linux 系统。🖥️ 如果你也是设计硬件的人，这就有点矛盾，因为大多数 PCB 设计师在 Windows 中工作。🔧 虽然 Windows 的 Linux 子系统可以运行你构建板子镜像所需的所有软件，但 WSL 目前没有传递 USB 设备的能力，因此你将无法在 Linux 系统中使用硬件调试器（甚至是 USB microSD 卡读取器）。📱
And since WSL2 is Hyper-V-based, once it’s enabled, you won’t be able to launch VMware, which uses its own hypervisor((Though a beta versions of VMWare will address this)).
由于 WSL2 是基于 Hyper-V 的，一旦启用，您将无法启动使用其自有虚拟机管理程序的 VMware（尽管 VMware 的测试版将解决此问题）。🖥️

Consequently, I recommend users skip over all the newfangled tech until it matures a bit more, and instead just spin up an old-school VMWare virtual machine and install Linux on it.
因此，我建议用户跳过所有新奇的技术，直到它们成熟一些，而是直接启动一个老式的 VMWare 虚拟机并在上面安装 Linux。🖥️
In VMWare you can pass through your MicroSD card reader, debug probe, and even the device itself (which usually has a USB bootloader).
在 VMWare 中，你可以直接传递你的 MicroSD 卡读卡器、调试探针，甚至设备本身（通常具有 USB 引导加载程序）。📦

Building images is a computationally heavy and highly-parallel workload, so it benefits from large, high-wattage HEDT/server-grade multicore CPUs in your computer — make sure to pass as many cores through to your VM as possible.
构建镜像是一个计算量大且高度并行的工作负载，因此可以从计算机中的大型、高功率的 HEDT/服务器级多核 CPU 中受益——确保尽可能将更多核心传递给你的虚拟机。💻
Compiling all the software for your target will also eat through storage quickly: I would allocate an absolute minimum of 200 GB if you anticipate juggling between a few large embedded Linux projects simultaneously.
编译所有针对目标的软件将迅速占用存储空间：如果您预计要同时处理几个大型嵌入式 Linux 项目，我建议至少分配 200 GB 的存储空间。💾

While your specific project will likely call for much more software than this, these are the five components that go into every modern embedded Linux system((Yes, there are alternatives to these components, but the further you move away from the embedded Linux canon, the more you’ll find yourself on your own island, scratching your head trying to get things to work.)):
虽然你的具体项目可能需要更多的软件，但

• A cross toolchain, usually GCC + glibc, which contains your compiler, binutils, and C library. This doesn’t actually go into your embedded Linux system, but rather is used to build the other components.
  交叉工具链，通常是 GCC + glibc，其中包含编译器、二进制工具和 C 库。这实际上并不会进入你的嵌入式 Linux 系统，而是用来构建其他组件。🔧
• U-boot, a bootloader that initializes your DRAM, console, and boot media, and then loads the Linux kernel into RAM and starts executing it.
  U-boot 是一个引导加载程序，它初始化你的 DRAM、控制台和启动媒体，然后将 Linux 内核加载到内存中并开始执行。🚀
• The Linux kernel itself, which manages memory, schedules processes, and interfaces with hardware and networks.
  Linux 内核本身负责管理内存、调度进程，并与硬件和网络进行交互。🖥️
• Busybox, a single executable that contains core userspace components (init, sh, etc)
  Busybox，一个包含核心用户空间组件（init、sh 等）的单个可执行文件。🔧
• a root filesystem, which contains the aforementioned userspace components, along with any loadable kernel modules you compiled, shared libraries, and configuration files.
  根文件系统，其中包含上述用户空间组件，以及您编译的任何可加载内核模块、共享库和配置文件。📂

As you’re reading through this, don’t get overwhelmed: if your hardware is reasonably close to an existing reference design or evaluation kit, someone has already gone to the trouble of creating default configurations for you for all of these components, and you can simply find and modify them.
在您阅读这篇文章时，不要感到不知所措：如果您的硬件与现有的参考设计或评估板大致相近，那么已经有人为您创建了所有这些组件的默认配置，您只需找到并修改它们即可。📦
As an embedded Linux developer doing BSP work, you’ll spend way more time reading other people’s code and modifying it than you will be writing new software from scratch.
作为一名嵌入式 Linux 开发者，从事 BSP 工作，你将花费更多的时间阅读和修改其他人的代码，而不是从头编写新的软件。🖥️

Cross Toolchain 交叉工具链 🛠️

Just like with microcontroller development, when working on embedded Linux projects, you’ll write and compile the software on your computer, then remotely test it on your target. When programming microcontrollers, you’d probably just use your vendor’s IDE, which comes with a cross toolchain — a toolchain designed to build software for one CPU architecture on a system running a different architecture. As an example, when programming an ATTiny1616, you’d use a version of GCC built to run on your x64 computer but designed to emit AVR code.
就像进行微控制器开发一样，当你在嵌入式 Linux 项目上工作时，你会在计算机上编写和编译软件，然后在目标设备上进行远程测试。💻 当编程微控制器时，你可能只会使用厂商提供的集成开发环境（IDE），其中包含交叉工具链——这是一个旨在在运行不同架构的系统上为一种 CPU 架构构建软件的工具链。🔧 举个例子，当编程 ATTiny1616 时，你会使用一个为你的 x64 计算机构建的 GCC 版本，但它设计用于输出 AVR 代码。📦
With embedded Linux development, you’ll need a cross toolchain here, too (unless you’re one of the rare types coding on an ARM-based laptop or building an x64-powered embedded system).
在嵌入式 Linux 开发中，你也需要一个交叉工具链（除非你是那些稀有的在 ARM 基础笔记本电脑上编码或构建 x64 驱动的嵌入式系统的人）。💻

When configuring your toolchain, there are two lightweight C libraries to consider — musl libc and uClibc-ng — which implement a subset of features of the full glibc, while being 1/5th the size. Most software compiles fine against them, so they’re a great choice when you don’t need the full libc features. Between the two of them, uClibc is the older project that tries to act more like glibc, while musl is a fresh rewrite that offers some pretty impressive stats, but is less compatible.
在配置您的工具链时，有两个轻量级的 C 库需要考虑——musl libc 和 uClibc-ng——它们实现了 glibc 的子集功能，同时体积仅为其 1/5。🔧 大多数软件在它们上编译都很好，因此当您不需要完整的 libc 功能时，它们是一个很好的选择。💡 在它们之间，uClibc 是一个较老的项目，试图更像 glibc，而 musl 则是一个全新的重写，提供了一些相当令人印象深刻的统计数据，但兼容性较差。📊

U-Boot U-Boot 🛠️

Unfortunately, our CPU’s boot ROM can’t directly load our kernel. Linux has to be invoked in a specific way to obtain boot arguments and a pointer to the device tree and initrd, and it also expects that main memory has already been initialized.
不幸的是，我们的 CPU 引导 ROM 无法直接加载我们的内核。😞 Linux 必须以特定的方式调用，以获取引导参数和指向设备树及 initrd 的指针，同时它还期望主内存已经初始化。📦
Boot ROMs also don’t know how to initialize main memory, so we would have nowhere to store Linux. Also, boot ROMs tend to just load a few KB from flash at the most — not enough to house an entire kernel.
引导 ROM 也不知道如何初始化主存储器，所以我们没有地方存储 Linux。🖥️ 此外，引导 ROM 通常最多只从闪存加载几 KB 的数据——这不足以容纳整个内核。📦
So, we need a small program that the boot ROM can load that will initialize our main memory and then load the entire (usually-multi-megabyte) Linux kernel and then execute it.
因此，我们需要一个小程序，启动 ROM 可以加载它，以初始化我们的主存储器，然后加载整个（通常是几兆字节的）Linux 内核，并执行它。💻

The most popular bootloader for embedded systems, Das U-Boot, does all of that — but adds a ton of extra features. It has a fully interactive shell, scripting support, and USB/network booting.
最受欢迎的嵌入式系统引导加载程序，Das U-Boot，完成了所有这些 —— 但增加了大量额外功能。它拥有一个完全交互式的命令行、脚本支持和 USB/网络启动。🔧

If you’re using a tiny SPI flash chip for booting, you’ll probably store your kernel, device tree, and initrd / root filesystem at different offsets in raw flash — which U-Boot will gladly load into RAM and execute for you.
如果您正在使用一个小型的 SPI 闪存芯片进行引导，您可能会将内核、设备树和 initrd / 根文件系统存储在原始闪存中的不同偏移量处——而 U-Boot 会乐意将其加载到 RAM 中并执行。💾
But since it also has full filesystem support, so you could store your kernel and device tree as normal files on a partition of an SD card, eMMC device, or on a USB flash drive.
但是由于它也具备完整的文件系统支持，因此你可以将内核和设备树作为普通文件存储在 SD 卡的分区、eMMC 设备或 USB 闪存驱动器上。💾

U-Boot has to know a lot of technical details about your system.
U-Boot 必须了解有关您系统的许多技术细节。🖥️
There’s a dedicated board.c port for each supported platform that initializes clocks, DRAM, and relevant memory peripherals, along with initializing any important peripherals, like your UART console or a PMIC that might need to be configured properly before bringing the CPU up to full speed.
每个支持的平台都有一个专用的板级 C 端口，用于初始化时钟、DRAM 和相关的内存外设，同时还要初始化任何重要的外设，比如你的 UART 控制台或可能需要正确配置的 PMIC，以便在将 CPU 提升到全速之前做好准备。🖥️
Newer board ports often store at least some of this configuration information inside a Device Tree, which we’ll talk about later.
较新的板卡端口通常会在设备树中存储至少部分配置信息，我们稍后会讨论这个问题。🌳
Some of the DRAM configuration data is often autodetected, allowing you to change DRAM size and layout without altering the U-Boot port’s code for your processor ((If you have a DRAM layout on the margins of working, or you’re using a memory chip with very different timings than the one the port was built for, you may have to tune these values)).
一些 DRAM 配置数据通常是自动检测的，这允许您更改 DRAM 的大小和布局，而无需修改处理器的 U-Boot 端口代码。🛠️（如果您有一个工作的边缘 DRAM 布局，或者您使用的内存芯片的时序与端口构建时大相径庭，您可能需要调整这些值。）⚙️
You configure what you want U-Boot to do by writing a script that tells it which device to initialize, which file/address to load into which memory address, and what boot arguments to pass along to Linux.
您通过编写脚本来配置 U-Boot 的操作，该脚本指示它初始化哪个设备、将哪个文件/地址加载到哪个内存地址，以及将哪些引导参数传递给 Linux。🛠️
While these can be hard-coded, you’ll often store these names and addresses as environmental variables (the boot script itself can be stored as a bootcmd environmental variable). So a large part of getting U-Boot working on a new board is working out the environment.
虽然这些可以硬编码，但你通常会将这些名称和地址存储为环境变量（启动脚本本身可以存储为 bootcmd 环境变量）。因此，让 U-Boot 在新板子上工作的很大一部分是搞清楚环境。🌍

Linux Kernel Linux 内核 🐧

Here’s the headline act. Once U-Boot turns over the program counter to Linux, the kernel initializes itself, loads its own set of device drivers((Linux does not call into U-Boot drivers the way that an old PC operating system like DOS makes calls into BIOS functions.)) and other kernel modules, and calls your init program.
这里是主要内容。 一旦 U-Boot 将程序计数器转交给 Linux，内核将自我初始化，加载其自己的设备驱动程序（（Linux 并不像旧的 PC 操作系统如 DOS 那样调用 U-Boot 驱动程序，而是调用 BIOS 功能。））和其他内核模块，然后调用您的初始化程序。🖥️

To get your board working, the necessary kernel hacking will usually be limited to enabling filesystems, network features, and device drivers — but there are more advanced options to control and tune the underlying functionality of the kernel.
要让你的板子工作，所需的内核修改通常仅限于启用文件系统、网络功能和设备驱动程序——但还有更高级的选项来控制和调整内核的底层功能。🛠️

Turning drivers on and off is easy, but actually configuring these drivers is where new developers get hung up.
打开和关闭驱动程序很简单，但实际配置这些驱动程序是新开发者遇到的难点。🔧
One big difference between embedded Linux and desktop Linux is that embedded Linux systems have to manually pass the hardware configuration information to Linux through a Device Tree file or platform data C code, since we don’t have EFI or ACPI or any of that desktop stuff that lets Linux auto-discover our hardware.
嵌入式 Linux 与桌面 Linux 之间的一个主要区别是，嵌入式 Linux 系统必须通过设备树文件或平台数据 C 代码手动将硬件配置信息传递给 Linux，因为我们没有 EFI、ACPI 或任何让 Linux 自动识别硬件的桌面设备。📦

We need to tell Linux the addresses and configurations for all of our CPU’s fancy on-chip peripherals, and which kernel modules to load for each of them. You may think that’s part of the Linux port for our CPU, but in Linux’s eyes, even peripherals that are literally inside our processor — like LCD controllers, SPI interfaces, or ADCs — have nothing to do with the CPU, so they’re handled totally separately as device drivers stored in separate kernel modules.
我们需要告诉 Linux 我们所有 CPU 的高级片上外设的地址和配置，以及为它们加载哪些内核模块。💻 你可能会认为这属于我们 CPU 的 Linux 移植部分，但在 Linux 看来，即使是字面上位于我们处理器内部的外设——例如 LCD 控制器、SPI 接口或 ADC——也与 CPU 没有关系，因此它们作为设备驱动程序在单独的内核模块中完全独立处理。📦

And then there’s all the off-chip peripherals on our PCB. Sensors, displays, and basically all other non-USB devices need to be manually instantiated and configured.
另外，我们电路板上的所有外部外设也需要考虑。传感器、显示器以及基本上所有其他非 USB 设备都需要手动实例化和配置。🔌
This is how we tell Linx that there’s an MPU6050 IMU attached to I2C0 with an address of 0x68, or an OV5640 image sensor attached to a MIPI D-PHY. Many device drivers have additional configuration information, like a prescalar factor, update rate, or interrupt pin use.
这就是我们如何告诉 Linx 有一个 MPU6050 IMU 连接到 I2C0，地址为 0x68，或者连接到 MIPI D-PHY 的 OV5640 图像传感器。🔧许多设备驱动程序还有额外的配置信息，比如预分频系数、更新率或中断引脚的使用。📊

The old way of doing this was manually adding C structs to a platform_data C file for the board, but the modern way is with a Device Tree, which is a configuration file that describes every piece of hardware on the board in a weird quasi-C/JSONish syntax.
旧的方法是手动将 C 结构体添加到板子的 platform_data C 文件中，但现代方式是使用设备树，它是一个配置文件，用奇怪的类 C/JSON 语法描述板上的每个硬件。🖥️
Each logical piece of hardware is represented as a node that is nested under its parent bus/device; its node is adorned with any configuration parameters needed by the driver.
每个逻辑硬件部分都作为一个节点表示，该节点嵌套在其父总线/设备下；节点上装饰有驱动程序所需的任何配置参数。🔧

A DTS file is not compiled into the kernel, but rather, into a separate .dtb binary blob file that you have to deal with (save to your flash memory, configure u-boot to load, etc)((OK, I lied. You can actually append the DTB to the kernel so U-Boot doesn’t need to know about it.
DTS 文件并不是编译到内核中的，而是编译成一个单独的.dtb 二进制文件，这是你需要处理的（保存到你的闪存，配置 u-boot 加载等）😅（好吧，我说谎了。实际上，你可以将 DTB 附加到内核上，这样 U-Boot 就不需要知道它了。）🤫
I see this done a lot with simple systems that boot from raw Flash devices.)). I think beginners have a reason to be frustrated at this system, since there’s basically two separate places you have to think about device drivers: Kconfig and your DTS file, and if these get out of sync, it can be frustrating to diagnose, since you won’t get a compilation error if your device tree contains nodes that there are no drivers for, or if your kernel is built with a driver that isn’t actually referenced for in the DTS file, or if you misspell a property or something (since all bindings are resolved at runtime).
我看到这在从原始闪存设备启动的简单系统中经常被使用。😅 我认为初学者有理由对这一系统感到沮丧，因为基本上你需要考虑设备驱动程序的两个不同地方：Kconfig 和你的 DTS 文件。📄 如果这两个不同步，诊断起来可能会很让人头痛，因为如果你的设备树包含没有驱动程序的节点，或者你的内核是用一个在 DTS 文件中没有实际引用的驱动程序构建的，或者如果你拼写错误了某个属性之类的，你不会收到编译错误。🔍（因为所有绑定都是在运行时解析的）。

BusyBox BusyBox 📦

Once Linux has finished initializing, it runs init. This is the first userspace program invoked on start-up. Our init program will likely want to run some shell scripts, so it’d be nice to have a sh we can invoke. Those scripts might touch or echo or cat things. It looks like we’re going to need to put a lot of userspace software on our root filesystem just to get things to boot — now imagine we want to actually login (getty), list a directory (ls), configure a network (ifconfig), or edit a text file (vi, emacs, nano, vim, flamewars ensue).
一旦 Linux 完成初始化，就会运行 init。🌟 这是启动时调用的第一个用户空间程序。🚀 我们的 init 程序可能想要运行一些 shell 脚本，因此有一个可以调用的 sh 会很方便。🐚 这些脚本可能会触摸、回显或显示内容。📂 看起来我们需要在根文件系统上放置很多用户空间软件才能使系统启动——想象一下我们实际想要登录（getty）、列出目录（ls）、配置网络（ifconfig）或编辑文本文件（vi、emacs、nano、vim，随之而来的争论）。💻

Rather than compiling all of these separately, BusyBox collects small, light-weight versions of these programs (plus hundreds more) into a single source tree that we can compile and link into a single binary executable.
与其单独编译这些程序，不如让 BusyBox 将这些程序（以及其他数百个程序）的小型精简版本收集到一个单一的源代码树中，然后我们可以将其编译和链接成一个单独的可执行文件。🖥️
We then create symbolic links to BusyBox named after all these separate tools, then when we call them on the command line to start up, BusyBox determines how it was invoked and runs the appropriate command. Genius!
我们接着为 BusyBox 创建指向这些单独工具的符号链接，当我们在命令行中调用它们以启动时，BusyBox 会判断其调用方式并运行相应的命令。真是天才！🤖

BusyBox configuration is obvious and uses the same Kconfig-based system that Linux and U-Boot use. You simply tell it which packages (and options) you wish to build the binary image with.
BusyBox 的配置很简单，使用与 Linux 和 U-Boot 相同的基于 Kconfig 的系统。📦 你只需告诉它你希望使用哪些软件包（和选项）来构建二进制镜像。🔧
There’s not much else to say — though a minor “gotcha” for new users is that the lightweight versions of these tools often have fewer features and don’t always support the same syntax/arguments.
没什么好再说的——不过对于新用户来说，一个小“陷阱”是这些工具的轻量版通常功能较少，且不一定支持相同的语法/参数。🛠️

Root Filesystems 根文件系统 🗂️

Linux requires a root filesystem; it needs to know where the root filesystem is and what filesystem format it uses, and this parameter is part of its boot arguments.
Linux 需要一个根文件系统；它需要知道根文件系统的位置以及使用的文件系统格式，这个参数是其启动参数的一部分。🐧

Many simple devices don’t need to persist data across reboot cycles, so they can just copy the entire rootfs into RAM before booting (this is called initrd). But what if you want to write data back to your root filesystem? Other than MMC, all embedded flash memory is unmanaged — it is up to the host to work around bad blocks that develop over time from repeated write/erase cycles.
许多简单设备在重启周期中不需要持久化数据，因此它们可以在启动前将整个根文件系统复制到内存中（这称为 initrd）🌟。但是，如果您想将数据写回根文件系统怎么办？除了 MMC 以外，所有嵌入式闪存都是无管理的——处理坏块的工作取决于主机，这些坏块是由于重复的写入/擦除周期随着时间的推移而产生的⚙️。
Most normal filesystems are not optimized for this workload, so there are specialized filesystems that target flash memory; the three most popular are JFFS2, YAFFS2, and UBIFS. These filesystems have vastly different performance envelopes, but for what it’s worth, I generally see UBIFS deployed more on higher-end devices and YAFFS2 and JFFS2 deployed on smaller systems.
大多数普通文件系统并未针对这种工作负载进行优化，因此有专门针对闪存的文件系统；其中最受欢迎的三个是 JFFS2、YAFFS2 和 UBIFS。💾 这些文件系统的性能范围有很大差异，但就我而言，我通常看到 UBIFS 更多地部署在高端设备上，而 YAFFS2 和 JFFS2 则部署在较小的系统上。📱

MMC devices have a built-in flash memory controller that abstracts away the details of the underlying flash memory and handles bad blocks for you.
MMC 设备内置了一个闪存控制器，它能够抽象出底层闪存的细节，并为您处理坏块问题。💾
These managed flash devices are much simpler to use in designs since they use traditional partition tables and filesystems — they can be used just like the hard drives and SSDs in your PC.
这些管理

Yocto & Buildroot YOCTO 和 BUILDROOT 🛠️

If the preceding section made you dizzy, don’t worry: there’s really no reason to hand-configure and hand-compile all of that stuff individually. Instead, everyone uses build systems — the two big ones being Yocto and Buildroot — to automatically fetch and compile a full toolchain, U-Boot, Linux kernel, BusyBox, plus thousands of other packages you may wish, and install everything into a target filesystem ready to deploy to your hardware.
如果前面的内容让你感到晕眩，不用担心：其实没有必要逐个手动配置和编译那些东西。😅 相反，每个人都使用构建系统——主要的有 Yocto 和 Buildroot——来自动获取和编译完整的工具链、U-Boot、Linux 内核、BusyBox，以及你可能需要的成千上万的其他软件包，并将所有内容安装到准备好部署到硬件的目标文件系统中。💻

Even more importantly, these build systems contain default configurations for the vendor- and community-developed dev boards that we use to test out these CPUs and base our hardware from. These default configurations are a real life-saver.
更重要的是，这些构建系统包含了我们用来测试这些 CPU 并基于此构建硬件的供应商和社区开发的开发板的默认配置。 ⚙️ 这些默认配置真的是救命稻草。 🛠️

Yes, on their own, both U-Boot and Linux have defconfigs that do the heavy lifting: For example, by using a U-Boot defconfig, someone has already done the work for you in configuring U-Boot to initialize a specific boot media and boot off it (including setting up the SPL code, activating the activating the appropriate peripherals, and writing a reasonable U-Boot environment and boot script).
是的，U-Boot 和 Linux 自带的 defconfig 可以处理繁重的工作：例如，通过使用 U-Boot 的 defconfig，已经有人为您完成了配置 U-Boot 以初始化特定引导媒体并从中引导的工作（包括设置 SPL 代码、激活适当的外设以及编写合理的 U-Boot 环境和引导脚本）。✨

But the build system default configurations go a step further and integrate all these pieces together.
但是构建系统的默认配置更进一步，将所有这些组件整合在一起。🔧
For example, assume you want your system to boot off a MicroSD card, with U-Boot written directly at the beginning of the card, followed by a FAT32 partition containing your kernel and device tree, and an ext4 root filesystem partition.
例如，假设您希望您的系统从 MicroSD 卡启动，在卡的开头直接写入 U-Boot，后面是一个 FAT32 分区，包含您的内核和设备树，以及一个 ext4 根文件系统分区。📱
U-Boot’s defconfig will spit out the appropriate bin file to write to the SD card, and Linux’s defconfig will spit out the appropriate vmlinuz file, but it’s the build system itself that will create a MicroSD image, write U-Boot to it, create the partition scheme, format the filesystems, and copy the appropriate files to them.
U-Boot 的 defconfig 会输出适合写入 SD 卡的 bin 文件，而 Linux 的 defconfig 会输出适合的 vmlinuz 文件，但是真正创建 MicroSD 镜像、写入 U-Boot、创建分区方案、格式化文件系统并将适当的文件复制到它们中的，是构建系统本身。📦
Out will pop an “image.sdcard” file that you can write to a MicroSD card.
将会弹出一个“image.sdcard”文件，你可以将其写入 MicroSD 卡中。📁

Almost every commercially-available dev board has at least unofficial support in either or both Buildroot or Yocto, so you can build a functioning image with usually one or two commands.
几乎所有市面上可买到的开发板至少在 Buildroot 或 Yocto 中有非官方支持，因此你通常只需要一两条命令就能构建一个可运行的镜像。📦

These two build environments are absolutely, positively, diametrically opposed to each other in spirit, implementation, features, origin story, and industry support. Seriously, I have never found two software projects that do the same thing in such totally different ways.
这两个构建环境在精神、实现、功能、来源和行业支持上绝对、肯定、截然相反。😲 说真的，我从未见过有两个软件项目以如此完全不同的方式执行相同的任务。💻
Let’s dive in. 让我们开始吧。🌊

Buildroot Buildroot 建立环境 🛠️

Buildroot started as a bunch of Makefiles strung together to test uClibc against a pile of different commonly-used applications to help squash bugs in the library. Today, the infrastructure is the same, but it’s evolved to be the easiest way to build embedded Linux images.
Buildroot 最初是一组连接在一起的 Makefile，用于测试 uClibc 与一堆常用应用程序，以帮助修复库中的错误。🔧 今天，基础设施依然如此，但它的发展使其成为构建嵌入式 Linux 镜像的最简单方法。🛠️

By using the same Kconfig system used in Linux, U-Boot, and BusyBox, you configure everything — the target architecture, the toolchain, Linux, U-Boot, target packages, and overall system configuration — by simply running make menuconfig. It ships with tons of canned defconfigs that let you get a working image for your dev board by loading that config and running make. For example, make raspberrypi3_defconfig && make will spit out an SD card image you can use to boot your Pi off of.
通过使用与 Linux、U-Boot 和 BusyBox 相同的 Kconfig 系统，您可以通过简单地运行 make menuconfig 来配置所有内容——目标架构、工具链、Linux、U-Boot、目标软件包和整体系统配置。🛠️它附带了大量预设的 defconfig，可以让您通过加载该配置并运行 make 获得适用于开发板的工作映像。📦例如，运行 make raspberrypi3_defconfig && make 将生成一个 SD 卡映像，您可以用它来启动您的树莓派。💻

Buildroot can also pass you off to the respective Kconfigs for Linux, U-Boot, or BusyBox — for example, running make linux-menuconfig will invoke the Linux menuconfig editor from within the Buildroot directory. I think beginners will struggle to know what is a Buildroot option and what is a Linux kernel or U-Boot option, so be sure to check in different places.
Buildroot 也可以将你引导到 Linux、U-Boot 或 BusyBox 的相应 Kconfig——例如，运行 make linux-menuconfig 将从 Buildroot 目录中调用 Linux menuconfig 编辑器。🤖 我认为初学者会很难分辨什么是 Buildroot 选项，什么是 Linux 内核或 U-Boot 选项，所以一定要在不同的地方检查。📚

Buildroot is distributed as a single source tree, licensed as GPL v2. To properly add your own hardware, you’d add a defconfig file and board folder with the relevant bits in it (these can vary quite a bit, but often include U-Boot scripts, maybe some patches, or sometimes nothing at all).
Buildroot 以单一源代码树的形式发布，采用 GPL v2 许可证。🛠️ 要正确添加自己的硬件，您需要添加一个 defconfig 文件和一个包含相关内容的 board 文件夹（这些内容可能会有所不同，但通常包括 U-Boot 脚本、一些补丁，或者有时什么都没有）。📁
While they admit it is not strictly necessary, Buildroot’s documentation notes “the general view of the Buildroot developers is that you should release the Buildroot source code along with the source code of other packages when releasing a product that contains GPL-licensed software.” I know that many products (3D printers, smart thermostats, test equipment) use Buildroot, yet none of these are found in the officially supported configurations, so I can’t imagine people generally follow through with the above sentiment; the only defconfigs I see are for development boards.
虽然他们承认这并不是绝对必要的，但 Buildroot 的文档指出：“Buildroot 开发者的普遍观点是，当发布包含 GPL 许可软件的产品时，您应该与其他软件包的源代码一起发布 Buildroot 源代码。” 🤔 我知道许多产品（3D 打印机、智能恒温器、测试设备）使用 Buildroot，但这些产品在官方支持的配置中都没有看到，因此我无法想象人们通常会遵循上述观点；我看到的唯一 defconfigs 都是针对开发板的。 🛠️

And, honestly, for run-and-gun projects, you probably won’t even bother creating an official board or defconfig — you’ll just hack at the existing ones. We can do this because Buildroot is crafty in lots of good ways designed to make it easy to make stuff work.
老实说，对于快节奏的项目，你可能根本不会去创建官方电路板或配置文件——你只会直接修改现有的。我们之所以能这样做，是因为 Buildroot 在很多好的方面都很巧妙，旨在让事情变得容易。🛠️
For starters, most of the relevant settings are part of the defconfig file that can easily be modified and saved — for very simple projects, you won’t have to make further modifications.
首先，大多数相关的设置都可以在 defconfig 文件中找到，这个文件可以很容易地修改和保存——对于非常简单的项目，你不需要进行进一步的修改。📂
Think about toggling on a device driver: in Buildroot, you can invoke Linux’s menuconfig, modify things, save that config back to disk, and update your Buildroot config file to use your local Linux config, rather the one in the source tree.
考虑在设备驱动程序中切换：在 Buildroot 中，您可以调用 Linux 的 menuconfig，修改相关内容，保存配置到磁盘，并更新您的 Buildroot 配置文件以使用本地 Linux 配置，而不是源树中的配置。⚙️
Buildroot knows how to pass out-of-tree DTS files to the compiler, so you can create a fresh DTS file for your board without even having to put it in your kernel source tree or create a machine or anything. And if you do need to modify the kernel source, you can hardwire the build process to bypass the specified kernel and use an on-disk one (which is great when doing active development).
Buildroot 知道如何将树外的 DTS 文件传递给编译器，因此您可以为您的板子创建一个新的 DTS 文件，而无需将其放入内核源代码树中或创建机器或其他任何东西。🔧 如果您确实需要修改内核源代码，可以将构建过程硬编码以绕过指定的内核并使用磁盘上的内核（这在进行主动开发时非常不错）。💻

The chink in the armor is that Buildroot is brain-dead at incremental builds. For example, if you load your defconfig, make, and then add a package, you can probably just run make again and everything will work. But if you change a package option, running make won’t automatically pick that up, and if there are other packages that need to be rebuilt as a result of that upstream dependency, Buildroot won’t rebuild those either. You can use the make [package]-rebuild target, but you have to understand the dependency graph connecting your different packages. Half the time, you’ll probably just give up and do make clean && make ((Just remember to save your Linux, U-Boot, and BusyBox configuration modifications first, since they’ll get wiped out.)) and end up rebuilding everything from scratch, which, even with the compiler cache enabled, takes forever.
Buildroot 的一个弱点是它在增量构建方面非常笨拙。🛡️ 例如，如果你加载你的 defconfig，运行 make，然后添加一个包，你可以直接再次运行 make，一切将正常工作。🔄 但是如果你更改了一个包的选项，运行 make 不会自动捕捉到这一点，并且如果有其他包因为这个上游依赖关系需要重建，Buildroot 也不会重建它们。🔧 你可以使用 make [package]-rebuild 目标，但你必须理解连接你不同包的依赖图。📊 一半的时间，你可能会放弃，执行 make clean && make（记得先保存你的 Linux、U-Boot 和 BusyBox 配置修改，因为它们会被删除。）🗑️ 最终，你将从头开始重建所有内容，即使启用了编译器缓存，这也会耗费很长时间。⏳
Honestly, Buildroot is the principal reason that I upgraded to a Threadripper 3970X during this project.
老实说，Buildroot 是我在这个项目中升级到 Threadripper 3970X 的主要原因。💻

Yocto Yocto 🛠️

Yocto is totally the opposite. Buildroot was created as a scrappy project by the BusyBox/uClibc folks. Yocto is a giant industry-sponsored project with tons of different moving parts.
Yocto 完全是相反的。Buildroot 是由 BusyBox/uClibc 团队作为一个简陋项目创建的。Yocto 是一个庞大的行业赞助项目，拥有众多不同的组成部分。🐧
You will see this build system referred to as Yocto, OpenEmbedded, and Poky, and I did some reading before publishing this article because I never really understood the relationship.
您会看到这个构建系统被称为 Yocto、OpenEmbedded 和 Poky，在发布这篇文章之前我阅读了一些资料，因为我从来没有真正理解它们之间的关系。📚
I think the first is the overall head project, the second is the set of base packages, and the third is the… nope, I still don’t know. Someone complain in the comments and clarify, please.
我认为第一个是整体的主要项目，第二个是一系列基础包，第三个是……不，我还是不知道。请在评论中有人抱怨并澄清一下。🤔

Here’s what I do know: Yocto uses a Python-based build system (BitBake) that parses “recipe” files to execute tasks. Recipes can inherit from other recipes, overriding or appending tasks, variables, etc. There’s a separate “Machine” configuration system that’s closely related.
我所知道的是：Yocto 使用基于 Python 的构建系统（BitBake），它解析“配方”文件以执行任务。🍰 配方可以继承其他配方，覆盖或附加任务、变量等。🔧 还有一个与之密切相关的单独“机器”配置系统。🖥️
Recipes are grouped into categories and layers.
食谱被分为不同的类别和层次。📚

There are many layers in the official Yocto repos. Layers can be licensed and distributed separately, so many companies maintain their own “Yocto layers” (e.g., meta-atmel), and the big players actually maintain their own distribution that they build with Yocto. TI’s ProcessorSDK is built using their Arago Project infrastructure, which is built on top of Yocto. The same goes for ST’s OpenSTLinux Distribution. Even though Yocto distributors make heavy use of Google’s repo tool, getting a set of all the layers necessary to build an image can be tedious, and it’s not uncommon for me to run into strange bugs that occur when different vendors’ layers collide.
在官方的 Yocto 仓库中有许多层。🔍 这些层可以单独授权和分发，因此许多公司维护自己的“Yocto 层”（例如，meta-atmel）。🏢 大型厂商实际上维护着自己的分发版，这是他们使用 Yocto 构建的。🛠️ TI 的 ProcessorSDK 是基于他们的 Arago 项目基础设施构建的，该基础设施建立在 Yocto 之上。📦 ST 的 OpenSTLinux 分发版也是如此。🐢 尽管 Yocto 分发者大量使用 Google 的 repo 工具，但获取构建映像所需的所有层集可能是繁琐的。😓 我遇到不同厂商的层碰撞时出现奇怪的 bug 并不少见。🛑

While Buildroot uses Kconfig (allowing you to use menuconfig), Yocto uses config files spread out all over the place: you definitely need a text editor with a built-in file browser, and since everything is configuration-file-based, instead of a GUI like menuconfig, you’ll need to have constant documentation up on your screen to understand the parameter names and values.
虽然 Buildroot 使用 Kconfig（允许你使用 menuconfig），但 Yocto 使用分散在各处的配置文件：你绝对需要一个带有内置文件浏览器的文本编辑器，并且由于一切都基于配置文件，而不是像 menuconfig 这样的图形用户界面，你需要在屏幕上始终查阅文档，以理解参数名称和数值。📂
It’s an extremely steep learning curve.
这是一条极其陡峭的学习曲线。📈

However, if you just want to build an image for an existing board, things couldn’t be easier: there’s a single environmental variable, MACHINE, that you must set to match your target. Then, you BitBake the name of the image you want to build (e.g., bitbake core-image-minimal) and you’re off to the races.
然而，如果你只是想为现有的开发板构建一个镜像，那可就简单多了：你只需要设置一个环境变量，MACHINE，以匹配你的目标。然后，你使用 BitBake 命令构建你想要的镜像名称（例如，bitbake core-image-minimal），就可以开始了。🏁

But here’s where Yocto falls flat for me as a hardware person: it has absolutely no interest in helping you build images for the shiny new custom board you just made. It is not a tool for quickly hacking together a kernel/U-Boot/rootfs during the early stages of prototyping (say, during this entire blog project). It wasn’t designed for that, so architectural decisions they made ensure it will never be that. It’s written in a very software-engineery way that values encapsulation, abstraction, and generality above all else. It’s not hard-coded to know anything, so you have to modify tons of recipes and create clunky file overlays whenever you want to do even the simplest stuff.
但对于我这个硬件人员来说，Yocto 的缺点在于：它对帮助你为刚制作的光鲜新定制板构建映像完全没有兴趣。🔧 它并不是一个可以在原型早期阶段快速拼凑内核/U-Boot/rootfs 的工具（例如，在这整个博客项目中）。🛠️ 它并不是为此设计的，所以他们所做的架构决策确保它永远不会成为那样。📐 它以一种非常软件工程的方式编写，优先考虑封装、抽象和通用性。💻 它并没有硬编码来了解任何内容，因此每当你想做即使是最简单的事情时，你都必须修改大量的食谱并创建笨重的文件覆盖。📄
It doesn’t know what DTS files are, so it doesn’t have a “quick trick” to compile Linux with a custom one.
它不知道 DTS 文件是什么，所以没有快速的方法来使用自定义文件编译 Linux。💻
Even seemingly mundane things — like using menuconfig to modify your kernel’s config file and save that back somewhere so it doesn’t get wiped out — become ridiculous tasks. Just read through Section 1 of this Yocto guide to see what it takes to accomplish the equivalent of Buildroot’s make linux-savedefconfig((Alright, to be fair: many kernel recipes are set up with a hardcoded defconfig file inside the recipe folder itself, so you can often just manually copy over that file with a generated defconfig file from your kernel build directory — but this relies on your kernel recipe being set up this way)).
甚至看似平常的事情——比如使用 menuconfig 修改内核的配置文件，并将其保存到某处以防止丢失——都会变成荒谬的任务。😅 只需阅读本 Yocto 指南的第一部分，就能了解实现相当于 Buildroot 的 make linux-savedefconfig 所需的工作。📚（好吧，公平地说：许多内核配方都是在配方文件夹中设置了硬编码的 defconfig 文件，因此你通常可以直接用从内核构建目录生成的 defconfig 文件手动覆盖该文件——但这依赖于你的内核配方是如此设置的。）🔧
Instead, if I plan on having to modify kernel configurations or DTS files, I usually resort to the nuclear option: copy the entire kernel somewhere else and then set the kernel recipe’s SRC_URI to that.
相反，如果我打算修改内核配置或 DTS 文件，我通常会采取极端的做法：将整个内核复制到其他地方，然后将内核配方的 SRC_URI 设置为该位置。💻

Yocto is a great tool to use once you have a working kernel and U-Boot, and you’re focused on sculpting the rest of your rootfs.
Yocto 是一个很好的工具，一旦你有了一个工作的内核和 U-Boot，并且你专注于塑造其余的根文件系统。🛠️
Yocto is much smarter at incremental builds than Buildroot — if you change a package configuration and rebuild it, when you rebuild your image, Yocto will intelligently rebuild any other packages necessary.
Yocto 在增量构建方面比 Buildroot 聪明得多——如果你更改了一个软件包的配置并重新构建，当你重建镜像时，Yocto 会智能地重新构建任何其他必要的软件包。🔧
Yocto also lets you easily switch between machines, and organizes package builds into those specific to a machine (like the kernel), those specific to an architecture (like, say, Qt5), and those that are universal (like a PNG icon pack).
Yocto 还允许您轻松切换机器，并将软件包构建组织为特定于机器的（例如内核）、特定于架构的（例如 Qt5），以及通用的（例如 PNG 图标包）。🔄
Since it doesn’t rebuild packages unecessarily, this has the effect of letting you quickly switch between machines that share an instruction set (say ARMv7) without having to rebuild a bunch of packages.
由于它不会不必要地重新构建软件包，这使得您能够在共享指令集的机器之间（比如 ARMv7）快速切换，而无需重新构建一堆软件包。⚙️

It may not seem like a big distinction when you’re getting started, but Yocto builds a Linux distribution, while Buildroot builds a system image. Yocto knows what each software component is and how those components depend on each other.
当你刚开始的时候，这可能看起来并不是一个很大的区别，但 Yocto 构建的是一个 Linux 发行版，而 Buildroot 构建的是一个系统映像. 🖥️ Yocto 知道每个软件组件是什么，以及这些组件之间的相互依赖关系. 🔗
As a result, Yocto can build a package feed for your platform, allowing you to remotely install and update software on your embedded product just as you would a desktop or server Linux instance. That’s why Yocto thinks of itself not as a Linux distribution, but as a tool to build Linux distributions. Whether you use that feature or not is a complicated decision — I think most embedded Linux engineers prefer to do whole-image updates at once to ensure there’s no chance of something screwy going on.
因此，Yocto 可以为您的平台构建软件包源，允许您像在桌面或服务器 Linux 实例上那样，远程安装和更新嵌入式产品上的软件。🖥️ 这就是为什么 Yocto 认为自己不是一个 Linux 发行版，而是构建 Linux 发行版的工具。🔧 是否使用该功能是一个复杂的决定——我认为大多数嵌入式 Linux 工程师更喜欢一次性进行整个映像更新，以确保不会出现任何故障。⚙️
But if you’re building a huge project with a 500 MB root filesystem, pushing images like that down the tube can eat through a lot of bandwidth (and annoy customers with “Downloading….” progress bars).
但是如果你正在构建一个 500 MB 根文件系统的大型项目，像这样的推送镜像可能会消耗大量带宽（并让客户烦恼于“正在下载…….”的进度条）。📡

When I started this project, I sort of expected to bounce between Buildroot and Yocto, but I ended up using Buildroot exclusively (even though I had much more experience with Yocto), and it was definitely the right choice.
当我开始这个项目时，我原本预计会在 Buildroot 和 Yocto 之间切换，但最终我只使用了 Buildroot（尽管我对 Yocto 经验更丰富），这绝对是一个正确的选择。😊
Yes, it was ridiculous: I had 10 different processors I was building images for, so I had 10 different copies of buildroot, each configured for a separate board. I bet 90% of the binary junk in these folders was identical.
是的，这真是荒谬：我有 10 种不同的处理器在构建镜像，因此我有 10 个不同的 buildroot 副本，每个副本都是为不同的电路板配置的。我敢打赌，这些文件夹中的 90%二进制垃圾是相同的。🤦‍♂️
Yocto would have enabled me to switch between these machines quickly. In the end, though, Yocto is simply not designed to help you bring up new hardware. You can do it, but it’s much more painful.
Yocto 本可以让我快速切换这些机器。💻 但最终，Yocto 确实不是为了帮助你启动新硬件而设计的。🛠️ 你可以做到，但过程会更加痛苦。😫

The Contenders 竞争者们 🌟

I wanted to focus on entry-level CPUs — these parts tend to run at up to 1 GHz and use either in-package SDRAM or a single 16-bit-wide DDR3 SDRAM chip. These are the sorts of chips used in IoT products like upscale WiFi-enabled devices, smart home hubs, and edge gateways.
我想专注于入门级 CPU——这些部件的运行频率通常可达到 1 GHz，并使用封装内 SDRAM 或单个 16 位宽的 DDR3 SDRAM 芯片。这些是用于物联网产品的芯片，如高端 WiFi 设备、智能家居中心和边缘网关。💻
You’ll also see them in some HMI applications like high-end desktop 3D printers and test equipment.
您还会在一些人机界面（HMI）应用中看到它们，例如高端桌面 3D 打印机和测试设备。🖨️

Here’s a brief run-down of each CPU I reviewed:
这是我评测的每款 CPU 的简要介绍：📝

• Allwinner F1C200s: a 400 MHz ARM9 SIP with 64 MB (or 32 MB for the F1C100s) of DDR SDRAM, packaged in an 88-pin QFN. Suitable for basic HMI applications with a parallel LCD interface, built-in audio codec, USB port, one SDIO interface, and little else.
  全志 F1C200s：一款频率为 400 MHz 的 ARM9 SIP，配备 64 MB（或 F1C100s 的 32 MB）DDR SDRAM，封装在 88 针 QFN 中。适合基本的 HMI 应用，具有并行 LCD 接口、内置音频编码器、USB 端口、一个 SDIO 接口和较少的其他功能。📦
• Nuvoton NUC980: 300 MHz ARM9 SIP available in a variety of QFP packages and memory configurations. No RGB LCD controller, but has an oddly large number of USB ports and controls-friendly peripherals.
  Nuvoton NUC980：提供多种 QFP 封装和内存配置的 300 MHz ARM9 SIP。没有 RGB LCD 控制器，但有数量异常多的 USB 端口和友好的外设控制。🖥️
• Microchip SAM9X60 SIP: 600 MHz ARM9 SIP with up to 128 MB of SDRAM. Typical peripheral set of mainstream, industrial-friendly ARM SoCs.
  Microchip SAM9X60 SIP：600 MHz ARM9 SIP，支持高达 128 MB 的 SDRAM。典型的主流工业友好型 ARM 系统芯片外设组合。💻
• Microchip SAMA5D27 SIP: 500 MHz Cortex-A5 (the only one out there offered by a major manufacturer) with up to 256 MB of DDR2 SDRAM built-in. Tons of peripherals and smartly-multiplexed I/O pins.
  微芯科技 SAMA5D27 SIP：500 MHz Cortex-A5（目前唯一一家主要制造商提供的），内置高达 256 MB 的 DDR2 SDRAM。拥有大量外设和智能复用的 I/O 引脚。🖥️
• Allwinner V3s: 1 GHz Cortex-A7 in a SIP with 64 MB of RAM. Has the same fixings as the F1C200s, plus an extra SDIO interface and, most unusually, a built-in Ethernet PHY — all packaged in a 128-pin QFP.
  全志 V3s：1 GHz Cortex-A7 集成电路，配备 64 MB 内存。具有与 F1C200s 相同的固定装置，此外还有一个额外的 SDIO 接口，最特别的是内置以太网物理层 — 所有这一切都包装在一个 128 针的 QFP 中。🔧
• Allwinner A33: Quad-core 1.2 GHz Cortex-A9 with an integrated GPU, plus support for driving MIPI and LVDS displays directly. Strangely, no Ethernet support.
  全志 A33：四核 1.2 GHz Cortex-A9，配备集成 GPU，支持直接驱动 MIPI 和 LVDS 显示器。奇怪的是，竟然没有以太网支持。🖥️
• NXP i.MX 6ULx: Large cohort of mainstream Cortex-A7 chips available with tons of speed grades up to 900 MHz and typical peripheral permutations across the UL, ULL, and ULZ subfamilies.
  NXP i.MX 6ULx：大规模的主流 Cortex-A7 芯片，可提供多种速度等级，最高可达 900 MHz，并具有 UL、ULL 和 ULZ 子系列的典型外设组合。 🚀
• Texas Instruments Sitara AM335x and AMIC110: Wide-reaching family of 300-1000 MHz Cortex-A7 parts with typical peripherals, save for the integrated GPU found on the highest-end parts.
  德州仪器 Sitara AM335x 和 AMIC110：广泛的 300-1000 MHz Cortex-A7 系列，配备典型的外设，最高端的部件上集成了 GPU。🎉
• STMicroelectronics STM32MP1: New for this year, a family of Cortex-A7 parts sporting up to dual 800 MHz cores with an additional 200 MHz Cortex-M4 and GPU acceleration. Features a controls-heavy peripheral set and MIPI display support.
  STMicroelectronics STM32MP1：今年推出的新系列，采用最高双 800 MHz 核心的 Cortex-A7 部件，另外还配备 200 MHz 的 Cortex-M4 和 GPU 加速。🌟 具备大量控制功能的外设集和 MIPI 显示支持。🖥️
• Rockchip RK3308: A quad-core 1.3 GHz Cortex-A35 that’s a much newer design than any of the other parts reviewed. Tailor-made for smart speakers, this part has enough peripherals to cover general embedded Linux work while being one of the easiest Rockchip parts to design around.
  Rockchip RK3308：一款四核 1.3 GHz Cortex-A35，比其他评测过的部件设计更新。这款专为智能音箱量身定制的处理器，拥有足够的外设支持常规的嵌入式 Linux 工作，同时也是最容易设计的 Rockchip 部件之一。🎤

From the above list, it’s easy to see that even in this “entry level” category, there’s tons of variation — from 64-pin ARM9s running at 300 MHz, all the way up to multi-core chips with GPU acceleration stuffed in BGA packages that have 300 pins or more.
从上述列表中可以很容易看出，即使在这个“入门级”类别中，也有许多变化——从运行在 300 MHz 的 64 引脚 ARM9，到多核芯片和 GPU 加速的 BGA 封装，具有 300 引脚或更多。📦

The Microchip, NXP, ST, and TI parts are what I would consider general-purpose MPUs: designed to drop into a wide variety of industrial and consumer connectivity, control, and graphical applications.
我认为 Microchip、NXP、ST 和 TI 的芯片是通用微处理器：旨在用于各种工业和消费连接、控制和图形应用中。💻
They have 10/100 ethernet MACs (obviously requiring external PHYs to use), a parallel RGB LCD interface, a parallel camera sensor interface, two SDIO interfaces (typically one used for storage and the other for WiFi), and up to a dozen each of UARTs, SPI, I2C, and I2S interfaces.
它们具有 10/100 以太网 MAC（显然需要外部 PHY 使用）、并行 RGB LCD 接口、并行摄像头传感器接口、两个 SDIO 接口（通常一个用于存储，另一个用于 WiFi），以及多达十个 UART、SPI、I2C 和 I2S 接口。🌐
They often have extensive timers and a dozen or so ADC channels. These parts are also packaged in large BGAs that ball-out 100 or more I/O pins that enable you to build larger, more complicated systems.
它们通常具有广泛的计时器和十多个 ADC 通道。🔧 这些部件还包装在大型 BGA 中，提供 100 个或更多 I/O 引脚，使您能够构建更大、更复杂的系统。🔗

The Nuvoton NUC980 has many of the same features of these general-purpose MPUs (in terms of communication peripherals, timers, and ADC channels), but it leans heavily toward IoT applications: it lacks a parallel RGB interface, its SDK targets booting off small and slow SPI flash, and it’s….
Nuvoton NUC980 具有许多通用 MPU 的相似功能（在通信外设、计时器和 ADC 通道方面），但它在物联网应用方面倾向明显：它缺少并行 RGB 接口，其 SDK 主要支持从小而慢的 SPI 闪存启动，并且它…💡
well… just plain slow.
嗯……就是很慢。🐢

On the other hand, the Allwinner and Rockchip parts are much more purpose-built for consumer goods — usually very specific consumer goods. With a built-in Ethernet PHY and a parallel and MIPI camera interface, the V3s is obviously designed as an IP camera. The F1C100s — a part with no Ethernet but with a hardware video decoder — is built for low-cost video playback applications.
另一方面，Allwinner 和 Rockchip 的芯片更专门针对消费品——通常是非常特定的消费品。📱 V3s 显然是作为 IP 摄像头设计的，配备了内置的以太网 PHY 和并行及 MIPI 摄像头接口。📷 F1C100s 则是一款没有以太网但具有硬件视频解码器的芯片，专为低成本视频播放应用而开发。💻
The A33 — with LVDS / MIPI display support, GPU acceleration, and no Ethernet — is for entry-level Android tablets.
A33——支持 LVDS / MIPI 显示，具备 GPU 加速且无以太网——适用于入门级 Android 平板电脑。📱
None of these parts have more than a couple UART, I2C, or SPI interfaces, and you might get a single ADC input and PWM channel on them, with no real timer resources available.
这些部件都不超过几个 UART、I2C 或 SPI 接口，您可能仅能获得一个 ADC 输入和 PWM 通道，而没有实际可用的定时器资源。🔧
But they all have built-in audio codecs — a feature not found anywhere else — along with hardware video decoding (and, in some cases, encoding).
但它们都具备内置音频编解码器——这一功能在其他地方找不到——以及硬件视频解码（在某些情况下，还有编码）。🎶
Unfortunately, with Allwinner, you always have to put a big asterisk by these hardware peripherals, since many of them will only work when using the old kernel that Allwinner distributes — along with proprietary media encoding/decoding libraries.
不幸的是，对于全志科技，你总是需要对这些硬件外设加上一个大星号，因为其中许多只有在使用全志科技分发的旧内核时才能工作——以及与之配套的专有媒体编码/解码库。⭐️
Mainline Linux support will be discussed more for each part separately.
主线 Linux 支持将针对每个部分单独进行讨论。💻

Invasion of the SIPs SIP 的侵袭 🌐

From a hardware design perspective, one of the takeaways from this article should be that SIPs — System-in-Package ICs that bundle an application processor along with SDRAM in a single chip — are becoming commonplace, even in relatively high-volume applications.
从硬件设计的角度看，这篇文章的一个要点是，系统级封装（SIPs）——将应用处理器与 SDRAM 集成在单一芯片中的集成电路——正变得越来越普遍，甚至在相对高容量的应用中也是如此。📦
There are two main advantages when using SIPs:
使用 SIP 的主要有两个优点：😊

• Since the DDR SDRAM is integrated into the chip itself, it’s a bit quicker and easier to route the PCB, and you can use crappier PCB design software without having to bend over backward too much.
  由于 DDR SDRAM 集成在芯片内部，因此布线 PCB 会更快、更容易，并且可以使用较低质量的 PCB 设计软件，而不必过于费力。⚡
• These chips can dramatically reduce the size of your PCB, allowing you to squeeze Linux into smaller form factors.
  这些芯片可以显著减少电路板的尺寸，让你能够将 Linux 嵌入更小的形态中。📏

SIPs look extremely attractive if you’re just building simple CPU break-out boards, since DDR routing will take up a large percentage of the design time.
如果你只是构建简单的 CPU 接入板，SIP 看起来非常吸引人，因为 DDR 布线将占用设计时间的很大一部分。💻

But if you’re building real products that harness the capabilities of these processors — with high-resolution displays, image sensors, tons of I2C devices, sensitive analog circuitry, power/battery management, and application-specific design work — the relative time it takes to route a DDR memory bus starts to shrink to the point where it becomes negligible.
但是，如果你正在构建真正的产品，利用这些处理器的能力——配备高分辨率显示屏、图像传感器、大量 I2C 设备、灵敏的模拟电路、能源/电池管理以及特定应用的设计工作——那么布线 DDR 内存总线所需的相对时间就会逐渐缩小到可以忽略不计的程度。🚀

Also, as much as SIPs make things easier, most CPUs are not available in SIP packages and the ones that are usually ask a higher price than buying the CPU and RAM separately.
Also, many SIP-enabled processors top out at 128-256 MB of RAM, which may not be enough for your application, while the regular ol’ processors reviewed here can address up to either 1 or 2 GB of external DDR3 memory.
此外，许多支持 SIP 的处理器最大只能支持 128-256 MB 的 RAM，这可能不足以满足您的应用需求，而这里评测的普通处理器则可以访问多达 1 或 2 GB 的外部 DDR3 内存。💻

Nuvoton NUC980 NUVOTON NUC980 🖥️

The Nuvoton NUC980 is a new 300 MHz ARM9-based SIP with 64 or 128 MB of SDRAM memory built-in. The entry-level chip in this family is $4.80 in quantities of 100, making it one of the cheapest SIPs available. Plus, Nuvoton does 90% discounts on the first five pieces you buy when purchased through TechDesign, so you can get a set of chips for your prototype for a couple of bucks.
Nuvoton NUC980 是一款新的 300 MHz ARM9 架构的 SIP，内置 64 或 128 MB 的 SDRAM 内存。💻 这款系列的入门级芯片在购买 100 个时定价为 4.80 美元，使其成为市场上最便宜的 SIP 之一。💰 此外，当通过 TechDesign 购买时，Nuvoton 在前五个购买时提供 90% 的折扣，因此您可以花几美元就能为您的原型获取一套芯片。💵

This part sort of looks like something you’d find from one of the more mainstream application processor vendors: the full-sized version of this chip has two SDIO interfaces, dual ethernet MACs, dual camera sensor interfaces, two USB ports, four CAN buses, eight channels of 16-bit PWM (with motor-friendly complementary drive support), six 32-bit timers with all the capture/compare features you’d imagine, 12-bit ADC with 8 channels, 10 UARTs, 4 I2Cs, 2 SPIs, and 1 I2S — as well as a NAND flash and external bus interface.
这个部分看起来有点像你会在一些主流应用处理器供应商那里找到的东西：这个芯片的全尺寸版本有两个 SDIO 接口、双以太网 MAC、双摄像头传感器接口、两个 USB 端口、四个 CAN 总线、八个 16 位 PWM 通道（支持友好的电机互补驱动）、六个 32 位定时器，具有你能想象的所有捕获/比较功能、12 位 ADC，8 个通道、10 个 UART、4 个 I2C、2 个 SPI 和 1 个 I2S——以及一个 NAND 闪存和外部总线接口。🔧

But, being Nuvoton, this chip has some (mostly good) weirdness up its sleeve. Unlike the other mainstream parts that were packaged in ~270 ball BGAs, the NUC980 comes in 216-pin, 128-pin, and even 64-pin QFP packages.
但是，作为 Nuvoton，这款芯片有一些（大多是好的）奇特之处 🤔。与其他主流芯片采用约 270 球 BGA 封装不同，NUC980 提供 216 引脚、128 引脚，甚至 64 引脚的 QFP 封装 ☑️。
I’ve never had issues hand-placing 0.8mm pitch BGAs, but there’s definitely a delight that comes from running Linux on something that looks like it could be a little Cortex-M microcontroller.
我从未在手工放置 0.8mm 引脚间距的 BGA 时遇到过问题，但在看起来像是一个小型 Cortex-M 微控制器的设备上运行 Linux，确实会带来一种乐趣。 😊

Another weird feature of this chip is that in addition to the 2 USB high-speed ports, there are 6 additional “host lite” ports that run at full speed (12 Mbps). Nuvoton says they’re designed to be used with cables shorter than 1m.
这个芯片的另一个奇特之处在于，除了两个高速 USB 端口外，还有六个额外的“主机轻量”端口，它们以全速（12 Mbps）运行。Nuvoton 表示，这些端口旨在与长度小于 1 米的电缆配合使用。🔌
My guess is that these are basically full-speed USB controllers that just use normal GPIO cells instead of fancy-schmancy analog-domain drivers with controlled output impedance, slew rate control, true differential inputs, and all that stuff.
我的猜测是，这些基本上是全速 USB 控制器，只是使用普通的 GPIO 单元，而不是那些 fancy-schmancy 的模拟域驱动，带有受控输出阻抗、上升时间控制、真正的差分输入以及所有那些东西。🔌

Honestly, the only peripheral omission of note is the lack of a parallel RGB LCD controller. Nuvoton is clearly signaling that this part is designed for IoT gateway and industrial networked applications, not HMI.
老实说，唯一值得注意的外
That’s unfortunate since a 300-MHz ARM9 is plenty capable of running basic GUIs. The biggest hurdle would be finding a place to stash a large GUI framework inside the limited SPI flash these devices usually boot from.
这很不幸，因为 300-MHz 的 ARM9 足以运行基本的图形用户界面。😔 最大的障碍是找到一个地方在这些设备通常从中引导的有限 SPI 闪存内存储一个大型 GUI 框架。📦

There’s also an issue with using these for IoT applications: the part offers no secure boot capabilities.
在将这些用于物联网应用时还有一个问题：该组件不提供安全启动功能。🔒
That means people will be able to read out your system image straight from SPI flash and pump out clones of your device — or reflash it with alternative firmware if they have physical access to the SPI flash chip.
这意味着人们将能够直接从 SPI 闪存读取你的系统映像，并复制你的设备——或者如果他们可以物理接触到 SPI 闪存芯片，还可以重新闪存成替代的固件。📡
You can still distribute digitally-signed firmware updates, which would allow you to verify a firmware image before reflashing it, but if physical device security is a concern, you’ll want to move along.
您仍然可以分发数字签名的固件更新，这将允许您在重新闪存之前验证固件映像，但如果物理设备安全是一个问题，您可能需要继续前进。🔒

Hardware Design 硬件设计 🖥️

For reference hardware, Nuvoton has three official (and low-cost) dev boards. The $60 NuMaker-Server-NUC980 is the most featureful; it breaks out both ethernet ports and showcases the chip as a sort of Ethernet-to-RS232 bridge. I purchased the $50 NuMaker-IIoT-NUC980, which had only one ethernet port but used SPI NAND flash instead of NOR flash. They have a newer $30 NuMaker-Tomato board that seems very similar to the IoT dev board. I noticed they posted schematics for a reference design labeled “NuMaker-Chili” which appears to showcase the diminutive 64-pin version of the NUC980, but I’m not sure if or when this board will ship.
作为参考硬件，Nuvoton 提供了三款官方（且低成本）的开发板。💻 价格为 60 美元的 NuMaker-Server-NUC980 是功能最全面的；它将两个以太网端口实现分离，并展示了该芯片作为一种以太网到 RS232 的桥接器。🌉 我购买了 50 美元的 NuMaker-IIoT-NUC980，它只有一个以太网端口，但使用的是 SPI NAND 闪存，而不是 NOR 闪存。💾 他们还有一款新的 30 美元的 NuMaker-Tomato 开发板，看起来非常类似于物联网开发板。📡 我注意到他们发布了一个标记为“NuMaker-Chili”的参考设计的原理图，这似乎展示了 NUC980 的迷你 64 针版本，但我不确定这款板子是否会发货或何时发货。🕒

Speaking of that 64-pin chip, I wanted to try out that version for myself, just for the sake of novelty (and to see how the low-pin-count limitations affected things). Nuvoton provides excellent hardware documentation for the NUC980 series, including schematics for their reference designs, as well as a NUC980 Series Hardware Design Guide that contains both guidelines and snippets to help you out.
谈到那款 64 针的芯片，我想自己试试那个版本，纯粹是出于新奇（还想看看低引脚数量的限制如何影响各方面）。新唐科技为 NUC980 系列提供了优秀的硬件文档，包括参考设计的原理图，以及包含指导方针和代码片段的 NUC980 系列硬件设计指南，以帮助你。🔍

Nuvoton has since uploaded design examples for their 64-pin NUC980, but this documentation didn’t exist when I was working on my break-out board for this review, so I had to make some discoveries on my own: because only a few of the boot selection pins were brought out, I realized I was stuck booting from SPI NOR Flash memory, which gets very expensive above 16 or 32 MB (also, be prepared for horridly slow write speeds).
自那以来，Nuvoton 已上传了他们的 64 引脚 NUC980 的设计示例，但在我为这次评测制作开发板时，这些文档并不存在，因此我不得不自己做一些发现：因为只有少数引导选择引脚被引出，我意识到我只能从 SPI NOR Flash 存储器引导，这在超过 16 或 32 MB 后变得非常昂贵（而且，请准备好经历极其缓慢的写入速度）。💡

Regarding booting: there are 10 boot configuration signals, labeled Power-On Setting in the datasheet. Luckily, these are internally pulled-up with sensible defaults, but I still wish most of these were determined automatically based on probing.
关于引导：有 10 个引导配置信号，在数据表中标记为电源设置。幸运的是，这些信号内部有上拉电阻并且有合理的默认值，但我仍然希望大多数信号能基于探测自动确定。🔌
I don’t mind having two pins to determine the boot source, but it should not be necessary to specify whether you’re using SPI NAND or NOR flash memory since you can detect this in software, and there’s no reason to have a bus width setting or speed setting specified — the boot ROM should just operate at the slowest speed, since the bootloader will hand things over to u-boot’s SPL very quickly, which can use a faster clock or wider bus to load stuff.
我不介意有两个引脚来确定启动源，但不应该有必要指定你是使用 SPI NAND 还是 NOR 闪存，因为可以在软件中检测到这一点，并且没有理由需要指定总线宽度设置或速度设置——启动 ROM 应该只在最慢的速度下运行，因为启动加载程序会很快将事情交给 u-boot 的 SPL，它可以使用更快的时钟或更宽的总线来加载东西。💾

Other than the MPU and the SPI flash chip, you’ll need a 12 MHz crystal, a 12.1k USB bias resistor, a pull-up on reset, and probably a USB port (so you can reprogram the SPI flash in-circuit using the built-in USB bootloader on the NUC980).
除了 MPU 和 SPI 闪存芯片，你还需要一个 12 MHz 的晶振，一个 12.1k 的 USB 偏置电阻，一个重置上的上拉电阻，可能还需要一个 USB 端口（这样你可以使用 NUC980 上的内置 USB 引导程序在电路中重新编程 SPI 闪存）。🔧
Sprinkle in some decoupling caps to keep things happy, and that’s all there is to it. The chip even uses an internal VDD/2 VREF source for the on-chip DDR, so there’s no external voltage divider necessary.
在电路中添加一些解耦电容，以确保电子元件的稳定运行，这就是所有需要做的。该芯片甚至使用内部的 VDD/2 VREF 源为片上 DDR 提供电压，因此不需要外部电压分压器。🛠️

For power, you’ll need 1.2, 1.8, and 3.3 V supplies — I used a fixed-output 3.3V linear regulator, as well as a dual-channel fixed-output 1.2/1.8V regulator. According to the datasheet, the 1.2V core draws 132 mA, and the 1.8V memory supply tops out at 44 mA.
对于电源，您需要 1.2V、1.8V 和 3.3V 的电源——我使用了一个固定输出的 3.3V 线性稳压器，以及一个双通道的固定输出 1.2/1.8V 稳压器。📦 根据数据手册，1.2V 核心的电流为 132 mA，而 1.8V 内存电源最大为 44 mA。🔋
The 3.3V supply draws about 85 mA.
3.3V 电源约消耗 85 毫安。⚡️

Once you have everything wired up, you’ll realize only 35 pins are left for your I/O needs.
一旦你完成了所有连接，你会发现只剩下 35 个接口引脚用于输入输出需求。🔌
Signals are multiplexed OK, but not great: SDHC0 is missing a few pins and SDHC1 pins are multiplexed with the Ethernet, so if you want to do a design with both WiFi and Ethernet, you’ll need to operate your SDIO-based wifi chip in legacy SPI mode.
信号复用还可以，但不是很好：SDHC0 缺少几个引脚，而 SDHC1 的引脚与以太网复用，因此如果你想要一个同时支持 WiFi 和以太网的设计，你需要在传统 SPI 模式下操作基于 SDIO 的 WiFi 芯片。📡

The second USB High-Speed port isn’t available on the 64-pin package, so I wired up a USB port to one of the full-speed “Host Lite” interfaces mentioned previously.
第二个 USB 高速端口在 64 针封装上是不可用的，所以我将一个 USB 端口连接到之前提到的一个全速“Host Lite”接口上。🔌
I should have actually read the Hardware Design Guide instead of just skimming through it since it clearly shows that you need external pull-down resistors on the data pins (along with series-termination resistors that I wasn’t too worried about) — this further confirms my suspicion that these Host Lite ports just use normal I/O cells.
我实际上应该仔细阅读硬件设计指南，而不是仅仅浏览一下，因为它明确指出数据引脚上需要外部下拉电阻（还有我并不太担心的串联终端电阻）—— 这进一步证实了我对这些 Host Lite 端口只是使用普通 I/O 单元的怀疑。💡
Anyway, this turned out to be the only bodge I needed to do on my board.
无论如何，这证明它是我在电路板上需要做的唯一修补。🔧

On the 64-pin package, even with the Ethernet and Camera sensor allocated, you’ll still get an I2C bus, an I2S interface, and an application UART (plus the UART0 used for debugging), which seems reasonable.
在这个 64 引脚的封装中，即使分配了以太网和摄像头传感器，你仍然会得到一个 I2C 总线，一个 I2S 接口，以及一个应用 UART（加上用于调试的 UART0），这似乎是合理的。🌟
One thing to note: there’s no RTC oscillator available on the 64-pin package, so I wouldn’t plan on doing time-keeping on this (unless I had an NTP connection).
需要注意的一点是：64 引脚封装上没有 RTC 振荡器，因此我不打算在此进行时间保持（除非我有 NTP 连接）。🕒

If you jump to the 14x14mm 0.4mm-pitch 128-pin version of the chip, you’ll get 87 I/O, which includes a second ethernet port, a second camera port, and a second SDHC port.
如果你跳到 14x14mm 0.4mm 脚距 128 引脚版本的芯片，你将获得 87 个 I/O，其中包括第二个以太网端口、第二个相机端口和第二个 SDHC 端口。✨
If you move up to the 216-pin LQFP, you’ll get 100 I/O — none of which nets you anything other than a few more UARTs/I2Cs/SPIs, at the expense of trying to figure out where to cram in a 24x24mm chip on your board.
如果你升级到 216 引脚的 LQFP，你将获得 100 个 I/O——这些 I/O 除了多几个 UART/I2C/SPI 之外，并没有带来其他好处，但你得费心思去想怎么把一个 24x24mm 的芯片塞进你的电路板上。🛠️

Software 软件 🖥️

The NUC980 BSP seems to be built and documented for people who don’t know anything about embedded Linux development.
NUC980 BSP 似乎是为那些对嵌入式 Linux 开发一无所知的人构建和文档化的。😊
The NUC980 Linux BSP User Manual assumes your main system is a Windows PC, and politely walks you through installing the “free” VMWare Player, creating a CentOS-based virtual machine, and configuring it with the missing packages necessary for cross-compilation.
NUC980 Linux BSP 用户手册假设您的主要系统是 Windows PC，并礼貌地指导您安装“免费”的 VMWare Player，创建一个基于 CentOS 的虚拟机，并配置缺少的跨编译所需的软件包。💻

Interestingly, the original version of NuWriter — the tool you’ll use to flash your image to your SPI flash chip using the USB bootloader of the chip — is a Windows application.
有趣的是，NuWriter 的原始版本——您将使用它通过芯片的 USB 引导加载程序将映像刷写到 SPI 闪存芯片——是一个 Windows 应用程序。💻
They have a newer command-line utility that runs under Linux, but this should illustrate where these folks are coming from.
他们有一个在 Linux 下运行的新命令行工具，但这应该能说明这些人的出发点。💻

They have a custom version of Buildroot, but they also have an interesting BSP installer that will get you a prebuilt kernel, u-boot, and rootfs you can start using immediately if you’re just interested in writing applications.
他们有一个定制版本的 Buildroot，但他们还有一个有趣的 BSP 安装程序，可以让你获得一个预构建的内核、u-boot 和根文件系统，如果你只是想编写应用程序，可以立即开始使用。💻
Nuvoton also includes small application examples for CAN, ALSA, SPI, I2C, UART, camera, and external memory bus, so if you’re new to embedded Linux, you won’t have to run all over the Internet as much, searching for spidev demo code, for example.
Nuvoton 还包含了 CAN、

Instead of using the more-standard Device Tree system for peripheral configuration, by default Nuvoton has a funky menuconfig-based mechanism.
默认情况下，Nuvoton 使用一种基于 menuconfig 的独特机制，而不是使用更标准的设备树系统进行外设配置。🌟

For seasoned Linux developers, things get a bit weird when you start pulling back the covers.
对于经验丰富的 Linux 开发者来说，当你开始揭开真相时，事情就有点奇怪了。🧐
Instead of using a Device Tree, they actually use old-school platform configuration data by default (though they provide a device tree file, and it’s relatively straightforward to configure Linux to just append the DTB blob to the kernel so you don’t have to rework all your bootloader stuff).
他们实际上默认使用的是传统平台配置数据，而不是使用设备树（尽管他们提供了设备树文件，而且相对简单地配置 Linux 以便将 DTB 二进制大块追加到内核中，这样你就不必重新处理所有的引导加载程序设置）。📦

The platform configuration code is interesting because they’ve set it up so that much of it is actually configured using Kconfig; you can enable and disable peripherals, configure their options, and adjust their pinmux settings all interactively through menuconfig.
平台配置代码很有趣，因为它们已设置为大部分内容实际上是通过 Kconfig 配置的；你可以通过 menuconfig 交互式地启用和禁用外设，配置它们的选项，并调整它们的引脚复用设置。🛠️
To new developers, this is a much softer learning curve than rummaging through two or three layers of DTS include files to try to figure out a node setting to override.
对于新的开发者来说，这比翻阅两到三个层次的 DTS 包含文件来试图弄清楚一个节点设置以进行覆盖要容易得多。📚

The deal-breaker for a lot of people is that the NUC980 has no mainline support — and no apparent plans to try to upstream their work. Instead, Nuvoton distributes a 4.4-series kernel with patches to support the NUC980. The Civil Infrastructure Platform (CIP) project plans to maintain this version of the kernel for a minimum of 10 years — until at least 2026.
对很多人来说，问题的关键在于 NUC980 没有主线支持——并且似乎没有计划将他们的工作上游化。☹️ 相反，Nuvoton 分发了一个 4.4 系列内核，并附加了补丁以支持 NUC980。🛠️ 市政基础设施平台（CIP）项目计划将这一版本的内核维护至少 10 年——直到至少 2026 年。📆
It looks like Nuvoton occasionally pulls patches in from upstream, but if there’s something broken (or a vulnerability), you might have to ask Nuvoton to pull it in (or do it yourself).
看起来 Nuvoton 会偶尔从上游引入补丁，但如果有一些问题（或漏洞），您可能需要请求 Nuvoton 引入这些补丁（或者自己去做）。🔧

I had issues getting their Buildroot environment working, simply because it was so old — they’re using version 2016.11.1. There were a few host build tools on my Mint 19 VM that were “too new” and had minor incompatibilities, but after posting issues on GitHub, the Nuvoton engineer who maintains the repo fixed things.
我在使用他们的 Buildroot 环境时遇到了问题，因为它实在太旧了——他们使用的是 2016.11.1 版本。我的 Mint 19 虚拟机上有几个主机构建工具“太新”，导致了轻微的不兼容，但是在 GitHub 上发布了问题后，维护该仓库的 Nuvoton 工程师修复了这些问题。🛠️

Here’s a big problem Nuvoton needs to fix: by default, Nuvoton’s BSP is set up to boot from an SPI flash chip with a simple initrd filesystem appended to the uImage that’s loaded into RAM.
这里有一个 Nuvoton 需要解决的大问题：默认情况下，Nuvoton 的 BSP 设置为从 SPI 闪存芯片引导，并附加一个简单的 initrd 文件系统到加载到 RAM 中的 uImage。🚀
This is a sensible configuration for a production application, but it’s definitely a premature optimization that makes development challenging — any modifications you make to files will be wiped away on reboot (there’s nothing more exciting than watching sshd generate a new keypair on a 300 MHz ARM9 every time you reboot your board).
这是一个适合生产应用的合理配置，但这绝对是一种过早的优化，会使开发变得困难——任何对文件的修改在重启时都会被清除（没有什么比在每次重启你的板子时观察 sshd 在 300 MHz ARM9 上生成新的密钥对更让人兴奋的了）。🔧
Furthermore, I discovered that if the rootfs started getting “too big” Linux would fail to boot altogether.
此外，我发现如果 rootfs 变得“太大”，Linux 会完全无法启动。🖥️

Instead, the default configuration should store the rootfs on a proper flash filesystem (like YAFFS2), mounted read-write.
相反，默认配置应该将根文件系统存储在一个合适的闪存文件系统上（如 YAFFS2），以读写方式挂载。💾
Nuvoton doesn’t provide a separate Buildroot defconfig for this, and for beginners (heck, even for me), it’s challenging to switch the system over to this boot strategy, since it involves changing literally everything — the rootfs image that Buildroot generates, the USB flash tool’s configuration file, U-Boot’s bootcmd, and Linux’s Kconfig.
Nuvoton 并未为此提供单独的 Buildroot defconfig，对于初学者（甚至对我来说也是），将系统切换到这种启动策略是具有挑战性的，因为这涉及到改变几乎所有的东西——Buildroot 生成的根文件系统镜像、USB 闪存工具的配置文件、U-Boot 的 bootcmd，以及 Linux 的 Kconfig。🛠️

Even with the initrd system, I had to make a minor change to U-boot’s Kconfig, since by default, the NUC980 uses the QSPI peripheral in quad mode, but my 64-pin chip didn’t have the two additional pins broken out, so I had to operate it in normal SPI mode.
即使使用 initrd 系统，我仍然需要对 U-boot 的 Kconfig 进行一些小改动，因为默认情况下，NUC980 在四线模式下使用 QSPI 外设，但我的 64 引脚芯片没有额外的两个引脚，因此我不得不以普通 SPI 模式运行它。⚙️
They now have a “chilli” defconfig that handles this.
他们现在有一个“chilli”默认配置来处理这个。🌶️

In terms of support, Nuvoton’s forum looks promising, but the first time you post, you’ll get a notice that your message will need administrative approval. That seems reasonable for a new user, but you’ll notice that all subsequent posts also require approval, too. This makes the forum unusable — instead of serving as a resource for users to help each other out, it’s more or less an area for product managers to shill about new product announcements.
在支持方面，Nuvoton 的论坛看起来很有前景，但你第一次发帖时，会收到一条通知，称你的信息需要管理员批准。🛠️ 对于新用户来说，这似乎是合理的，但你会注意到所有后续的帖子也需要批准。📜 这使得论坛变得无法使用——它不仅不能作为用户互相帮助的资源，反而更像是产品经理宣传新产品发布的区域。📢

Instead, go straight to the source — when I had problems, I just filed issues on the GitHub repos for the respective tools I used (Linux, U-Boot, BuildRoot, NUC980 Flasher).
相反，直接去源头——当我遇到问题时，我只是对我使用的相应工具（Linux、U-Boot、BuildRoot、NUC980 Flasher）的 GitHub 仓库提交了问题反馈。🛠️
Nuvoton engineer Yi-An Chen and I kind of had a thing for a while where I’d post an issue, go to bed, and when I’d wake up, he had fixed it and pushed his changes back into master. Finally, the time difference between the U.S. and China comes in handy!
Nuvoton 工程师陈奕安和我之前有一段时间的默契，我会发布一个问题，去睡觉，等我醒来时，他已经修复了它并将更改推回主分支。 这真是美中不足的时差优势！⏰

Allwinner F1C100s / F1C200s
全 Winner F1C100S / F1C200S 🖥️

The F1C100s and F1C200s are identical ARM9 SIP processors with either 32 MB (F1C100s) or 64 MB (F1C200s) SDRAM built-in. They nominally run at 400 MHz but will run reliably at 600 MHz or more.
F1C100s 和 F1C200s 是相同的 ARM9 系统级芯片处理器，内置 32 MB（F1C100s）或 64 MB（F1C200s）SDRAM。它们名义上运行在 400 MHz，但在 600 MHz 或更高频率下可靠运行。💻

These parts are built for low-cost AV playback and feature a 24-bit LCD interface (which can also be multiplexed to form an 18-bit LCD / 8-bit camera interface), built-in audio codec, and analog composite video in/out.
这些组件是为低成本音视频播放而设计的，配备了 24 位 LCD 接口（也可以复用形成 18 位 LCD / 8 位摄像头接口）、内置音频编码器和模拟复合视频输入/输出。🎥
There’s an H.264 video decoder that you’ll need to be able to use this chip for video playback.
这个芯片需要一个 H.264 视频解码器才能进行视频播放。🎥
Just like with the A33, the F1C100s has some amazing multimedia hardware that’s bogged down by software issues with Allwinner — the company isn’t set up for typical Yocto/Buildroot-based open-source development.
就像 A33 一样，F1C100s 拥有一些出色的多媒体硬件，但却因为 Allwinner 的软件问题而受到影响——该公司并不适合进行典型的基于 Yocto/Buildroot 的开源开发。🎥
The parallel LCD interface and audio codec are the only two of these peripherals that have mainline Linux support; everything else only currently works with the proprietary Melis operating system Allwinner distributes, possibly an ancient 3.4-series kernel they have kicking around, along with their proprietary CedarX software (though there is an open-source effort that’s making good progress, and will likely end up supporting the F1C100s and F1C200s).
并行 LCD 接口和音频编解码器是这两个外设中唯一有主线 Linux 支持的；其余的目前仅与全志分发的专有 Melis 操作系统兼容，可能还在使用他们手头上的古老 3.4 系列内核，以及他们的专有 CedarX 软件（尽管有一个开源项目正在取得良好进展，最终可能会支持 F1C100s 和 F1C200s）。📱🎶

Other than that, these parts are pretty bare-bones in terms of peripherals: there’s a single SDIO interface, a single USB port, no Ethernet, really no programmable timer resources (other than two simple PWM outputs), no RTC, and just a smattering of I2C/UART/SPI ports.
除此之外，这些部件在外设方面相当简陋：只有一个 SDIO 接口，一个 USB 端口，没有以太网，实际上没有可编程定时器资源（除了两个简单的 PWM 输出），没有实时时钟（RTC），只有少量的 I2C/UART/SPI 端口。🔌
Like the NUC980, this part has no secure boot / secure key storage capabilities — but it also doesn’t have any sort of crypto accelerator, either.
与 NUC980 一样，这个部件没有安全启动/安全密钥存储功能——但它也没有任何加密加速器。🔒

The main reason you’d bother with the hassle of these parts is the size and price: these chips are packaged in a 10x10mm 88-pin QFN and hover in the $1.70 range for the F1C100s and $2.30 for the F1C200s.
您之所以愿意麻烦这些部件，主要是因为它们的尺寸和价格：这些芯片被封装在 10x10mm 的 88 针 QFN 中，F1C100s 的价格大约在 1.70 美元左右，而 F1C200s 的价格则在 2.30 美元左右。💰
Like the A33, the F1C100s doesn’t have good availability outside of China; Taobao will have better pricing, but AliExpress provides an English-language front-end and easy U.S. shipping.
与 A33 类似，F1C100s 在中国以外的供应情况不佳；淘宝的价格更具竞争力，但 AliExpress 提供了英语界面和便捷的美国运输。🛒

The most popular piece of hardware I’ve seen that uses these is the Bittboy v3 Retro Gaming handheld (YouTube teardown video).
我见过使用这些硬件的最受欢迎的设备是 Bittboy v3 复古游戏掌机（YouTube 拆解视频）🎮

Hardware Design 硬件设计💻

There may or may not be official dev boards from Allwinner, but most people use the $7.90 Lichee Pi Nano as a reference design. This is set up to boot from SPI NOR flash and directly attach to a TFT via the standard 40-pin FPC pinouts used by low-cost parallel RGB LCDs.
可能有也可能没有来自全志的官方开发板，但大多数人使用价格为 7.90 美元的 Lichee Pi Nano 作为参考设计。🖥️ 该设计设置为从 SPI NOR 闪存启动，并通过低成本并行 RGB LCD 所使用的标准 40 针 FPC 引脚直接连接到 TFT。📺

Of all the parts reviewed here, these were some of the simplest to design hardware around. The 0.4mm-pitch QFN package provided good density while remaining easy to solder. You’ll end up with 45 usable I/O pins (plus the dedicated audio codec).
在这里评审的所有部分中，这些是设计硬件时最简单的部分之一。0.4mm 引脚间距的 QFN 封装提供了良好的密度，同时仍然易于焊接。你将获得 45 个可用的 I/O 引脚（加上专用的音频编码器）。🔧

The on-chip DDR memory needs an external VDD/2 VREF divider, and if you want good analog performance, you should probably power the 3V analog supply with something other than the 2.5V noisy memory voltage as I did, but otherwise, there’s nothing more needed than your SPI flash chip, a 24 MHz crystal, a reset pull-up circuit, and your voltage regulators.
片上 DDR 存储器需要一个外部的 VDD/2 VREF 分压器，如果你想要良好的模拟性能，最好用除了 2.5V 噪声大的存储器电压之外的电源来供电 3V 模拟电源，就像我做的那样，但除此之外，你只需要你的 SPI 闪存芯片、一个 24 MHz 的晶体、一个复位上拉电路和你的电压调节器即可。🛠️
There are no boot configuration pins or OTP fuses to program; on start-up, the processor attempts to boot from SPI NAND or NOR flash first, followed by the SDIO interface, and if neither of those work, it goes into USB bootloader mode.
没有引导配置引脚或一时间可编程熔丝来进行编程；在启动时，处理器首先尝试从 SPI NAND 或 NOR 闪存启动，其次是 SDIO 接口，如果这两者都无法工作，则进入 USB 引导加载程序模式。🔄
If you want to force the board to enter USB bootloader mode, just short the MOSI output from the SPI Flash chip to GND — I wired up a pushbutton switch to do just this.
如果你想强制电路板进入 USB 引导加载程序模式，只需将 SPI Flash 芯片的 MOSI 输出短接到地 — 我接了一个按钮开关来实现这一点。🔌

The chip needs a 3.3V, 2.5V and 1.1V supply. I used linear regulators to simplify the BOM, and ended up using a dual-output regulator for the 3.3V and 2.5V rails. 15 BOM lines total (including the MicroSD card breakout).
该芯

Software 软件💻

Software on the F1C100s, like all Allwinner parts, is a bit of a mess. I ended up just grabbing a copy of buildroot and hacking away at it until I got things set up with a JFFS2-based rootfs, this kernel and this u-boot. I don’t want this review to turn into a tutorial; there are many unofficial sources of information on the F1C100s on the internet, including the Lichee Pi Nano guide. Also of note, George Hilliard has done some work with these chips and has created a ready-to-roll Buildroot environment — I haven’t tried it out, but I’m sure it would be easier to use than hacking at one from scratch.
F1C100s 上的软件和所有全志部件一样，有点乱。🌀 我最终只是拿了一份 buildroot 的副本，开始修改，直到我用基于 JFFS2 的 rootfs、这个内核和这个 u-boot 配置好了系统。🔧 我不想让这篇评论变成教程；网上有很多关于 F1C100s 的非官方信息来源，包括 Lichee Pi Nano 指南。📚 另外，George Hilliard 也对这些芯片做了一些工作，并创建了一个现成的 Buildroot 环境——我还没试过，但我相信用它会比从零开始修改要容易得多。👍

Once you do get everything set up, you’ll end up with a bog-standard mainline Linux kernel with typical Device Tree support. I set up my Buildroot tree to generate a YAFFS2 filesystem targeting an SPI NOR flash chip.
一旦你完成了所有设置，最终你会得到一个标准的主流 Linux 内核，具有典型的设备树支持。🚀 我设置了我的 Buildroot 树，以生成一个 YAFFS2 文件系统，目标是一个 SPI NOR 闪存芯片。💾

These parts have a built-in USB bootloader, called FEL, so you can reflash your SPI flash chip with the new firmware. Once again, we have to turn to the open-source community for tooling to be able to use this: the sunxi-tools package provides the sunxi-fel command-line utility for flashing images to the board.
这些部件内置了一个名为 FEL 的 USB 引导加载程序，因此您可以使用新固件重新闪存您的 SPI 闪存芯片。🔄 再次，我们必须依赖开源社区提供的工具来使用这一功能：sunxi-tools 包提供了 sunxi-fel 命令行工具，用于将映像闪存到板上。💻
I like this flash tool much better than some of the other ones in this review — since the chip waits around once flashing is complete to accept additional commands, you can repeatedly call this utility from a simple shell script with all the files you want; there’s no need to combine the different parts of your flash image into a monolithic file first.
我比这篇评论中的其他一些闪存工具更喜欢这个闪存工具——由于芯片在闪存完成后会等待接受额外的命令，您可以在简单的 Shell 脚本中多次调用这个工具，带上您想要的所有文件；不需要先将您的闪存映像的不同部分合并成一个单一的文件。📂

While the F1C100s / F1C200s can boot from SPI NAND or NOR flash, sunxi-fel only has ID support for SPI NOR flash. A bigger gotcha is that the flash-programming tool only supports 3-byte addressing, so it can only program the first 16MB of an SPI flash chip.
虽然 F1C100s / F1C200s 可以从 SPI NAND 或 NOR 闪存启动，但 sunxi-fel 仅支持 SPI NOR 闪存的 ID。🔍 一大问题是，闪存编程工具仅支持 3 字节寻址，因此它只能编程 SPI 闪存芯片的前 16MB。💾
This really limits the sorts of applications you can do with this chip — with the default memory layout, you’re limited to a 10 MB rootfs partition, which isn’t enough to install Qt or any other large application framework.
这确实限制了你可以使用这个芯片的应用类型——在默认的内存布局下，你被限制在 10 MB 的 rootfs 分区，这对于安装 Qt 或其他大型应用框架来说不够。💻
I hacked at the tool a bit to support 4-byte address mode, but I’m still having issues getting all the pieces together to boot, so it’s not entirely seamless.
我对这个工具进行了一些修改，以支持 4 字节地址模式，但我仍然在拼凑所有组件以实现启动方面遇到问题，所以这并不是完全无缝的。🛠️

Microchip SAM9X60 SIP 微芯科技 SAM9X60 SIP 🛠️

The SAM9X60 is a new ARM9-based SoC released at the end of 2019. Its name pays homage to the classic AT91SAM9260. Atmel (now part of Microchip) has been making ARM microprocessors since 2006 when they released that part.
SAM9X60 是一个基于 ARM9 的新型系统级芯片（SoC），于 2019 年底发布。🛠️ 其名称向经典的 AT91SAM9260 致敬。🎉 Atmel（现为 Microchip 的一部分）自 2006 年发布该芯片以来，一直在制造 ARM 微处理器。💻
They have a large portfolio of them, with unusual taxonomies that I wouldn’t spend too much time trying to wrap my head around.
他们有一个庞大的产品组合，拥有不寻常的分类，我不会花太多时间去理解这些。 🧐
They classify the SAM9N, SAM9G, and SAM9X as different families — with their only distinguishing characteristic is that SAM9N parts only have 1 SDIO interface compared to the two that the other parts have, and the SAM9X has CAN while the others don’t.
他们将 SAM9N、SAM9G 和 SAM9X 归类为不同的系列——唯一的区别在于 SAM9N 组件只有 1 个 SDIO 接口，而其他组件有两个，并且 SAM9X 具有 CAN 接口，而其他则没有。📦
Within each of these “families,” the parts vary by operating frequency, peripheral selection, and even package.((One family, however, stands out as being considerably different from all the others.
在这些“系列”中，各个部件在操作频率、外设选择甚至封装上都有所不同。🌟 不过，有一个系列显得与其他系列明显不同。🔍
The SAM9XE is basically a 180 MHz ARM9 microcontroller with embedded flash.)) Don’t bother trying to make sense of it. And, really, don’t bother looking at anything other than the SAM9X60 when starting new projects.
SAM9XE 基本上是一个具有嵌入式

While it carries a legacy name, this part is obviously intended to be a “reset” for Microchip.
尽管它承载着一个传统的名称，但这一部分显然旨在成为 Microchip 的“重置”。🔄
When introduced last year, it simultaneously became the cheapest and best SAM9 available — 600-MHz core clock, twice as much cache, tons more communication interfaces, twice-as-fast 1 MSPS ADC, and better timers.
去年推出时，它同时成为了市面上最便宜和最好的 SAM9 —— 600MHZ 核心时钟，双倍缓存，更多通信接口，速度提升一倍的 1 MSPS ADC，以及更好的计时器。💻
And it’s the first SAM-series application processor I’ve seen that carries a Microchip badge on the package.
这是我见过的第一个带有 Microchip 标志的 SAM 系列应用处理器。💻

All told, the SAM9X60 has 13 UARTs, 6 SPI, 13 I2C, plus I2s, parallel camera and LCD interfaces. It also features three proper high-speed USB ports (the only chip in this round-up that had that feature).
总的来说，SAM9X60 有 13 个 UART，6 个 SPI，13 个 I2C，还有 I2S、并行摄像头和 LCD 接口。🎉它还具备三个真正的高速 USB 端口（这是本次汇总中唯一具备此功能的芯片）。🔌
Unlike the F1C100s and NUC980, this part has Secure Boot capability, complete with secure OTP key storage, tamper pins, and a true random number generator (TRNG). Like the NUC980, it also has a crypto accelerator. It does not have a trusted execution environment, though, which only exists in Cortex-A offerings.
与 F1C100s 和 NUC980 不同，这个部件具有安全启动功能，配备安全的一次性编程（OTP）密钥存储、篡改针脚和真实随机数生成器（TRNG）。🔒像 NUC980 一样，它也具有加密加速器。不过，它没有可信执行环境，这在 Cortex-A 系列中才存在。🛡️

This part doesn’t have true embedded audio codec like the F1C100s does, but it has a Class D controller, which looks like it’s essentially just a PWM-type peripheral, with either single-ended or differential outputs.
这部分没有像 F1C100s 那样的真实嵌入式音频编码器，但它有一个 D 类控制器，基本上看起来就是一个 PWM 类型的外设，具有单端或差分输出。🔊
I suppose it’s kind of a neat feature, but the amount of extraneous circuitry required will add 7 BOM lines to your project — far more than just using a single-chip Class-D amplifier.
我想这算是一个不错的功能，但所需的额外电路会为你的项目增加 7 条物料清单——远远超过仅使用单芯片 D 类放大器的复杂程度。🔌

This processor comes as a stand-alone MPU (which rings in less than $5), but the more interesting option integrates SDRAM into the package. This SIP option is available with SDR SDRAM (available in an 8 MB version), or DDR2 SDRAM (available in 64 and 128 MB versions).
这个处理器以独立的微处理器（价格低于 5 美元）形式提供，但更有趣的选择是将 SDRAM 集成到封装中。这个系统级封装选项提供了 SD SDRAM（有 8 MB 版本可选），或 DDR2 SDRAM（有 64 MB 和 128 MB 版本可选）。💻
Unless you’re doing bare-metal development, stick with the 64MB version (which is $8), but mount the 128MB version ($9.50) to your prototype to develop on — both of these are housed in a 14x14mm 0.8mm-pitch BGA that’s been 20% depopulated down to 233 pins.
除非你在进行裸金属开发，否则请选择 64MB 版本（售价 8 美元），但可以在你的原型上安装 128MB 版本（售价 9.50 美元）进行开发——这两种版本均采用 14x14mm、0.8mm 引脚间距的 BGA 封装，已经减少了 20%的引脚数量，缩减至 233 个引脚。🛠️

It’s important to note that people design around SIPs to reduce design complexity, not cost. While you’d think that integrating the DRAM into the package would be cheaper than having two separate ICs on your board, you always pay a premium for the difficult-to-manufacture SIP version of chips: pairing a bare SAM9X60 with a $1.60 stand-alone 64MB DDR2 chip is $6.60 — much less than the $8 SIP with the same capacity.Also, the integrated- and non-integrated-DRAM versions come with completely different ball-outs, so they’re not drop-in compatible.
人们在设计时围绕系统集成封装（SIP）进行设计，主要是为了降低设计复杂性，而不是成本，这是很重要的。💡 虽然你可能认为将 DRAM 集成到封装中会比在电路板上使用两个独立的集成电路便宜，但实际上你总是要为难以制造的 SIP 版本的芯片支付额外费用：将一个裸 SAM9X60 与一个$1.60 的独立 64MB DDR2 芯片配对的成本是$6.60——这远低于同样容量的$8 SIP。💰 此外，集成和非集成 DRAM 版本的引脚排列完全不同，因此它们不是可互换的。🔌

If you’d like to try out the SAM9X60 before you design a board around it, Microchip sells the $260 SAM9X60-EK. It’s your typical old-school embedded dev board — complete with lots of proprietary connectors and other oddities. It’s got a built-in J-Link debugger, which shows that Microchip sees this as a viable product for bare-metal development, too.
如果你想在设计电路板之前试用 SAM9X60，Microchip 出售售价为 260 美元的 SAM9X60-EK。这是一款典型的老式嵌入式开发板——配备了许多专有连接器和其他奇特之处。它内置了 J-Link 调试器，这表明 Microchip 也将其视为适合裸金属开发的可行产品。💻
This is a pretty common trend in the industry that I’d love to see changed. I would prefer a simpler dev board that just breaks out all the signals to 0.1″ headers — maybe save for an RMII-connected Ethernet PHY and the MMC buses.
这是业界一个相当普遍的趋势，我希望看到改变。😊 我更喜欢一个简单的开发板，只将所有信号引出到 0.1″的接头——也许可以为一个 RMII 连接的以太网 PHY 和 MMC 总线保留一些端口。💻

My issue is that none of these signals are particularly high-speed so there’s no reason to run them over proprietary connectors.
我的问题是，这些信号都不是特别高速，因此没有理由通过专有连接器来传输它们。🔌
Sure, it’s a hassle to breadboard something like a 24-bit RGB LCD bus, but it’s way better than having to design custom adapter boards to convert the 0.5mm-pitch FPC connection to whatever your actual display uses.
当然，像 24 位 RGB LCD 总线这样的东西在面包板上搭建确实麻烦，但总比为了将 0.5mm 间距的 FPC 连接转换为你实际显示器使用的连接而设计自定义适配器板要强得多。📟

These classic dev board designs are aptly named “evaluation kits” instead of “development platforms.” They end up serving more as a demonstration that lets you prototype an idea for a product — but when it comes time to actually design the hardware, you have to make so many component swaps that your custom board is no longer compatible with the DTS / drivers you used on the evaluation kit.
这些经典的开发板设计被恰当地称为“评估工具包”，而不是“开发平台”。🛠️ 它们最终更像是一个演示，可以让你为产品原型设计一个想法——但当真正需要设计硬件时，你必须进行许多组件替换，以至于你的定制板不再与评估工具包中使用的 DTS/驱动程序兼容。🔌
I’m really not a fan of these (that’s one of the main reasons I designed a bunch of breakout boards for all these chips).
我真的不喜欢这些（这就是我为所有这些芯片设计了一堆扩展板的主要原因之一）。😊

Hardware Design 硬件设计 💻

Microchip selectively-depopulated the chip in such a way that you can escape almost all I/O signals on the top layer. There are also large voids in the interior area which gives ample room for capacitor placement without worrying about bumping into vias.
Microchip 选择性地去除了芯片，使得您可以几乎将所有的 I/O 信号从顶层引出。内部区域也有大面积的空隙，这为电容器的放置提供了充足的空间，无需担心碰到过孔。💡
I had a student begging me to let him lay out a BGA-based embedded Linux board, and this processor provided a gentle introduction.
我有一个学生恳求我让他设计一个基于 BGA 的嵌入式 Linux 板，而这个处理器提供了一个温和的入门体验。😊

Powering the SAM9X60 is a similar affair to the NUC980 or F1C100s. It requires 3.3V, 1.8V and 1.2V supplies — we used a 3.3V and dual-channel 1.8/1.2V LDO. In terms of overall design complexity, it’s only subtly more challenging than the other two ARM9s.
为 SAM9X60 供电的方式与 NUC980 或 F1C100s 类似。⚡它需要 3.3V、1.8V 和 1.2V 的电源——我们使用了 3.3V 以及双通道的 1.8/1.2V 线性稳压器。🔌在整体设计复杂性方面，它只比其他两个 ARM9 稍微具有挑战性。🛠️
It requires a precision 5.62k bias resistor for USB, plus a 20k precision resistor for DDR, in addition to a DDR VREF divider. There’s a 2.5V internal regulator that must be bypassed.
它需要一个精度为 5.62k 的 USB 偏置电阻， plus 一个 20k 的精度电阻用于 DDR，此外还需要一个 DDR VREF 分压器。还有一个必须旁路的 2.5V 内部稳压器。🔧

But this is the complexity you’d expect from a mainstream vendor who wants customers to slide through EMC testing without bothering their FAEs too much.
但是这是你会期待的来自一个主流供应商的复杂性，他们希望客户能够轻松通过 EMC 测试，而不太打扰他们的 FAE 们。💻

The 233-ball package provides 112 usable I/O pins — more than any other ARM9 reviewed.
233 块封装提供 112 个可用的 I/O 引脚——比其他任何评审过的 ARM9 都要多。📦

Unfortunately, most of these additional I/O pins seem to focus on reconfigurable SPI/UART/I2C communication interfaces (FLEXCOMs) and a parallel NAND flash interface (which, from the teardowns I’ve seen, is quickly falling out of style among engineers).
不幸的是，这些额外的 I/O 引脚大多集中在可重构的 SPI/UART/I2C 通信接口（FLEXCOMs）和并行 NAND 闪存接口上（从我看到的拆解情况来看，这种接口在工程师中迅速变得不再流行）。📉
How many UARTs does a person really need? I’m trying to think of the last time I needed more than two.
一个人到底需要多少个 UART？我在想上一次我需要超过两个的是什么时候。🤔

The victim of this haphazard pin-muxing is the LCD and CSI interfaces, which have overlapping pins. And Microchip didn’t even do it in a crafty way like the F1C100s where you could still run an LCD (albeit in 16-bit mode) with an 8-bit camera sensor attached.
因此，这种随意的引脚多路复用的受害者是 LCD 和 CSI 接口，它们的引脚重叠。😕而且微芯片甚至没有像 F1C100s 那样巧妙地处理这一问题，在这种情况下，你仍然可以连接一个 8 位相机传感器并以 16 位模式运行 LCD。📸

Software Design 软件设计 🖥️

This is a new part that hasn’t made its way into the main Buildroot branch yet, but I grabbed the defconfig and board folder from this Buildroot-AT91 branch. They’re using the linux4sam 4.4 kernel, but there’s also mainline Linux support for the processor, too.
这是一个新组件，还没有融入到主 Buildroot 分支中，但我从这个 Buildroot-AT91 分支中获取了 defconfig 和 board 文件夹。🛠️ 他们正在使用 linux4sam 4.4 内核，但处理器也支持主线 Linux。🖥️

The Buildroot/U-Boot defconfig was already set up to boot from a MicroSD card, which makes it much easier to get going quickly on this part; you don’t have to fiddle with configuring USB flasher software as I did for the SPI-equipped NUC980 and F1C100s board, and your rootfs can be as big as you’d like.
Buildroot/U-Boot 的 defconfig 已经设置为从 MicroSD 卡启动，这使得在这个部分快速启动变得容易得多；你不必像我为 SPI 配备的 NUC980 和 F1C100s 板所做的那样去调试 USB 刷写软件，而且你的 rootfs 大小可以随意设置。📦
Already, that makes this chip much easier to get going — you’ll have no issues throwing on SSH, GDB, Python, Qt, and any other tools or frameworks you’re interested in trying out.
这使得这款芯片更容易启动——你将不会有任何问题来使用 SSH、GDB、Python、Qt 以及你有兴趣尝试的其他工具或框架。🚀

Just remember that this is still just an ARM9 processor; it takes one or two minutes to install a single package from pip, and you might as well fix yourself a drink while you wait for SSH to generate a keypair. I tested this super simple Flask app (which is really just using Flask as a web server) and page-load times seemed completely reasonable; it takes a couple seconds to load large assets, but I don’t think you’d have any issue coaxing this processor into light-duty web server tasks for basic smart home provisioning or configuration.
只需记住，这仍然只是一个 ARM9 处理器；从 pip 安装一个软件包需要一两分钟，你不妨在等待 SSH 生成密钥对的时候给自己倒杯饮料。🍹我测试了这个超级简单的 Flask 应用程序（它实际上只是将 Flask 用作 Web 服务器），页面加载时间似乎完全合理；加载大型资产需要几秒钟，但我认为你可以轻松让这个处理器承担基本智能家居配置或设置的轻任务。💻

The DTS files for both this part and the SAMA5D27 below were a bit weird. They don’t use phandles at all for their peripherals; everything is re-declared in the board-specific DTS file, which makes them extremely verbose to navigate.
这部分和下面的 SAMA5D27 的 DTS 文件有点奇怪。它们的外设根本没有使用 phandle；所有内容都在特定于板子的 DTS 文件中重新声明，这使得它们在浏览时显得非常冗长。📂
Since they have labels in their base DTS file, it’s a simple fix to rearrange things in the board file to reference those labels — I’ve never seen a vendor do things this way, though.
由于它们在基础 DTS 文件中有标签，因此在板文件中重新排列以引用这些标签是一个简单的修复——不过我从未见过供应商以这种方式处理。 🛠️

As is typical, they require that you look up the actual peripheral alternate-function mode index — if you know a pin has, say, I2C2_SDA capability, you can’t just say you want to use it with “I2C2.” This part has a ton of pins and not a lot of different kinds of peripherals, so I’d imagine most people would just leave everything to the defaults for most basic applications.
通常，他们要求你查找实际的外设备用功能模式索引——如果你知道一个引脚具有，例如，I2C2_SDA 功能，你不能仅仅说想用“I2C2”。这个部分有很多引脚，但外设种类不多，所以我想大多数人会在大多数基本应用中将一切保留为默认设置。🔍

The EVK DTS has pre-configurated pinmux schemes for RGB565, RGB666, and RGB888 parallel LCD interfaces, so you can easily switch over to whichever you’re using.
EVK DTS 预配置了 RGB565、RGB666 和 RGB888 并行 LCD 接口的引脚复用方案，因此您可以轻松切换到您正在使用的接口。🌈
The default timings were reasonable; I didn’t have to do any configuration to interface the chip with a standard 5″ 800×480 TFT. I threw Qt 5 plus all the demos on an SD card, plugged in a USB mouse to the third USB port, and I was off to the races.
默认的时序设置是合理的；我不需要进行任何配置就可以将芯片与标准的 5 英寸 800×480 TFT 屏幕连接起来。🎉 我把 Qt 5 和所有示例放在一张 SD 卡上，插入了 USB 鼠标到第三个 USB 接口，然后就顺利启动了。🚀
Qt Quick / QML is perfectly useable on this platform, though you’re going to run into performance issues if you start plotting a lot of signals. I also noticed the virtual keyboard tends to stutter when changing layouts.
Qt Quick / QML 在这个平台上完全可以使用，不过如果你开始绘制大量信号，就会遇到性能问题。😅 我还注意到，当更改布局时，虚拟键盘往往会卡顿。🖥️

Documentation is fairly mixed. AN2772 covers the basics of embedded Linux development and how it relates to the Microchip ecosystem (a document that not every vendor has, unfortunately).
文档质量参差不齐。AN2772 涵盖了嵌入式 Linux 开发的基础以及它与 Microchip 生态系统的关系（不幸的是，并不是每个供应商都有这份文件）。📄
But then there are huge gaping holes: I couldn’t really track down much official documentation on SAM-BA 3.x, the new command-line version of their USB boot monitor application used to program fuses and load images if you’re using on-board flash memory.
但仍然存在巨大的空白：我实在找不到关于 SAM-BA 3.x 的官方文档，这是他们用于编程熔丝和加载镜像的 USB 启动监视器应用程序的新命令行版本，适用于使用板载闪存的情况。💻
Everything on Microchip’s web site is for the old 2.x series version of SAM-BA, which was a graphical user interface. Most of the useful documentation is on the Linux4SAM wiki.
Microchip 网站上的所有内容都是针对旧的 2.x 系列版本的 SAM-BA，这是一种图形用户界面。🖥️ 大部分有用的文档都在 Linux4SAM 维基上。📚

Microchip SAMA5D27 SIP 微芯科技 SAMA5D27 SIP 🛠️

With their acquisition of Atmel, Microchip inherited a line of application processors built around the Cortex-A5 — an interesting oddity in the field of slower ARM9 cores and faster Cortex-A7s in this roundup.
通过收购 Atmel，Microchip 继承了一系列基于 Cortex-A5 的应用处理器——在这次汇总中，这是在较慢的 ARM9 核心和较快的 Cortex-A7 之间的一个有趣异类。🤖
The Cortex-A5 is basically a Cortex-A7 with only a single-width instruction decode and optional NEON (which our particular SAMA5 has).
Cortex-A5 基本上是 Cortex-A7，但只有单宽指令解码，并且可选的 NEON（我们特定的 SAMA5 具有此功能）。🖥️

There are three family members in the SAMA5 klan, and, just like the SAM9, they all have bizarre product differentiation.
SAMA5 家族有三个成员，和 SAM9 一样，它们都具有奇特的产品差异化。🛠️

The D2 part features 500 MHz operation with NEON and TrustZone, a DDR3 memory controller, ethernet, two MMC interfaces, 3 USB, CAN, plus LCD and camera interfaces.
D2 部件具有 500 MHz 的运行频率，并支持 NEON 和 TrustZone，配备 DDR3 内存控制器、Ethernet、两个 MMC 接口、3 个 USB、CAN 以及 LCD 和摄像头接口。📦
Moving up to the D3, we bump up to 536 MHz, lose the NEON and TrustZone extensions, lose the DDR3 support, but gain a gigabit MAC. Absolutely bizarre.
升级到 D3 后，我们的频率提升到 536 MHz，但失去了 NEON 和 TrustZone 扩展，且不再支持 DDR3，同时获得了一个千兆 MAC。真是太奇怪了。😕
Moving up to the D4, and we get our NEON and TrustZone back, still no DDR3, but now we’re at 600 MHz and we have a 720p30 h.264 decoder.
升级到 D4，我们恢复了 NEON 和 TrustZone，仍然没有 DDR3，但现在我们达到了 600 MHz，并且具备 720p30 h.264 解码器。📈

I can’t make fun of this too much, since lots of companies tailor-make application processors for very specific duties; they’ve decided the D2 is for secure IoT applications, the D3 is for industrial work, and the D4 is for portable multimedia applications.
我不能对此嘲笑太多，因为许多公司为非常特定的任务量身定制应用处理器；他们已经决定 D2 用于安全的物联网应用，D3 用于工业工作，D4 则用于便携式多媒体应用。🛠️

Zooming into the D2 family, these seem to only vary by CAN controller presence, die shield (for some serious security!), and I/O count (which I suppose also affects peripheral counts).
缩小到 D2 系列，这些似乎仅通过 CAN 控制器的存在、芯片保护层（用于增强安全性！）以及 I/O 数量（我想这也会影响外设的数量）来进行区分。🔍
The D27 is nearly the top-of-the-line model, featuring 128 I/O, a 32-bit-wide DDR memory bus (twice the width of every other part reviewed), a parallel RGB LCD controller, parallel camera interface, Ethernet MAC, CAN, cap-touch, 10 UARTs, 7 SPIs, 7 I2Cs, two MMC ports, 12 ADC inputs, and 10 timer/PWM pins.
D27 几乎是顶级型号，拥有 128 个 I/O，32 位宽的 DDR 内存总线（是其他每个评测的部件宽度的两倍），并配备并行 RGB LCD 控制器、并行相机接口、以太网 MAC、CAN、触摸感应、10 个 UART、7 个 SPI、7 个 I2C、两个 MMC 端口、12 个 ADC 输入和 10 个定时器/PWM 引脚。💻

Like the SAM9X60, these parts feature good secure-boot features, as well as standard crypto acceleration capabilities. Microchip has an excellent app note that walks you through everything required to get secure boot going. Going a step further, this is the first processor in our review that has TrustZone, with mature support in OP-TEE.
像 SAM9X60 一样，这些部件具有良好的安全启动功能，以及标准的密码加速能力。🔐 Microchip 有一份优秀的应用说明，可以指导您完成启动安全启动所需的一切。📑 更进一步，这是我们评测中的第一款拥有 TrustZone 的处理器，且在 OP-TEE 中有成熟的支持。🔒

These D2 chips are available in several different package sizes: a tiny 8x8mm 256-ball 0.4mm (!) pitch BGA with lots of selective depopulations, an 11×11 189-ball 0.75mm-pitch full-rank BGA, and a 14x14mm 289-ball 0.8mm-pitch BGA, also full-rank.
这些 D2 芯片有几种不同的封装尺寸可供选择：一个微型 8x8mm 的 256 球 0.4mm (!) 踏点 BGA，带有大量选择性去球，一个 11×11 189 球 0.75mm 踏点的全排 BGA，以及一个 14x14mm 的 289 球 0.8mm 踏点的全排 BGA。📦

The more interesting feature of this line is that many of these have a SIP package available. The SIP versions use the same packaging but different ball-outs.
这一系列中更有趣的特点是，许多产品都有 SIP 封装可供选择。SIP 版本使用相同的封装，但引脚排列不同。📦
They’re available in the 189- and 289-ball packages, along with a larger 361-ball package that takes advantage of the 32-bit-wide memory bus (the only SIP I know that does this).
它们有 189 球和 289 球的包装可供选择，还有一个更大的 361 球包装，利用了 32 位宽的内存总线（我所知道的唯一一个做到这一点的 SIP）。⚙️
I selected the SAMA5D27-D1G to review — these integrate 128 MB of DDR2 memory into the 289-ball package.
我选择了 SAMA5D27-D1G 进行评审——它们将 128 MB 的 DDR2 内存集成到 289 球封装中。📦

For evaluation, Microchip has the $200 ATSAMA5D27-SOM1-EK, which actually uses the SOM — not SIP — version of this chip. It’s a pretty typical dev board that’s similar to the SAM9X60-EK, so I won’t rehash my opinions on this style of evaluation kit.
为了评估，Microchip 提供了 $200 的 ATSAMA5D27-SOM1-EK，它实际上使用的是该芯片的 SOM 版本，而不是 SIP 版本。💻 这是一款非常典型的开发板，类似于 SAM9X60-EK，因此我不会重复我对这种评估工具的看法。🔧

Hardware Design 硬件设计 💻

As we’ve seen before, the SAMA5 uses a triple-supply 3.3V/1.8V/1.2V configuration for I/O, memory, and core. There’s an additional 2.5V supply you must provide to program the fuses if necessary, but Microchip recommends leaving the supply unpowered during normal operation.
正如我们之前所见，SAMA5 使用三电源 3.3V/1.8V/1.2V 配置来供电给 I/O、内存和核心。🔌 如果需要编程熔丝，您还必须提供额外的 2.5V 电源，但 Microchip 建议在正常操作期间保持该电源不通电。⚡

The SIP versions of these parts use Revision C silicon (MRL C, according to Microchip documentation). If you’re interested in the non-SIP version of this part, make sure to opt for the C revision.
这些零件的 SIP 版本使用的是 Revision C 的硅片（根据 Microchip 文档为 MRL C）。如果您对该零件的非 SIP 版本感兴趣，请确保选择 C 修订版。🔍
Revision A of the part is much worse than B or C — with literally twice as much power consumption. Revision B fixed the power consumption figures, but can’t boot from the SDMMC interface (!!) because of a card-detect sampling bug.
该部件的版本 A 的功耗远远高于 B 或 C，几乎是它们的两倍。🔋 版本 B 修正了功耗数据，但由于存在卡检测采样错误，无法通过 SDMMC 接口引导（！！）。🛠️
Revision C fixes that bug and provides default booting from SDMMC0 and SDMMC1 without needing to do any SAM-BA configuration.
修订版 C 修复了该错误，并提供了从 SDMMC0 和 SDMMC1 的默认引导，无需进行任何 SAM-BA 配置。🛠️

Escaping signals from this BGA is much more challenging than most other chips in this review, simply because it has a brain-dead pin-out.
从这个 BGA 引脚逃离信号比本次评测中大多数其他芯片要困难得多，这仅仅是因为它的引脚布局非常糟糕。🧠
The IC only has 249 signals, but instead of selectively-depopulating a 289-ball package like the SAM9X60 does, Microchip leaves the package full-rank and simply marks 40 of these pins as “NC” — forcing you to carefully route around these signals.
这款集成电路只有 249 个信号，但与 SAM9X60 选择性去除 289 球封装不同，Microchip 保持封装的满排布，并简单地将其中 40 个引脚标记为“NC” —— 强制你仔细绕过这些信号。⚠️
Rather than putting these NC pins toward the middle of the package, they’re bumped up in the corner, which is awful to work around.
与其将这些 NC 引脚放置在封装的中间，不如将它们放在角落，这样的设计实在令人头疼。😩

The power supply pins are also randomly distributed throughout the package, with signal pins going all the way to the center of the package — 8 rows in. This makes 4-layer fanout trickier since there are no internal signal layers to route on.
电源引脚在封装内随机分布，信号引脚则一路延伸到封装的中心——共 8 行。这使得 4 层扇出变得更加复杂，因为没有内部信号层可以进行布线。🔌
In the end, I couldn’t implement Microchip’s recommended decoupling capacitor layout since I simply didn’t have room on the bottom layer.
最后，我无法实施 Microchip 推荐的解耦电容布局，因为我在底层根本没有空间。🔋
This wasn’t an issue at all with the other BGAs in the round-up, which all had centralized power supply pins, or at least a central ground island and/or plenty of voids in the middle area of the chip.
这在其他汇总中的 BGA 上根本不是问题，所有这些 BGA 都有集中供电引脚，或者至少有一个中央接地岛和/或芯片中间区域有足够的空隙。🔌

However, once you do get everything fanned out, you’ll be rewarded with 128 usable I/O pins —second only to the 355-ball RK3308.
然而，一旦你将所有组件展开，你将获得 128 个可用的 I/O 引脚——仅次于 355 球的 RK3308。✨
And that doesn’t include the dedicated audio PLL clock output or the two dedicated USB transceivers  (ignore the third port in my design — it’s an HSIC-only USB peripheral).
这还不包括专用的音频锁相环时钟输出以及两个专用的 USB 收发器（忽略我设计中的第三个端口——它仅是 HSIC USB 外设）。🔌
There are no obvious multiplexing gotchas that the Allwinner or SAM9X60 parts have, and the sheer number of comms interfaces gives you plenty of routing options if you have a large board with a lot of peripherals on it.
没有明显的复用陷阱，Allwinner 或 SAM9X60 部件没有这些问题，而且大量的通信接口为你提供了丰富的布线选择，特别是在拥有众多外设的大型电路板上。🔌

There’s only a single weird 5.62k bias resistor needed, in addition to the DDR VDD/2 reference divider. They ball out the ODT signal, which should be connected to GND for DDR2-based SIPs like the one I used.
只需一个奇怪的 5.62k 偏置电阻，外加 DDR VDD/2 参考分压器。它们将 ODT 信号引出，这个信号应连接到地（GND），适用于我使用的基于 DDR2 的 SIP。🔧

And if you’ve ever wondered about the importance of decoupling caps: I got a little too ahead of myself when these boards came off the hot plate — I plugged them in and started running benchmarking tests before realizing I completely forgot to solder the bottom side of the board full of all the decoupling capacitors.
如果你曾经想知道去耦电容的重要性：当这些电路板从热板上取下时，我有些急于求成 — 我在插上电源并开始运行基准测试之前，完全忘记了将底部满是去耦电容的电路板焊接好。💡
The board ran just fine!((Yes, yes, obviously, if you actually wanted to start depopulating bypass capacitors in a production setting, you’d want to carefully evaluate the analog performance of the part — ADC inputs, crystal oscillator phase jitter, and EMC would be of top concern to me.))
电路板运行得很好！💻（是的，是的，显然，如果你真的想在生产环境中开始去除旁路电容，你会想要仔细评估这个部件的模拟性能——ADC 输入、晶体振荡器的相位抖动和电磁兼容性对我来说都是最重要的关注点。）🔍

Software 软件 🖥️

Current-generation MRL-C devices, like the SIPs I used, will automatically boot from MMC0 without needing to use the SAM-BA monitor software to burn any boot fuses or perform any configuration at all.
当前一代 MRL-C 设备，比如我使用的 SIP，将会自动从 MMC0 启动，无需使用 SAM-BA 监控软件来烧录任何启动熔丝或进行任何配置。💻
But, as is common, it won’t even attempt to boot off the card if the card-detect signal (PA13) isn’t grounded.
但是，通常情况下，如果卡检测信号（PA13）没有接地，它甚至不会尝试从卡启动。🔌

When U-boot finally did start running, my serial console was gibberish and appeared to be outputting text at half the baud I had expected.
当 U-boot 最终开始运行时，我的串口控制台输出的都是乱码，似乎以我预期的一半波特率输出文本。💻
After adjusting the baud, I realized U-boot was compiled assuming a 24 MHz crystal (even though the standard SAMA5D2 Xplained board uses a 12 MHz). This blog post explained that Microchip switched the config to a 24 MHz crystal when making their SOM for this chip.
调整波特率后，我意识到 U-boot 是在假设 24 MHz 晶振的情况下编译的（尽管标准的 SAMA5D2 Xplained 板使用的是 12 MHz）。这篇博客文章解释了 Microchip 在为该芯片制作 SOM 时，将配置切换到了 24 MHz 晶振。📡

The evaluation kits all use eMMC memory instead of MicroSD cards, so I had to switch the bus widths over to 8 bits. The next problem I had is that the write-protect GPIO signal on the SDMMC peripheral driver doesn’t respect your device tree settings and is always enabled.
评估套件全部使用 eMMC 内存而非 MicroSD 卡，因此我不得不将总线宽度切换到 8 位。📏 接下来遇到的问题是，SDMMC 外设驱动上的写保护 GPIO 信号并不尊重你的设备树设置，始终处于启用状态。🔒
If this pin isn’t shorted to GND, Linux will think the chip has write protection enabled, causing it to throw a -30 error code (read-only filesystem error) on boot-up.
如果这个引脚没有短接到地（GND），Linux 会认为芯片启用了写保护，从而在启动时抛出-30 错误代码（只读文件系统错误）。🔧
I ended up adding a wp-inverted declaration in the device tree as a hack, but if I ever want to use that GPIO pin for something else, I’ll have to do some more investigation.
我最终在设备树中添加了一个 wp-inverted 声明作为一种临时解决方案，但如果我以后想用那个 GPIO 引脚做其他事情，我还需要进行更多的调查。🔧

As for documentation, it’s hit or miss. On their product page, they have some cute app notes that curate what I would consider “standard Linux canon” in a concise place to help you use peripherals from userspace in C code (via spidev, i2cdev, sysfs, etc), which should help beginners who are feeling a bit overwhelmed.
关于文档，有时好有时坏。在他们的产品页面上，有一些可爱的应用笔记，归纳了我认为的“标准 Linux 经典”，集中在一个简洁的地方，帮助你在 C 代码中使用来自用户空间的外设（通过 spidev、i2cdev、sysfs 等），这应该能帮助感到有些不知所措的初学者。📄

Allwinner V3s 全志 V3S 🖥️

The Allwinner V3s is the last SIP we’ll look at in this review. It pairs a fast 1 GHz Cortex-A7 with 64 MB of DDR2 SDRAM.
全志 V3s 是我们在本次评测中要看的最后一款 SIP。它搭载了 1 GHz 的 Cortex-A7 处理器和 64 MB 的 DDR2 SDRAM。💻
Most interestingly, it has a build-in audio codec (with microphone preamp), and an Ethernet MAC with a built-in PHY — so you can wire up an ethernet mag jack directly to the processor.
最有趣的是，它内置了音频编码解码器（带麦克风前置放大器），并且有一个带内置物理层的以太网 MAC——所以你可以直接将以太网连接器接入处理器。🔌

Other than that, it has a basic peripheral set: two MMC interfaces, a parallel RGB LCD interface that’s multiplexed with a parallel camera sensor interface, a single USB port, two UARTs, one SPI, and two I2C interfaces. It comes in a 128-pin 0.4mm-pitch QFP.
除此之外，它拥有基本的外设配置：两个 MMC 接口，一个与并行摄像头传感器接口复用的并行 RGB LCD 接口，一个 USB 端口，两个 UART，一个 SPI 和两个 I2C 接口。它采用 128 引脚 0.4mm 间距的 QFP 封装。📦

Hardware Design 硬件设计 🖥️

Just like with the F1C100s, there’s not a lot of official documentation for the V3s. There’s a popular, low-cost, open-source dev board, the Lichee Pi Zero, which serves as a good reference design and a decent evaluation board.
就像 F1C100s 一样，V3s 的官方文档也不多。😕 有一个流行的、低成本的开源开发板，Lichee Pi Zero，它是一个很好的参考设计和可行的评估板。👍

The QFP package makes PCB design straightforward; just like with the NUC980 and F1C100s, I had no problems doing a single-sided design.
QFP 封装使 PCB 设计变得简单；就像 NUC980 和 F1C100s 一样，我在进行单面设计时没有遇到任何问题。📦
On the other hand, I found the package — with its large size and 0.4mm pitch — relatively challenging to solder (I had many shorts that had to be cleaned up).
另一方面，我发现这个封装的尺寸较大且引脚间距为 0.4 毫米，焊接起来相对较具挑战性（我有很多短路需要清理）。🛠️
The large thermal pad in the center serves as the only GND connection and makes the chip impossible to pencil-solder without resorting to a comically-large via to poke your soldering iron into.
中心的大型导热垫是唯一的接地连接，使得芯片无法用铅笔焊接，除非使用一个滑稽的大孔来插入你的电烙铁。🛠️

Again, there are three voltage domains — 3.3V for I/O, 1.8V for memory, and 1.2V for the core voltage. External component requirements are similar to the F1C200s — an external VREF divider, precision bias resistor, and a main crystal — but the V3s adds an RTC crystal.
再次，有三个电压域——3.3V 用于 I/O，1.8V 用于内存，1.2V 用于核心电压。🔋 外部组件要求与 F1C200s 相似——一个外部 VREF 分压器、精密偏置电阻和一个主晶振——但 V3s 增加了一个 RTC 晶振。🕰️

With dedicated pins for the PHY, audio CODEC, and MIPI camera interface, there are only 51 I/O pins on the V3s, with MMC0 pins multiplexed with a JTAG, and two UARTs overlapped with two I2C peripherals, and the camera and LCD parallel interface on top of each other as well.
V3s 上有专用的 PHY、音频 CODEC 和 MIPI 摄像头接口引脚，总共有 51 个 I/O 引脚，其中 MMC0 引脚与 JTAG 复用，两个 UART 与两个 I2C 外设重叠，摄像头和 LCD 并行接口也重叠在一起。✨

To give you an idea about the sort of system you might build with this chip, consider a product that uses UART0 as the console, an SPI Flash boot chip, MMC0 for external MicroSD storage, MMC1 and a UART for a WiFi/BT combo module, and I2C for a few sensors.
为了让你了解使用这款芯片可能构建的系统类型，可以考虑一个产品，该产品使用 UART0 作为控制台，SPI Flash 启动芯片，MMC0 用于外部 MicroSD 存储，MMC1 和 UART 用于 WiFi/BT 组合模块，以及 I2C 用于几个传感器。🔧
That leaves an open LCD or camera interface, a single I2C port or UART, and… that’s it.
这留出了一个开放的 LCD 或相机接口，一个 I2C 端口或 UART，至此完毕。📱

In addition to the massive number of shorts I had when soldering the V3s, the biggest hardware issue I had was with the Ethernet PHY — no one on my network could hear packets I was sending out.
除了在焊接 V3 时遇到大量短路之外，我遇到的最大硬件问题是以太网 PHY——我的网络上没有人能接收到我发送的数据包。🔌
I realized the transmitter was particularly sensitive and needed a 10 uH (!!!) inductor on the center-tap of the mags to work properly. This is clearly documented in the Lichee Pi Base schematics, but I thought it was a misprint and used a ferrite bead instead. Lesson learned!
我意识到发射器特别敏感，需要在磁芯的中心抽头上使用一个 10 微亨（!!!）的电感才能正常工作。这个在 Lichee Pi Base 的原理图中明确记录，但我以为是印刷错误，反而使用了一个铁氧体珠。教训吸取了！💡

Software Design 软件设计 💻

With official Buildroot support for the V3s-based Lichee Pi Zero, software on the V3s is a breeze to get going, but due to holes in mainline Linux support, some of the peripherals are still unavailable. Be sure to mock-up your system and test peripherals early on, since much of the BSP has been quickly ported from other Allwinner chips and only lightly tested.
随着官方对基于 V3s 的 Lichee Pi Zero 的 Buildroot 支持，V3s 上的软件轻松启动，但由于主线 Linux 支持的不足，某些外设仍然不可用。 🛠️ 一定要提前构建系统并测试外设，因为大部分 BSP 是从其他 Allwinner 芯片迅速移植而来，仅经过轻度测试。 ⚙️
I had a group in my Advanced Embedded Systems class last year who ended up with a nonfunctional project after discovering late into the process that the driver for the audio CODEC couldn’t simultaneously play and record audio.
我去年在高级嵌入式系统课程中有一个小组，最后的项目无法正常工作，因为在过程的后期发现音频编码解码器的驱动程序无法同时播放和录制音频。🎧

I’ve played with this chip rather extensively and can confirm the parallel camera interface, parallel RGB LCD interface, audio codec, and comms interfaces are relatively straightforward to get working.
我已经对这个芯片进行了相当广泛的实验，可以确认并行相机接口、并行 RGB LCD 接口、音频编码器和通信接口都相对容易使其正常工作。📷
Just like the F1C100s, the V3s doesn’t have good low-power support in the kernel yet.
就像 F1C100s 一样，V3s 在内核中还没有良好的低功耗支持。⚡

NXP i.MX 6UL/6ULL/6ULZ NXP I.MX 6UL/6ULL/6ULZ 🛠️

The i.MX 6 is a broad family of application processors that Freescale introduced in 2011 before the NXP acquisition. At the high end, there’s the $60 i.MX 6QuadMax with four Cortex-A9 cores, 3D graphics acceleration, and support for MIPI, HDMI, or LVDS.
i.MX 6 是一个广泛的应用处理器系列，Freescale 于 2011 年在被 NXP 收购前推出。💻 在高端中，有售价 60 美元的 i.MX 6QuadMax，配备四个 Cortex-A9 核心、3D 图形加速，并支持 MIPI、HDMI 或 LVDS。🎮
At the low end, there’s the $2.68 i.MX 6ULZ with…. well, basically none of that.
在低端，价格为 2.68 美元的 i.MX 6ULZ，基本上……没有任何这些。💰

For full disclosure, NXP’s latest line of processors is actually the i.MX 8, but these parts are really quite a bit of a technology bump above the other parts in this review and didn’t seem relevant for inclusion.
据全面披露，NXP 最新的处理器系列实际上是 i.MX 8，但这些部件在技术上确实比本次评测中的其他部件高出不少，因此似乎不适合纳入评测中。💻
They’re either $45 each for the massive 800+ pin versions that come in 0.65mm-pitch packages, or they come in tiny 0.5mm-pitch BGAs that are annoying to hand-assemble (and, even with the selectively depopulated pin areas, look challenging to fan-out on a standard-spec 4-layer board).
它们要么是每个$45 的大型 800+引脚版本，采用 0.65mm 间距封装，💵 要么是小型 0.5mm 间距 BGA，这种手动组装起来很麻烦（即使在选择性去除引脚区域的情况下，在标准规格的 4 层板上看起来仍然很难放线）。😩
They also have almost a dozen supply rails that have to be sequenced properly. I don’t have anything against using them if you’re working in a well-funded prototyping environment, but this article is focused on entry-level, low-cost Linux-capable chips.
他们还有将近十条电源轨需要正确排序。如果你在一个资金充足的原型开发环境中使用它们，我对此没有什么意见，但这篇文章关注的是入门级、低成本的支持 Linux 的芯片。💡

We may yet see a 0.8mm-pitch low-end single- or dual-core i.MX 8, as Freescale often introduces higher-end parts first. Indeed, the entry-level 528 MHz i.MX 6UltraLite (UL) was introduced years after the 6SoloLite and SoloX (Freescale’s existing entry-level parts) and represented the first inexpensive Cortex-A7 available.
我们可能会看到一个 0.8 毫米间距的低端单核或双核 i.MX 8，因为 Freescale 通常首先推出更高端的产品。🤖 实际上，528 MHz 的入门级 i.MX 6UltraLite (UL)是在 6SoloLite 和 SoloX（Freescale 现有的入门级产品）之后数年推出的，并且代表了首个经济实惠的 Cortex-A7。💡

The UL has built-in voltage regulators and power sequencing, making it much easier to power than other i.MX 6 designs. Interestingly, this part can address up to 2 GB of RAM (the A33 was the only other part in this review with that capability).
该 UL 内置了电压调节器和电源顺序控制，使其比其他 i.MX 6 设计更容易供电。⚡有趣的是，这个部件可以支持高达 2 GB 的 RAM（在此评测中只有 A33 具备该能力）。🧠
Otherwise, it has standard fare: a parallel display interface, parallel camera interface, two MMC ports, two USB ports, two fast Ethernet ports, three I2S, two SPDIF, plus tons of UART, SPI, and I2C controllers.
否则，它有标准配置：一个并行显示接口，一个并行摄像头接口，两个 MMC 端口，两个 USB 端口，两个快速以太网端口，三个 I2S，两个 SPDIF，以及大量的 UART、SPI 和 I2C 控制器。📡
These specs aren’t wildly different than the 6SoloLite / SoloX parts, yet the UL is half the price.
这些规格与 6SoloLite / SoloX 的部分并没有太大差异，但 UL 的价格却是它的一半。💰

This turns out to be a running theme: there has been a mad dash toward driving down the cost of these parts (perhaps competition from TI or Microchip has been stiff?), but interestingly, instead of just marking down the prices, NXP has introduced new versions of the chip that are essentially identical in features — but with a faster clock and a cheaper price tag.
这似乎是一个持续的主题：人们对降低这些零件的成本进行了疯狂的追逐（也许来自 TI 或 Microchip 的竞争非常激烈？）💸，但有趣的是，NXP 并没有仅仅降价，而是推出了新版本的芯片，这些芯片在功能上基本相同——但时钟更快，价格更便宜。🔧

The 6ULL (UltraLiteLite?) was introduced a couple of years after the UL and features essentially the same specs, in the same package, with a faster 900-MHz clock rate, for the same price as the UL.
6ULL（超轻超轻版？）是在 UL 发布几年后推出的，基本上具有相同的规格，采用相同的封装，时钟频率提高到 900MHz，价格与 UL 相同。 📦
This part has three SKUs: the Y0, which has no security, LCD/CSI, or CAN (and only one Ethernet port), the Y1, which adds basic security and CAN, and the Y2, which adds LCD/CSI, a second CAN, and a second Ethernet.
这个部分有三个 SKU：Y0，没有安全性、LCD/CSI 或 CAN（只有一个以太网端口），Y1，增加了基本的安全性和 CAN，以及 Y2，增加了 LCD/CSI、第二个 CAN 和第二个以太网端口。📦
The latest part — the 6ULZ — is basically the same as the Y1 version of the 6ULL, but with an insanely-cheap $2.68 price tag.
最新的部分——6ULZ——基本上与 6ULL 的 Y1 版本相同，但价格便宜到令人难以置信，仅为$2.68。💰

I think the most prominent consumer product that uses the i.MX 6UL is the Nest Thermostat E, though, like TI, these parts end up in lots and lots of low-volume industrial products that aren’t widely seen in the consumer space. Freescale offers the $149 MCIMX6ULL-EVK to evaluate the processor before you pull the trigger on your own design. This is an interesting design that splits the processor out to its own SODIMM-form-factor compute module and a separate carrier board, allowing you drop the SOM into your own design.
我认为使用 i.MX 6UL 的最显著消费品是 Nest Thermostat E，尽管像 TI 一样，这些部件最终会出现在许多低产量的工业产品中，这些产品在消费市场上并不常见。💡 Freescale 提供了 149 美元的 MCIMX6ULL-EVK，以便在您进行自己的设计之前评估处理器。💻 这是一个有趣的设计，将处理器分离到其自己的 SODIMM 形式因子计算模块和一个单独的载板上，让您可以将 SOM 集成到自己的设计中。🔧
The only major third-party dev board I found is the $39 Seeed Studio NPi. There’s also a zillion PCB SoM versions of i.MX 6 available from vendors of various reputability; these are all horribly expensive for what you’re getting, so I can’t recommend this route.
我找到的唯一主要的第三方开发板是 39 美元的 Seeed Studio NPi。💵 此外，还有无数不同声誉的供应商提供的 i.MX 6 的 PCB SoM 版本；💻 这些价格都非常高昂，而你得到的产品并不值得，所以我不推荐这个选择。🚫

Hardware Design 硬件设计 💻

I tried out both the newer 900 MHz i.MX 6ULL, along with the older 528-MHz 6UL that I had kicking around, and I can verify these are completely drop-in compatible with each other (and with the stripped-down 6ULZ) in terms of both software and hardware.
我尝试了新的 900 MHz i.MX 6ULL，以及我手头的旧的 528 MHz 6UL，我可以确认这两者在软件和硬件方面完全兼容（以及与简化版的 6ULZ）。🔄
I’ll refer to all these parts collectively as “UL” from here on out.
我将

These parts come in a 289-ball 0.8mm-pitch 14x14mm package — smaller than the Atmel SAMA5D27, the Texas Instruments AM335x and the ST STM32MP1.
这些元件采用 289 个引脚、0.8 毫米间距、14x14 毫米的封装，比 Atmel SAMA5D27、德州仪器 AM335x 和 ST STM32MP1 还要小。🔧
Consequently, there are only 106 usable I/O on this part, and just like with most parts reviewed here, there’s a lot of pin-muxing going on.((NXP names the pin with the default alternate function, not a basic GPIO port name, so be prepared for odd-looking pin-muxing names, like I2C1_SCL__UART4_TX_DATA.))
因此，这个芯片上只有 106 个可用的 I/O，就像本节中大多数组件一样，这里涉及了大量的引脚复用。(NXP 使用默认的替代功能命名引脚，而不是基本的 GPIO 端口名称，所以要准备好看到奇怪的引脚复用名称，比如 I2C1_SCL__UART4_TX_DATA。)🔌

The i.MX 6 series is one of the easiest parts to design when compared to similar-scale parts from other vendors.
i.MX 6 系列是与其他供应商类似规模部件相比，最容易设计的部件之一。😊
This is mostly due to its unique internal voltage regulator scheme: A 1.375-nominal VDD_SOC power is brought in and internally regulated to a 0.9 – 1.3V core voltage, depending on CPU speed.
这主要是由于其独特的内部电压调节方案：输入 1.375 的标称 VDD_SOC 电源，内部调节为 0.9 – 1.3V 的核心电压，具体取决于 CPU 速度。⚡
There are additional internal regulators and power switches for 1.1V PLLs, 2.5V analog-domain circuitry, 3.3V USB transceivers, and coin cell battery-backed memory.
还有额外的内部调节器和电源开关，用于 1.1V 的锁相环（PLL）、2.5V 的模拟域电路、3.3V 的 USB 收发器以及备有纽扣电池的存储器。🔌
By using DDR3L memory, I ended up using nothing but two regulators — a 1.35V and 3.3V one — to power the entire system. For power sequencing, the i.MX 6 simply requires the 3.3V rail to come up before the 1.35V one.
通过使用 DDR3L 内存，我最后只使用了两个稳压器——一个是 1.35V，一个是 3.3V——来为整个系统供电。 ⚡ 为了电源排序，i.MX 6 仅要求 3.3V 电源在 1.35V 电源之前启动。 🔋

One hit against the i.MX 6 is the DRAM ball-out: The data bus seems completely discombobulated. I ended up swapping the two data lanes and also swapping almost all the pins in each lane, which I didn’t have to do with any other part reviewed here.
i.MX 6 的一个缺点是 DRAM 信号分配：数据总线似乎完全混乱了。⚠️ 我最后换了两个数据通道，并且几乎交换了每条通道中的所有引脚，这在这里评审的其他部分中并没有遇到过。🔄

For booting, there are 24 GPIO bootstrap pins that can be pulled (or tied if otherwise unused) high or low to specify all sorts of boot options.
在启动时，有 24 个 GPIO 引导引脚可以拉高或拉低（如果不使用的话可以接地），以指定各种启动选项。🔌
Once you’ve set this up and verified it, you can make these boot configurations permanent with a write to the boot configuration OTP memory (that way, you don’t have to route all those boot pins on production boards).
一旦你设置并验证了这一点，你可以通过写入引导配置的 OTP 内存来使这些引导配置永久生效（这样，你就不必在生产板上连接所有这些引导引脚了）。🔧

Best of all, if you’re trying to get going quickly and don’t want to throw a zillion pull-up/pull-down resistors into your design, there’s an escape hatch: if none of the boot fuses have been programmed and the GPIO pins aren’t set either, the processor will attempt to boot off the first MMC device, which you could, say, attach to a MicroSD card.
最好的是，如果你想快速启动，并且不想在设计中添加一堆上拉/下拉电阻，还有一个逃生口：如果没有任何引导熔丝被编程，并且 GPIO 引脚也没有设置，处理器将会尝试从第一个 MMC 设备启动，你可以将其连接到 MicroSD 卡上。📦
Beautiful! 美丽！😍

Software Workflow 软件工作流程 🛠️

Linux and U-Boot both have had mainline support for this architecture for years. NXP officially supports Yocto, but Buildroot also has support.
Linux 和 U-Boot 多年来都对该架构提供了主线支持。🖥️ NXP 官方支持 Yocto，但 Buildroot 也有支持。🔧
If you want to use the SD/MMC Manufacture Mode option to boot directly off a MicroSD card without fiddling with boot pins or blowing OTP fuses, you’ll have to modify U-Boot. I submitted a patch years ago to the official U-Boot mailing list as well as a pull request to u-boot-fslc, but it’s been ignored. The only other necessary change is to switch over the SDMMC device in the U-Boot mx6ullevk.h port.
如果你想使用 SD/MMC 制造模式选项直接从 MicroSD 卡启动，而不需要调整引导针或熔断一次性可编程熔丝，你需要修改 U-Boot。💻 我几年前在官方 U-Boot 邮件列表上提交了一个补丁，并向 u-boot-fslc 提交了一个拉取请求，但都被忽视了。🚫 唯一另一个必要的更改是切换 U-Boot mx6ullevk.h 端口中的 SDMMC 设备。🔧

Compared to others in this round-up, DTS files for the i.MX 6 are OK.
与本次汇总中的其他产品相比，i.MX 6 的 DTS 文件还不错。👍
They reference a giant header file with every possible pinmux setting predefined, so you can autocomplete your way through the list to establish the mux setting, but you’ll still need to calculate a magical binary number to configure the pin itself (pull-up, pull-down, drive strength, etc).
他们引用了一个巨大的头文件，里面预定义了所有可能的引脚复用设置，因此你可以通过自动补全的方式浏览列表以确定复用设置，但你仍然需要计算一个神奇的二进制数来配置引脚本身（上拉、下拉、驱动强度等）。🔧
Luckily, these can usually be copied from elsewhere (or if you’re moving a peripheral from one set of pins to another, there’s probably no need to change). I still find this way better than DTS files that require you look up the alternate-function number in the datasheet.
幸运的是，这些通常可以从其他地方复制（或者如果你只是将外设从一组引脚移动到另一组，引脚可能不需要更改）。我仍然觉得这种方式比需要查找数据表中替代功能编号的 DTS 文件要好。😊

NXP provides a pinmuxing tool that can automatically generate DTS pinmux code which makes this far less burdensome, but for most projects, I’d imagine you’d be using mostly defaults anyway — with only light modifications to secure an extra UART, I2C, or SPI peripheral, for example.
NXP 提供了一个引脚复用工具，可以自动生成 DTS 引脚复用代码，这大大减轻了工作负担，但对于大多数项目，我想你们还是会主要使用默认配置 —— 例如，仅需轻微修改以确保额外的 UART、I2C 或 SPI 外设。🔧

Windows 10 IoT Core Windows 10 IoT 核心🖥️

The i.MX 6 is the only part I reviewed that has first-party support for Windows 10 IoT Core, and although this is an article about embedded Linux, Windows 10 IoT core competes directly with it and deserves mention.
i.MX 6 是我评测过的唯一一款具有 Windows 10 IoT Core 官方支持的产品，尽管这是一篇关于嵌入式 Linux 的文章，但 Windows 10 IoT Core 与其直接竞争，值得一提。🖥️
I downloaded the source projects which are divided into a Firmware package that builds an EFI-compliant image with U-Boot, and then the actual operating system package.
我下载了源项目，这些项目分为一个固件包，该包构建了一个符合 EFI 标准的映像和 U-Boot，以及实际的操作系统包。📦
I made the same trivial modifications to U-Boot to ensure it correctly boots from the first MMC device, recompiled, copied the new firmware to the board, and Windows 10 IoT core booted up immediately.
我对 U-Boot 进行了相同的微小修改，以确保它能够正确从第一个 MMC 设备启动，重新编译后，将新固件拷贝到板子上，然后 Windows 10 IoT 核心立即启动。🔧

OK, well, not immediately. In fact, it took 20 or 30 minutes to do the first boot and setup. I’m not sure the single-core 900 MHz i.MX 6ULL is the part I would want to use for Windows 10 IoT-based systems; it’s just really, really slow. Once everything was set up, it took more than a minute and a half from when I hit the “Start Debugging” button in Visual Studio to when I landed on my InitializeComponent() breakpoint in my trivial UWP project.
好的，没那么快。实际上，第一次启动和设置花了 20 到 30 分钟。我不确定单核 900 MHz 的 i.MX 6ULL 是否适合用于基于 Windows 10 IoT 的系统；它确实非常非常慢。所有设置完成后，从我在 Visual Studio 中点击“开始调试”按钮到我在简单的 UWP 项目中的 InitializeComponent()断点，花了超过一分钟半的时间。⏳
It looks to be somewhat RAM-starved, so I’d like to re-evaluate on a board that has 2 GB of RAM (the board I was testing just had a 512-MB part mounted).
它似乎有些内存不足，所以我想重新评估一块拥有 2GB 内存的电路板（我测试的电路板只有 512MB 的内存）。💻

Allwinner A33 全志 A33 🖥️

Our third and final Allwinner chip in the round-up is an older quad-core Cortex-A7 design. I picked this part because it has a sensible set of peripherals for most embedded development, as well as good support in Mainline Linux.
我们本次总结的第三款也是最后一款 Allwinner 芯片是一款较老的四核 Cortex-A7 设计。🔍 我选择这款芯片是因为它具备大多数嵌入式开发所需的合理外设，并且在主线 Linux 中有良好的支持。💻
I also had a pack of 10 of them laying around that I had purchased years ago and never actually tried out.
我还有一包 10 个的它们闲置在那儿，是我几年前买的却从未真正尝试过。📦

This part, like all the other A-series parts, was designed for use in Android tablets — so you’ll find Arm Mali-based 3D acceleration, hardware-accelerated video decoding, plus LVDS, MIPI and parallel RGB LCD support, a built-in audio codec, a parallel camera sensor interface, two USB HS ports, and three MMC peripherals — an unusually generous complement.
这一部分与所有其他 A 系列部件一样，旨在用于 Android 平板电脑——因此您会发现基于 Arm Mali 的 3D 加速、硬件加速的视频解码、LVDS、MIPI 和并行 RGB LCD 支持、内置音频编码器、并行摄像头传感器接口、两个 USB HS 端口，以及三个 MMC 外设——这是一种特别慷慨的配置。🎉

There’s an open-source effort to get hardware video decoding working on these parts. They currently have MPEG2 and H264 decoding working. While I haven’t had a chance to test it on the A33, this is an exciting development — it makes this the only part in this round-up that has a functional hardware video decoder.
目前有一个开源项目正在努力使这些硬件的视频解码工作。🎥他们目前已经实现了 MPEG2 和 H264 的解码。🎞️虽然我还没有机会在 A33 上进行测试，但这是一个令人兴奋的发展——这使得它成为此次汇总中唯一具有功能性硬件视频解码器的部件。✨

Additionally, you’ll find a smattering of lower-speed peripherals: two basic PWM channels, six UARTs, two I2S interfaces, two SPI controllers, four I2C controllers, and a single ADC input. The biggest omission is the Ethernet MAC.
此外，你会发现一些低速外设：两个基本 PWM 通道、六个 UART、两个 I2S 接口、两个 SPI 控制器、四个 I2C 控制器和一个 ADC 输入。最大的问题是缺少以太网 MAC。🔌

This and the i.MX 6 are the only two parts in this round-up that can address a full 2 GB of memory (via two separate banks). I had some crazy-expensive dual-die 2 GB dual-rank DDR memory chips laying around that I used for this.
这款和 i.MX 6 是此次汇总中唯一可以支持 2 GB 内存（通过两个独立内存银行）的两个部件。😊 我有一些非常昂贵的双芯片 2 GB 双排 DDR 内存条，用于这个。💰
You can buy official-looking A33 dev boards from Taobao, but I picked up a couple Olimex A33-OLinuXino boards to play with. These are much better than some of the other dev boards I’ve mentioned, but I still wish the camera CSI / MIPI signals weren’t stuck on an FFC connector.
你可以在淘宝上购买看起来官方的 A33 开发板，但我选择了一些 Olimex A33-OLinuXino 开发板来玩玩。🎮 这些开板比我提到过的其他一些开发板要好得多，但我仍然希望相机的 CSI / MIPI 信号没有绑定在 FFC 连接器上。📷

Hardware Design 硬件设计 🛠️

The A33 has four different voltage rails it needs, which starts to move the part up into PMIC territory. The PMIC of choice for the A33 is the AXP223.
A33 需要四个不同的电压轨，这使得它开始进入 PMIC 的领域。 🤖 A33 选择的 PMIC 是 AXP223。 ⚡️
This is a great PMIC if you’re building a portable battery-powered device, but it’s far too complicated for basic always-on applications. It has 5 DC/DC converters, 10 LDO outputs, plus a lithium-ion battery charger and power-path switching capability.
如果你正在构建一个便携式电池供电的设备，这是一款很棒的 PMIC，但对于基本的常开应用来说，它实在是太复杂了。😊 它有 5 个 DC/DC 转换器，10 个 LDO 输出，还有一个锂离子电池充电器和电源路径切换功能。🔋

After studying the documentation carefully, I tried to design around it in a way that would allow me to bypass the DC/DC-converter battery charger to save board space and part cost. When I got the board back, I spent a few hours trying to coax the chip to come alive, but couldn’t get it working in the time I had set aside.
在仔细研究文档后，我尝试设计一种方法，绕过 DC/DC 转换器的电池充电器，以节省板子的空间和零件成本。📏 当我收回电路板时，我花了几个小时试图唤醒芯片，但在我预留的时间内未能让它正常工作。⏲️

Anticipating this, I had designed and sent off a discrete regulator version of the board as well, and that board booted flawlessly.
考虑到这一点，我还设计并发送了一版离散调节器的电路板，而那块电路板启动完美无缺。✨
To keep things simple on that discrete version, I used the same power trick with the A33 as I did on the i.MX 6, AM3358, and STM32MP1: I ran both the core and memory off a single 1.35V supply.
为了使离散版本简单，我使用了与 i.MX 6、AM3358 和 STM32MP1 相同的电源技巧：我让核心和内存都由一个 1.35V 的电源供电。⚡️
There was a stray VCC_DLL pin that needed to be supplied with 2.5V, so I added a dedicated 2.5V LDO. The chip runs pretty hot when maxing out the CPU, and I don’t think running VDD_CPU and VDD_SYS (which should be 1.1V) at 1.35V is helping.
有一个孤立的 VCC_DLL 引脚需要供电 2.5V，所以我添加了一个专用的 2.5V LDO。🥵 当 CPU 达到最大负载时，芯片会运行得相当热，我认为将 VDD_CPU 和 VDD_SYS（应该是 1.1V）运行在 1.35V 并没有帮助。💡

The audio codec requires extra bypassing with 10 uF capacitors on several bias pins which adds a bit of extra work, but not even the USB HS transceivers need an external bias resistor, so other than the PMIC woes, the hardware design went together smoothly.
音频编码解码器在多个偏置引脚上需要额外的 10 微法法电容旁路，这增加了一些额外工作，但连 USB HS 收发器都不需要外部偏置电阻，所以除了 PMIC 的问题，硬件设计进行得很顺利。🔧

Fan-out on the A33 is beautiful: power pins are in the middle, signal pins are in the 4 rows around the outside, and the DDR bus pinout is organized nicely.
A33 的引脚分布非常美观：电源引脚位于中间，信号引脚则排列在外面的四排，DDR 总线的引脚布局也很整齐。✨
There is a column-long ball depopulation in the middle that gives you extra room to place capacitors without running into vias.
中间有一个长柱状的球形去人口，给你额外的空间放置电容器而不必碰到过孔。⚡️
There are no boot pins (the A33 simply tries each device sequentially, starting with MMC0), and there are no extraneous control / enable signals other than a reset and NMI line.
没有引导引脚（A33 仅依次尝试每个设备，从 MMC0 开始），除复位和 NMI 线外，没有额外的控制/使能信号。🔌

Software 软件 🖥️

The A33 OLinuXino defconfig in Buildroot, U-Boot, and Linux is a great jumping-off place.
A33 OLinuXino 在 Buildroot、U-Boot 和 Linux 中的 defconfig 是一个很好的起点。🚀
I disabled the PMIC through U-Boot’s menuconfig (and consequently, the AXP GPIOs and poweroff command), and added a dummy regulator for the SDMMC port in the DTS file, but otherwise had no issues booting into Linux.
我通过 U-Boot 的 menuconfig 禁用了 PMIC（因此，AXP GPIO 和关机命令也被禁用），并在 DTS 文件中为 SDMMC 端口添加了一个虚拟稳压器，但在启动 Linux 时没有遇到其他问题。🔧
I had the card-detect pin connected properly and didn’t have a chance to test whether or not the boot ROM will even attempt to boot from MMC0 if the CD line isn’t low.
我已经正确连接了卡检测引脚，但没有机会测试如果 CD 线不低，启动 ROM 是否会尝试从 MMC0 启动。📌

Once you’re booted up, there’s not much to report. It’s an entirely stock Linux experience. Mainline support for the Allwinner A33 is pretty good — better than almost every other Allwinner part — so you shouldn’t have issues getting basic peripherals working.
一旦启动后，没什么特别需要报告的。😊 这完全是一个标准的 Linux 体验。🌟 Allwinner A33 的主流支持相当不错——比几乎所有其他 Allwinner 部件都要好——所以你应该不会在使用基本外设时遇到问题。👍

Whenever I have to modify an Allwinner DTS file, I’m reminded how much nicer these are than basically every other part in this review.
每当我需要修改一个 Allwinner DTS 文件时，我就会想起这些文件比这篇评测中的其他部分要好得多。💻
They use simple string representations for pins and functions, with no magic bits to calculate or datasheet look-ups for alternate-function mapping; the firmware engineer can modify the DTS files looking at nothing other than the part symbol on the schematic.
他们使用简单的字符串表示针对引脚和功能，没有魔法位来计算或查阅数据表进行备用功能映射；固件工程师只需查看原理图上的部件符号即可修改 DTS 文件。🔧

Texas Instruments AM335x/AMIC110
德州仪器 AM335X/AMIC110

The Texas Instruments Sitara AM335x family is TI’s entry-level range of MPUs introduced in 2011. These come in 300-, 600-, 800-, and 1000-MHz varieties, and two features — integrated GPU and programmable real-time units (PRU) — set them apart from other parts reviewed here.
德州仪器的 Sitara AM335x 系列是 TI 在 2011 年推出的入门级 MPU。这些型号有 300MHz、600MHz、800MHz 和 1000MHz 的不同版本，两个特点——集成 GPU 和可编程实时单元（PRU）——使它们在这里审核的其他部件中脱颖而出。📈

I reviewed the 1000-MHz version of the AM3358, which is the top-of-the-line SGX530 GPU-enabled model in the family. From TI Direct, this part rings in at $11.62 @ 100 qty, which is a reasonable value given that this is one of the more featureful parts in the roundup.
我审查了 1000-MHz 版本的 AM3358，这是该系列中顶级的 SGX530 GPU-enabled 型号。💻 从 TI Direct 来看，这个部件的价格为每 100 个数量 11.62 美元，这在考虑到这是此次回顾中功能最齐全的部件之一时是一个合理的价值。💰

These Sitara parts are popular — they’re found in Siglent spectrum analyzers (and even bench meters), the (now defunct) Iris 2.0 smart home hub, the Sense Energy monitor, the Form 2 3D printer, plus lots of low-volume industrial automation equipment.
这些 Sitara 部件非常受欢迎——它们出现在 Siglent 的频谱分析仪（甚至是台式仪表）、已经停产的 Iris 2.0 智能家居中心、Sense Energy 监测仪、Form 2 3D 打印机，以及许多低产量的工业自动化设备中。📊

In addition to all the AM335x chips, there’s also the AMIC110 — a newer, cheaper version of the AM3352. This appears to be in the spirit of the i.MX 6ULZ — a stripped-down version optimized for low-cost IoT devices.
除了所有的 AM335x 芯片，还有 AMIC110——AM3352 的一个更新、更便宜的版本。💰这看起来是在追随 i.MX 6ULZ 的精神——一个为低成本物联网设备优化的简化版本。📦
I’m not sure it’s a great value, though: while having identical peripheral complements, the i.MX 6ULZ runs at 900 MHz while the AMIC110 is limited to 300. The AMIC110 is also 2-3 times more expensive than the i.MX 6ULZ. Hmm.
我不确定这是否是一个很好的价值：虽然具有相同的外围设备配置，但 i.MX 6ULZ 的运行频率为 900 MHz，而 AMIC110 限制在 300 MHz。🤔 AMIC110 的价格也比 i.MX 6ULZ 贵 2-3 倍。💰 嗯。

There’s a standard complement of comms peripherals: three MMC ports (more than every other part except the A33), 6 UARTs, 3 I2Cs, 2 SPI, 2 USB HS and 2 CAN peripherals.
有一套标准的通信外设：三个 MMC 端口（比其他所有部分还要多，除了 A33），6 个 UART，3 个 I2C，2 个 SPI，2 个 USB HS 和 2 个 CAN 外设。🔌
The part has a 24-bit parallel RGB LCD interface, but oddly, it was the only device in this round-up that lacks a parallel camera interface.((Apparently Radium makes a parallel camera board for the BeagleBone that uses some sort of bridge driver chip to the GPMC, but this is definitely a hack.))
该部件拥有 24 位并行 RGB 液晶显示接口，但奇怪的是，它是这次测评中唯一没有并行相机接口的设备。📸（显然，Radium 为 BeagleBone 制作了一款并行相机板，使用某种桥接驱动芯片与 GPMC 连接，但这绝对算是一个外挂。💻）

The Sitara has some industrial-friendly features: an 8-channel 12-bit ADC, three PWM modules (including 6-output bridge driver support), three channels of hardware quadrature encoder decoding, and three capture modules.
Sitara 具备一些工业友好的特性：8 通道 12 位 ADC，三个 PWM 模块（包括 6 输出的桥接驱动支持），三个硬件正交编码器解码通道，以及三个捕获模块。🔧
While parts like the STM32MP1 integrate a Cortex-M4 to handle real-time processing tasks, the AM335x uses two proprietary-architecture Programmable Real-Time Unit (PRU) for these duties.
虽然像 STM32MP1 这样的部件集成了 Cortex-M4 来处理实时处理任务，但 AM335x 则使用两个专有架构的可编程实时单元（PRU）来完成这些工作。🔧

I only briefly played around with this capability, and it seems pretty half-baked. TI doesn’t seem to provide an actual peripheral library for these parts — only some simple examples.
我只简单体验了一下这个功能，感觉它还不够成熟。德州仪器似乎并没有为这些部件提供真正的外设库——只有一些简单的例子。🛠️
If I wanted to run something like a fast 10 kHz current-control loop with a PWM channel and an ADC, the PRU seems like it’d be perfect for the job — but I have no idea how I would actually communicate with those peripherals without dusting off the technical reference manual for the processor and writing the register manipulation code by hand.
如果我想运行类似于快速 10 kHz 电流控制循环的程序，使用一个 PWM 通道和一个 ADC，PRU 似乎非常适合这个任务——但我完全不知道如何实际与这些外设进行通信，而不必翻阅处理器的技术参考手册并手动编写寄存器操作代码。💻

It seems like TI is focused pretty heavily on EtherCAT and other Industrial Ethernet protocols as application targets for this processor; they have PRU support for these protocols, plus two gigabit Ethernet MACs (the only part in this round-up with that feature) with an integrated switch.
看起来 TI 非常关注 EtherCAT 和其他工业 Ethernet 协议作为该处理器的应用目标；他们为这些协议提供了 PRU 支持，以及两个千兆 Ethernet MAC（在这个汇总中唯一具有该特性的部分）和一个集成交换机。🔧

A huge omission is security features: the AM335x has no secure boot capabilities and doesn’t support TrustZone.
一个巨大的遗漏是安全功能：AM335x 没有安全启动能力，也不支持 TrustZone。🔒
Well, OK, the datasheet implies that it supports secure boot if you engage with TI to obtain custom parts from them — presumably mask-programmed with keys and boot configuration.
好吧，说明书暗示，如果你与德州仪器（TI）合作获取他们的定制零件，就可以支持安全启动——推测是用密钥和启动配置进行掩模编程的。🔑
Being even more presumptuous, I’d hypothesize that TI doesn’t have any OTP fuse technology at their disposal; you’d need this to store keys and boot configuration data (they use GPIO pins to configure boot).
我甚至可以大胆假设，德州仪器（TI）没有任何一次性可编程（OTP）保险丝技术可供使用；你需要这个来存

Hardware Design 硬件设计 💻

When building up schematics, the first thing you’ll notice about the AM335x is that this part is in dire need of some on-chip voltage regulation (in the spirit of the i.MX 6 or STM32MP1).
在构建原理图时，您首先会注意到 AM335x 这一部分在芯片上急需一些电压调节（参考 i.MX 6 或 STM32MP1 的设计）。⚡
There are no fewer than 5 different voltages you’ll need to supply to the chip to maintain spec: a 1.325V-max VDD_MPU supply, a 1.1V VDD_CORE supply, a 1.35 or 1.5V DDR supply, a 1.8V analog supply, and a 3.3V I/O supply.
为了满足规格，您需要向芯片提供不少于 5 种不同的电压：一个 1.325V 的最大 VDD_MPU 电源，一个 1.1V 的 VDD_CORE 电源，一个 1.35 或 1.5V 的 DDR 电源，一个 1.8V 的模拟电源，以及一个 3.3V 的 I/O 电源。⚡️

My first effort was to combine the MPU, CORE, and DDR rails together as I did with the previous two chips.
我第一次尝试将 MPU、CORE 和 DDR 电源轨道结合在一起，就像我之前对待两个芯片时一样。🔗
However, the AM335x datasheet has quite specific power sequencing requirements that I chose to ignore, and I had issues getting my design to reliably startup without some careful sequencing (for discrete-regulator inspiration, check out Olimex’s AM335x board).
然而，AM335x 数据表有非常具体的电源顺序要求，而我选择忽视了这些要求，因此在没有经过仔细的顺序控制的情况下，我的设计在启动时出现了一些问题（有关离散调节器的灵感，请查看 Olimex 的 AM335x 开发板）。⚡

I can’t recommend using discrete regulators for this part: my power consumption is atrocious and the BOM exploded with the addition of a POR supervisor, a diode, transistor, different-value RC circuits — plus all the junk needed for the 1.35V buck converter and two linear regulators.
我不建议在这个部分使用单独的稳压器：我的功耗非常糟糕，添加了一个 POR 监控器、一个二极管、一个晶体管、不同值的 RC 电路后，物料清单也随之暴涨——还有用于 1.35V 降压转换器和两个线性稳压器所需的所有杂七杂八的东西。💡
This is not the way you should be designing with this part — it really calls for a dedicated PMIC that can properly sequence the power supplies and control signals.
这并不是你该如何设计这个零件的方式——它确实需要一个专用的 PMIC，能够正确地顺序控制电源和控制信号。🔌

Texas Instruments maintains an extensive PMIC business, and there are many supported options for powering the AM335x — selecting a PMIC involves figuring out if you need dual power-supply input capability, Lithium-Ion battery charging, and extensive LDO or DC/DC converter additions to power other peripherals on your board.
德州仪器拥有广泛的电源管理集成电路（PMIC）业务，并提供多种支持选项来为 AM335x 供电——选择 PMIC 时需要考虑是否需要双电源输入功能、锂离子电池充电，以及为板上的其他外设提供额外的低压差稳压器（LDO）或 DC/DC 转换器。⚡️
For my break-out board, I selected the TPS65216, which was the simplest PMIC that Texas Instruments recommended using with the AM335x. There’s an app notes suggesting specific hook-up strategies for the AM335x, but no exact schematics were provided. In my experience, even the simplest Texas Instruments power management chips are overly complicated to design around, and I’m not sure I’ve ever nailed the design on the first go-around (this outing was no different).
对于我的扩展板，我选择了 TPS65216，这是德州仪器推荐与 AM335x 一起使用的最简单的 PMIC。📋 有应用笔记建议了 AM335x 的特定连接策略，但没有提供确切的原理图。📐 根据我的经验，即使是德州仪器最简单的电源管理芯片，在设计时也过于复杂，我不确定是否曾经一次性成功完成设计（这次也没有例外）。🛠️

There’s also a ton of control signals: in addition to internal 1.8V regulator and external PMIC enable signals — along with NMI and EXT_WAKEUP input — there are no fewer than three reset pins (RESET_INOUT, PWRONRST, and RTC_PWRONRST).
还有大量的控制信号：除了内部 1.8V 调节器和外部 PMIC 使能信号外——以及 NMI 和 EXT_WAKEUP 输入——至少还有三个复位引脚（RESET_INOUT，PWRONRST 和 RTC_PWRONRST）。🔌

In addition to power and control signals, booting on the Sitara is equally clunky.
除了电源和控制信号，Sitara 的启动过程同样繁琐。⚙️
There are 16 SYSBOOT signals multiplexed onto the LCD data bus used to select one of 8 different boot priority options, along with main oscillator options (the platform supports 24, 25, 26 and 19.2 MHz crystals).
有 16 个 SYSBOOT 信号复用到 LCD 数据总线上，用于选择 8 种不同的启动优先级选项，以及主振荡器选项（该平台支持 24、25、26 和 19.2 MHz 的晶体）。📊
With a few exceptions, the remaining nine pins are either “don’t care” or required to be set to specific values regardless of the options selected.
除了少数例外，其余九个引脚要么是“无所谓”，要么必须设置为特定值，不管选择了什么选项。🔌
I like the flexibility to be able to use 25 MHz crystals for Ethernet-based designs (or 26 MHz for wireless systems), but I wish there was also a programmable fuse set or other means of configuring booting that doesn’t rely on GPIO signals.
我喜欢能够在基于以太网的设计中使用 25 MHz 的晶体（或者在无线系统中使用 26 MHz 的晶体）的灵活性，但我希望还有其他可编程熔断器或配置启动的方式，而不依赖于 GPIO 信号。🔧

Overall, I found that power-on boot-up is much more sensitive on this chip than anything I’ve ever used before.
总体而言，我发现这个芯片的开机启动比我以前使用过的任何设备都要敏感得多。⚡
Misplacing a 1k resistor in place of a 10k pull-up on the processor’s reset signal caused one of my prototypes to fail to boot — the CPU was coming out of reset before the 3.3V supply had come out of reset, so all the SYSBOOT signals were read as 0s.
将一个 1k 电阻错误地放在处理器复位信号的 10k 上拉电阻位置，导致我的一个原型无法启动——CPU 在 3.3V 供电恢复之前就已经复位，因此所有的 SYSBOOT 信号都被读取为 0。💡

Other seemingly simple things will completely wreak havoc on the AM335x: I quickly noticed my first prototype failed to start up whenever I have my USB-to-UART converter attached to the board — parasitic current from the idle-high TX pin will leak into the processor’s 3.3V rail and presumably violate a power sequencing spec that puts the CPU in a weird state or something.
其他看似简单的事情会对 AM335x 造成完全的混乱：我很快发现我的第一个原型在连接 USB 转 UART 转换器时无法启动——处于高电平闲置状态的 TX 引脚的寄生电流会泄漏到处理器的 3.3V 电源线上，并可能违反电源顺序规范，使 CPU 进入一个奇怪的状态或其他情况。⚠️
There’s a simple fix — a current-limiting series resistor — but these are the sorts of problems I simply didn’t see from any other chip reviewed. This CPU just feels very, very fragile.
有一个简单的解决办法——一个限流的串联电阻——但这些问题是我在其他任何评测的芯片上都没有见过的。这个 CPU 感觉非常非常脆弱。⚡

Things don’t get any better when moving to DDR layout. TI opts for a non-standard 49.9-ohm ZQ termination resistance, which will annoyingly add an entirely new BOM line to your design for no explicable reason.
在转换到 DDR 布局时，情况并没有变得更好。 ⚠️ TI 选择了一个非标准的 49.9 欧姆 ZQ 终端电阻，这会令人烦恼地为你的设计新增一条完全没有说明理由的物料清单。 📋
The memory controller pinout contains many crossing address/command nets regardless of the memory IC orientation, making routing slightly more annoying than the other parts in this review. And while there’s a downloadable IBIS model, a warning on their wiki states that “TI does not support timing analysis with IBIS simulations.” As a result, there’s really no way to know how good your timing margins are.
内存控制器引脚分配包含许多交叉的地址/命令网络，无论内存 IC 的方向如何，这使得布线相较于本次评测中的其他部分稍显麻烦。🛠️ 尽管有可下载的 IBIS 模型，但他们的维基上有警告指出：“TI 不支持使用 IBIS 模拟进行时序分析。”⚠️ 因此，实际上无法知道你的时序余量有多好。📉

That’s par for the course if you’re Allwinner or Rockchip, but this is Texas Instruments — their products are used in high-reliability aerospace applications by engineers who lean heavily on simulation, as well as in specialty applications where you can run into complex mechanical constraints that force you into weird layouts that work on the margins and should be simulated.
这对全志或瑞芯微来说是很正常的，但这是德州仪器 —— 他们的产品被工程师用于高可靠性航空航天应用，这些工程师在设计时非常依赖仿真，同时也适用于那些可能会遇到复杂机械约束的特殊应用，这些约束迫使你采用边缘工作且需要被仿真的奇怪布局。✈️

There’s really only one good thing I can say about the hardware design: the part has one of the cleanest ball-outs I saw in this round-up. The power supply pins seem to be carefully placed to allow escaping on a single split plane — something that other CPUs don’t handle as well.
我唯一能说关于这个硬件设计的好处就是：这个部件的引脚布局在这一轮评测中是最整洁的之一。电源引脚似乎被仔细放置，以便在单一分裂层上逃离——这是其他 CPU 处理得不太好的一点。🔌
There’s plenty of room under the 0.8mm-pitch BGA for normal-sized 0402 footprints. Power pins are centralized in the middle of the IC and all I/O pins are in the outer 4 rows of balls.
在 0.8mm 间距的 BGA 下，有足够的空间容纳正常尺寸的 0402 封装。电源引脚集中在集成电路的中间，所有 I/O 引脚则位于外侧的四排球中。🔌
Peripherals seem to be located reasonably well in the ball-out, and I didn’t encounter many crossing pins.
外围设备似乎在引脚布局中位置合理，我没有遇到太多交叉引脚。🔌

Software Design 软件设计 💻

Texas Instruments provides a Yocto-derived Processor SDK that contains a toolchain plus a prebuilt image you can deploy to your EVK hardware. They have tons of tools and documentation to help you get started — and you’ll be needing it.
德州仪器提供了一个基于 Yocto 的处理器 SDK，其中包含一个工具链以及一个可以部署到你的 EVK 硬件上的预构建镜像。🛠️他们有大量的工具和文档来帮助你入门——你会需要这些。📚

Porting U-Boot to work with my simple breakout board was extremely tedious.
将 U-Boot 移植到我的简单扩展板上是非常繁琐的。😩
TI doesn’t enable early serial messages by default, so you won’t get any console output until after your system is initialized and the SPL turns things over to U-Boot Proper, which is way too late for bringing up new hardware. TI walks you through how to enable early debug UART on their Processor SDK documentation page, but there’s really no reason this should be disabled by default.
TI 默认情况下不启用

It turns out my board wasn’t booting up because it was missing an I2C EEPROM that TI installs on all its EVKs so U-Boot can identify the board it’s booting from and load the appropriate configuration.
原来我的开发板没有启动是因为缺少一个 I2C EEPROM，而德州仪器在所有的评估板（EVK）上都会安装这个，以便 U-Boot 能够识别启动的开发板并加载适当的配置。💻
This is an absolutely bizarre design choice; for embedded Linux developers, there’s little value in being able to use the same U-Boot image in different designs — especially if we have to put an EEPROM on each of our boards for this sole purpose.
这是一个绝对奇怪的设计选择；对于嵌入式 Linux 开发者来说，在不同的设计中使用相同的 U-Boot 镜像几乎没有什么价值——尤其是如果我们必须在每个板子上都装一个 EEPROM 来实现这一目的。🤖

This design choice is the main reason that makes the AM335x U-Boot code so clunky to work through — rather than have a separate port for each board, there’s one giant board.c file with tons of switch-case statements and conditional blocks that check if you’re a BeagleBone, a BeagleBone Black, one of the other BeagleBone variants (why are there so many?), the official EVM, the EVM SK, or the AM3359 Industrial Communication Engine dev board. Gosh.
这种设计选择是导致 AM335x U-Boot 代码如此笨重的主要原因——与其为每块板创建一个单独的端口，不如有一个包含大量 switch-case 语句和条件块的巨大 board.c 文件，这些语句检查你是 BeagleBone、BeagleBone Black，还是其他 BeagleBone 变种（为什么有这么多？）、官方的 EVM、EVM SK 或 AM3359 工业通信引擎开发板。天哪。😅

In addition to working around the EEPROM code, I had to hack the U-Boot environment a bit to get it to load the correct DTB file (again, since it’s a universal image, it’s built to dynamically probe the current target and load the appropriate DTB, rather than storing it as a simple static environmental variable).
除了处理 EEPROM 代码之外，我还必须稍微修改 U-Boot 环境，以使其加载正确的 DTB 文件（再次强调，由于这是一个通用映像，所以它被构建为动态探测当前目标并加载适当的 DTB，而不是将其作为一个简单的静态环境变量存储）。🔧

While the TPS65216 is a recommended PMIC for the AM335x, TI doesn’t actually have built-in support for it in their AM335x U-Boot port, so you’ll have to do a bit of copying and pasting from other ports in the U-Boot tree to get it running — and you’ll have to know the little secret that the TPS65216 has the same registers and I2C address as the older TPS65218; that’s the device driver you’ll have to use.
虽然 TPS65216 是 AM335x 推荐使用的电源管理集成电路（PMIC），但 TI 在他们的 AM335x U-Boot 移植中实际上并没有内置支持它，所以你需要从 U-Boot 树中的其他移植中复制和粘贴一些代码才能让它运行——而且你需要知道一个小秘密：TPS65216 具有与旧款 TPS65218 相同的寄存器和 I2C 地址；这就是你需要使用的设备驱动程序。 📦

Once U-Boot started booting Linux, I was greeted by…. nothing. It turns out early in the boot process the kernel was hanging on a fault related to a disabled RTC. Of course, you wouldn’t know that, since, in their infinite wisdom, TI doesn’t enable earlyprintk either, so you’ll just get a blank screen. At this point, are you even surprised?
一旦 U-Boot 开始启动 Linux，我看到的是……什么都没有。😶‍🌫️ 结果在启动过程的早期，内核因为一个与被禁用的 RTC 相关的错误而挂起。🛑 当然，你不会知道这一点，因为在他们无尽的智慧下，TI 也没有启用 earlyprintk，所以你只能看到一片空白的屏幕。📺 在这一点上，你还会感到惊讶吗？🤔

Once I got past that trouble, I was finally able to boot into Linux to do some benchmarking and playing around. I didn’t encounter any oddities or unusual happenings once I was booted up.
一旦我解决了那个问题，我终于能够启动 Linux 进行一些基准测试和玩耍。💻 当我启动后没有遇到任何奇怪的事情或异常情况。😊

I’ve looked at the DTS files for each part I’ve reviewed, just to see how they handle things, and I must say that the DTS files on the Texas Instruments parts are awful.
我查看了我所评审的每个部分的 DTS 文件，仅仅是想看看它们是如何处理事情的，我必须说，德州仪器的 DTS 文件真糟糕。😩
Rather than using predefined macros like the i.MX 6 — or, even better, using human-readable strings like the Allwinner parts — TI fills the DTS files with weird magic numbers that get directly passed to the pinmux controller. The good news is they offer an easy-to-use TI PinMux Tool that will automatically generate this gobbledygook for you. I’m pretty sure a 1 GHz processor is plenty capable of parsing human-readable strings in device tree files, and there are also DT compiler scripts that should be able to do this with some preprocessor magic.
与其使用像 i.MX 6 这样的预定义宏 - 或者更好的是，像 Allwinner 组件使用可读字符串 - 德州仪器在 DTS 文件中填充了奇怪的魔法数字，这些数字直接传递给引脚复用控制器。😮 好消息是，他们提供了一个易于使用的 TI PinMux 工具，可以自动为你生成这些杂乱无章的字符串。🛠️ 我相信 1 GHz 的处理器完全可以解析设备树文件中的可读字符串，并且还有一些 DT 编译器脚本应该能够用一些预处理器魔法来做到这一点。🌟
They could have at least had pre-defined macros like NXP does.
他们至少可以像 NXP 那样有预定义的宏。😊

STM32MP1 STM32MP1 🌟

The STM32MP1 is ST’s entry into Cortex-A land, and it’s anything but a tip-toe into the water. These Cortex-A7 parts come in various core count / core speed configurations that range from single-core 650 MHz to dual-core 800 MHz + Cortex-M4 + GPU.
STM32MP1 是 ST 进入 Cortex-A 领域的产品，绝不是小心翼翼地试水🐾。这些 Cortex-A7 部件拥有多种核心数量/核心速度配置，从单核 650 MHz 到双核 800 MHz + Cortex-M4 + GPU 不等💻。

These are industrial controls-friendly parts that look like high-end STM32F7 MCUs: 29 timers (including the usual STM32 advanced control timers and quadrature encoder interfaces), 16-bit ADCs running up to 4.5 Msps, DAC, a bunch of comms peripherals (plenty of UART, I2C, SPI, along with I2S / SPDIF).
这些是适合工业控制的高端 STM32F7 MCU 风格的元件：29 个定时器（包括常见的 STM32 高级控制定时器和正交编码器接口），16 位 ADC 可运行高达 4.5Msps，DAC，还有一堆通信外设（丰富的 UART、I2C、SPI，以及 I2S / SPDIF）。🛠️

But they also top out the list of parts I reviewed in terms of overall MPU-centric peripherals, too: three SDIO interfaces, a 14-bit-wide CSI, parallel RGB888-output LCD interface, and even a 2-lane MIPI DSI output (on the GPU-enabled models).
但它们在我审查的整体以 MPU 为中心的外设中同样名列前茅：三个 SDIO 接口，一个 14 位宽的 CSI，平行 RGB888 输出 LCD 接口，甚至还有一个 2 通道 MIPI DSI 输出（在启用 GPU 的型号上）。📊

The -C and -F versions of these parts have Secure Boot, TrustZone, and OP-TEE support, so they’re a good choice for IoT applications that will be network-connected.
这些部件的 -C 和 -F 版本支持安全启动、TrustZone 和 OP-TEE，因此它们是适合网络连接的物联网应用的不错选择。🔒

Each of these processors can be found in one of four different BGA packages. For 0.8mm-pitch fans, there are 18x18mm 448-pin and 16x16mm 354-pin options. If you’re space-constrained, ST makes a 12×12 361-pin and 10x10mm 257-pin 0.5mm-pitch option, too.
每个处理器均可在四种不同的 BGA 封装中找到。对于 0.8mm 间距的风扇，有 18x18mm 的 448 脚和 16x16mm 的 354 脚选项。如果您的空间有限，ST 还提供 12×12 的 361 脚和 10x10mm 的 257 脚的 0.5mm 间距选项。📦
The 0.5mm packages have tons of depopulated pads (and actually a 0.65mm-pitch interior grid), and after looking carefully at it, I think it might be possible to fan-out all the mandatory signals without microvias, but it would be pushing it. Not being a sadomasochist, I tested the STM32MP157D in the 354-pin 0.8mm-pitch flavor.
这个 0.5mm 封装有大量去除的焊盘（实际上具有 0.65mm 间距的内部网格），仔细观察后，我认为有可能在没有微孔的情况下将所有必要信号排出，但这会有点勉强。出于对自己不施虐待，我在 354 引脚的 0.8mm 间距版本上测试了 STM32MP157D。💻

Hardware Design 硬件设计 🛠️

When designing the dev board for the STM32MP1, ST really missed the mark. Instead of a Nucleo-style board for this MCU-like processor, ST offers up two fairly-awful dev boards: the $430 EV1 is a classic overpriced large-form-factor embedded prototyping platform with tons of external peripherals and connectors present.
在为 STM32MP1 设计开发板时，ST 真的错失了良机。😞 他们没有为这个类似 MCU 的处理器提供 Nucleo 风格的开发板，而是推出了两个相当糟糕的开发板：430 美元的 EV1 是一个经典的价格过高的大型嵌入式原型平台，配备了大量的外部外设和连接器。💻

But the $60 DK1 is really where things get offensive: it’s a Raspberry Pi form-factor SBC design with a row of Arduino pins on the bottom, an HDMI transmitter, and a 4-port USB hub.
但是这款 60 美元的 DK1 真的是让人感到冒犯的地方：它是一款树莓派规格的单板计算机设计，底部有一排 Arduino 引脚，配备 HDMI 发射器和 4 个 USB 端口的集线器。💻
Think about that: they took a processor with almost 100 GPIO pins designed specifically for industrial embedded Linux work and broke out only 46 of those signals to headers, all to maintain a Raspberry Pi / Arduino form factor.
想想看：他们使用了一个几乎有 100 个 GPIO 引脚的处理器，这个处理器是专门为工业嵌入式 Linux 工作设计的，但仅将其中 46 个信号引出到接头，所有这些都是为了保持 Raspberry Pi / Arduino 的形状尺寸。🔧

None of the parallel RGB LCD signals are available, as they’re all routed directly into an HDMI transmitter (for the uninitiated, HDMI is of no use to an embedded Linux developer, as all LCDs use parallel RGB, LVDS, or MIPI as interfaces).
所有并行 RGB LCD 信号均不可用，因为它们都直接连接到 HDMI 传输器（对于不熟悉的人来说，HDMI 对嵌入式 Linux 开发者无用，因为所有 LCD 都使用并行 RGB、LVDS 或 MIPI 作为接口）。📺
Do they seriously believe that anyone is going to hook up an HDMI monitor, keyboard, and mouse to a 650 MHz Cortex-A7 with only 512 MB of RAM and use it as some sort of desktop Linux / Raspberry Pi alternative?
他们真的相信有人会将 HDMI 显示器、键盘和鼠标连接到只有 512 MB RAM 的 650 MHz Cortex-A7 上，并将其用作某种桌面 Linux / Raspberry Pi 替代品吗？🖥️

Luckily, this part was one of the easiest Cortex-A7s to design around in this round-up, so you should have no issue spinning a quick prototype and bypassing the dev board altogether.
幸运的是，在这次综述中，这一部分是设计 Cortex-A7 中最简单的，所以您应该能毫不费力地快速制作原型，并完全绕过开发板。😊
Just like the i.MX 6, I was able to power the STM32MP1 with nothing other than a 3.3V and 1.35V regulator; this is thanks to several internal LDOs and a liberal power sequencing directive in the datasheet.((With one caution I glanced past: the 3.3V USB supply has to come up after the 1.8V supply does, which is obviously impossible when using the internal 1.8V regulator. ST suggests using a dedicated 3.3V LDO or P-FET to power-gate the 3.3V USB supply.))
就像 i.MX 6 一样，我能够仅使用 3.3V 和 1.35V 稳压器来为 STM32MP1 供电；这得益于多个内部 LDO 和数据手册中宽松的电源排序指令。⚡️（有一个警告我略过了：3.3V 的 USB 电源必须在 1.8V 电源之后上升，使用内部 1.8V 稳压器时显然是不可能的。ST 建议使用专用的 3.3V LDO 或 P-FET 来为 3.3V USB 供电门控。）🔌

There’s a simple three-pin GPIO bootstrapping function (very similar to STM32 MCUs), but you can also blow some OTP fuses to lock in the boot modes and security features.
有一个简单的三针 GPIO 引导功能（与 STM32 微控制器非常相似），但您还可以烧录一些一次性可编程熔丝，以锁定引导模式和安全功能。🔒
Since there are only a few GPIO pins for boot mode selection, your options are a bit limited (for example, you can boot from an SD card attached to SDMMC1, but not SDMMC2), though if you program booting through OTP fuses, you have the full gamut of options.
由于用于引导模式选择的 GPIO 引脚数量有限，您的选择有些受到限制（例如，您可以从连接到 SDMMC1 的 SD 卡启动，但不能从 SDMMC2 启动），不过如果通过 OTP 熔丝编程引导，您将拥有所有选项。🔌

The first thing you’ll notice when fanning out this chip is that the STM32MP1 has a lot of power pins — 176 of them, mostly concentrated in a massive 12×11 grid in the center of the chip. This chip will chew threw almost 800 mA of current when running Dhrystone benchmarks across both cores at full speed — perhaps that explains the excessive number of power pins.
当你展开这块芯片时，你首先会注意到 STM32MP1 有很多电源引脚——总共有 176 个，主要集中在芯片中心的一个巨大的 12×11 的网格中。😲 这款芯片在两个核心全速运行 Dhrystone 基准测试时，电流消耗接近 800 毫安——也许这就解释了电源引脚数量的多。⚡️

This leaves a paltry 96 I/O pins available for your use — fewer than any other BGA-packaged processor reviewed here (again, this is available in a much-larger 448-pin package). Luckily, the pin multiplexing capabilities on this chip are pretty nuts.
这使得可用的 I/O 引脚仅剩下可怜的 96 个——比这里评测的任何其他 BGA 封装处理器都要少（再说一次，这在一个更大的 448 引脚封装中是可用的）。幸运的是，这款芯片的引脚复用能力非常强大。💡
I started adding peripherals to see what I could come up with, and I’d consider this the maxed-out configuration: Boot eMMC, External MicroSD card, SDIO-based WiFi, 16-bit parallel RGB LCD interface, RMII-based Ethernet, 8-bit camera interface, two USB ports, two I2C buses, SPI, plus a UART.
我开始添加外围设备，看看能搞出什么，我认为这是最大的配置：启动 eMMC、外部 MicroSD 卡、基于 SDIO 的 WiFi、16 位并行 RGB LCD 接口、基于 RMII 的以太网、8 位摄像头接口、两个 USB 端口、两个 I2C 总线、SPI，以及一个 UART。 🛠️
Not bad — plus if you can ditch Ethernet, you can switch to a full 24-bit-wide display.
不错——而且如果你能放弃以太网，你就可以切换到一个完整的 24 位显示器。✨

Software 软件 💻

These are new parts, so software is a bit of a mess. Officially, ST distributes a Yocto-based build system called OpenSTLinux (not to be confused with the older STLinux distribution for their old parts). They break it down into a Starter package (that contains binaries of everything), a Developer package (binary rootfs distribution + Linux / U-Boot source), and a Distribution package, that lets you build everything from source using custom Yocto layers.
这些是新部件，所以软件有点混乱。🛠️ 官方上，ST 发行了一个基于 Yocto 的构建系统，称为 OpenSTLinux（不要与他们旧部件的老 STLinux 发行版混淆）。📦 他们将其分为一个 Starter 包（包含所有内容的二进制文件）、一个 Developer 包（二进制根文件系统分发 + Linux / U-Boot 源代码）和一个 Distribution 包，允许你使用自定义的 Yocto 层从源代码构建一切。🔧

The somewhat perplexingly distribute a Linux kernel with a zillion patch files you have to apply on top of it, but I stumbled upon a kernel on their GitHub page that seems to have everything in one spot. I had issues getting this kernel to work, so until I figure that out, I’ve switched to a stock kernel, which has support for the earlier 650 MHz parts, but not the “v2” DTS rework that ST did when adding support for the newer 800 MHz parts.
有些令人困惑的是，他们提供了一个 Linux 内核，但需要在其上应用大量的补丁文件🔧。不过，我在他们的 GitHub 页面上发现了一个内核，似乎将所有内容都集中在一个地方🗂️。我在让这个内核工作时遇到了问题，因此在弄清楚之前，我转用了一个标准内核，这个内核支持早期的 650 MHz 部件，但不支持 ST 在增加对较新 800 MHz 部件的支持时所做的“v2”DTS 重构📉。
Luckily, it just took a single DTS edit to support the 800 MHz operating speed
幸运的是，只需进行一次 DTS 编辑就可以支持 800 MHz 的工作速度。🌟

ST provides the free STM32CubeIDE Eclipse-based development environment, which is mainly aimed at developing code for the Cortex-M4.
ST 提供免费的 STM32CubeIDE 基于 Eclipse 的开发环境，主要用于为 Cortex-M4 开发代码。💻
Sure, you can import your U-Boot ELF into the workspace to debug it while you’re doing board bring-up, but this is an entirely manual process (to the confusion and dismay of many users on the STM32 MPU forum).
当然，你可以将你的 U-Boot ELF 导入工作区，以便在进行板子引导时进行调试，但这是一个完全手动的过程（这让许多在 STM32 MPU 论坛上的用户感到困惑和失望）。😟

As usual, CubeIDE comes with CubeMX, which can generate init code for the Cortex-M4 core inside the processor — but you can also use this tool to generate DTS files for the Cortex-A7 / Linux side, too((No, ST does not have a bare-metal SDK for the Cortex-A7)).
像往常一样，CubeIDE 附带 CubeMX，这可以为处理器内部的 Cortex-M4 核心生成初始化代码——但您也可以使用这个工具为 Cortex-A7 / Linux 侧生成 DTS 文件（不，ST 没有针对 Cortex-A7 的裸机 SDK）。💻

If you come from the STM32 MCU world, Cube works basically the same when working on the integrated M4, with an added feature: you can define whether you want a peripheral controlled by the Cortex-A7 (potentially restricting its access to the secure area) or the Cortex-M4 core.
如果你来自 STM32 MCU 的世界，Cube 在集成的 M4 上工作基本相同，但增加了一项功能：你可以定义你想要由 Cortex-A7 控制外设（可能限制其对安全区域的访问）还是由 Cortex-M4 核心控制。🛠️
I spent less than an hour playing around with the Cortex-M4 stuff, and couldn’t actually get my J-Link to connect to that core — I’ll report back when I know more.
我花了不到一个小时玩弄 Cortex-M4 的东西，但实际上无法让我的 J-Link 连接到这个核心——等我了解更多信息后会再反馈。🕒

Other than the TI chip, this is the first processor I’ve played with that has a separate microcontroller core. I’m still not sold on this approach compared to just gluing a $1 MCU to y our board that talks SPI — especially given some less-than-steller benchmark results I’ve seen — but I need to spend more time with this before casting judgment.
除了 TI 芯片，这还是我玩过的第一款具有独立微控制器内核的处理器。🤔 我对此方法仍然持保留态度，特别是考虑到我看到的一些不太理想的基准结果，觉得直接将一个$1 的 MCU 通过 SPI 连接到你的电路板上更简单。💡 不过在作出判断之前，我需要更多时间来研究这一点。⏳

If you don’t want to mess around with any of this Cube / Eclipse stuff, don’t worry: you can still write up your device tree files the old-fashioned way, and honestly, ST’s syntax and organization is reasonably good — though not as good as the NXP, Allwinner, or Rockchip stuff.
如果你不想与这些 Cube / Eclipse 的东西搞在一起，不用担心：你仍然可以用传统的方式编写设备树文件，老实说，ST 的语法和组织还是相当不错的——尽管比不上 NXP、全志或瑞芯微的东西。🛠️

Rockchip RK3308 瑞芯微 RK3308 🌟

Anyone immersed in the enthusiast single-board computer craze has probably used a product based around a Rockchip processor. These are high-performance, modern 28nm heterogenous ARM processors designed for tablets, set-top boxes, and other consumer goods.
任何沉浸在单板计算机热潮中的爱好者可能都使用过基于 Rockchip 处理器的产品。⚙️ 这些是高性能的现代 28nm 异构 ARM 处理器，专为平板电脑、机顶盒和其他消费品设计。📱
Rockchip competes with — and dominates — Allwinner in this market. Their processors are usually 0.65mm-pitch or finer and require tons of power rails, but they have a few exceptions.
瑞芯微在这个市场上与全志竞争并占据主导地位。🔌 他们的处理器通常为 0.65mm 间距或更细，并且需要大量电源轨，但也有一些例外。⚡️
Older processors like the RK3188 or RK3368 come in 0.8mm-pitch BGAs, and the RK3126 even comes in a QFP package and can run from only 3 supplies.
较老的处理器，如 RK3188 或 RK3368，采用 0.8mm 引脚间距的 BGA 封装，而 RK3126 甚至采用 QFP 封装，并且仅需 3 个电源供电。💻

I somewhat haphazardly picked the RK3308 to look at.
我有些随意地选择了 RK3308 来研究。🔍
It’s a quad-core Cortex-A35 running at 1.3 GHz obviously designed for smart speaker applications: it forgoes the powerful camera ISP and video processing capabilities found in many Rockchip parts, but substitutes in a built-in audio codec with 8 differential microphone inputs — obviously designed for voice interaction.
这是一个运行在 1.3 GHz 的四核 Cortex-A35，显然是为智能音箱应用而设计的：它舍弃了许多 Rockchip 产品中强大的相机 ISP 和视频处理能力，但替代的是一个内置音频编码器，配备了 8 个差分麦克风输入 —— 显然是为了语音交互而设计的。🎤
In fact, it has a Voice Activity Detect peripheral dedicated just to this task.
实际上，它具有一个专门用于此任务的语音活动检测外设。🔊
Otherwise, it looks similar to other generalist parts reviewed: plenty of UART, SPI, and I2C peripherals, an LCD controller, Ethernet MAC, dual SDIO interfaces, 6-channel ADC, two six-channel timer modules, and four PWM outputs.
否则，它看起来与其他评论的通用部件相似：有大量的 UART、SPI 和 I2C 外设，一个 LCD 控制器，以太网 MAC，双 SDIO 接口，6 通道 ADC，两个六通道定时器模块，以及四个 PWM 输出。🔧

Hardware 硬件🔧

Unlike the larger-scale Rockchip parts, this part integrates a power-sequencing controller, simplifying the power supplies: in fact, the reference design doesn’t even call for a PMIC, opting instead for discrete 3.3-, 1.8-, 1.35- and 1.0-volt regulators.
与大规模的 Rockchip 部件不同，这个部件集成了一个电源顺序控制器，简化了电源供应：事实上，参考设计甚至不需要 PMIC，而是选择了离散的 3.3V、1.8V、1.35V 和 1.0V 稳压器。⚡
This adds substantial board space, but it’s plausible to use linear regulators for all of these supplies (except the 1.35V and 1.0V core domains).
这会增加相当多的电路板空间，但对于所有这些电源（除了 1.35V 和 1.0V 核心域）使用线性稳压器是可行的。📏
This part only has a 16-bit memory interface — this puts it into the same ballpark as the other parts reviewed here in terms of DDR routing complexity.
这一部分只有 16 位内存接口——在 DDR 布线复杂性方面，它与这里评审的其他部分处于相同的水平。🛠️

This is the only part I reviewed that was packaged in a 0.65mm-pitch BGA. Compared to the 0.8mm-pitch parts, this slowed me down a bit while I was hand-placing, but I haven’t run into any shorts or voids on the board.
这是我审核的唯一一个包装为 0.65mm 引脚间距 BGA 的部件。相比于 0.8mm 引脚间距的部件，这让我在手动放置时稍微慢了一点，但我并没有在板子上遇到任何短路或空洞。😊
There are a sufficient depopulation of balls under the chip to allow comfortable routing, though I had to drop my usual 4/4 rules down to JLC’s minimums to be able to squeeze everything through.
芯片下的球体数量足够稀疏，可以方便地进行布线，不过我不得不将我通常的 4/4 规则降低到 JLC 的最低标准，以便能够将所有内容挤过来。⚙️

Software 软件 🖥️

For a Chinese company, Rockchip has a surprisingly good open-source presence for their products — there are officially-supported repos on GitHub for Linux, U-Boot, and other projects, plus a Wiki with links to most of the relevant technical literature.
对于一家中国公司，瑞芯微的开源产品表现出乎意料的优秀——在 GitHub 上有官方支持的 Linux、U-Boot 及其他项目的仓库，还有一个维基，链接了大多数相关技术文献。📚

Once you dig in a bit, things get more complicated. Rockchip has recently removed their official Buildroot source tree (and many other repos) from GitHub, but it appears that one of the main developers at Rockchip is still actively maintaining one.
一旦深入研究，事情就变得更复杂了。😕 Rockchip 最近已从 GitHub 上移除了他们的官方 Buildroot 源树（以及许多其他仓库），但似乎 Rockchip 的一位主要开发者仍然在积极维护一个。🔧

While Radxa (Rock Pi) and Pine64 both make Rockchip-powered Single-Board Computers (SBCs) that compete with the Raspberry Pi, these companies focus on desktop Linux software and don’t maintain Yocto or Buildroot layers.
虽然 Radxa（Rock Pi）和 Pine64 都制造以 Rockchip 为动力的单板计算机（SBC），与树莓派竞争，但这些公司专注于桌面 Linux 软件，并不维护 Yocto 或 Buildroot 层。🐧

Firefly is probably the biggest maker of Rockchip SoMs and dev boards aimed at actual embedded systems development. Their SDKs look to lean heavily on Rockchip’s internally-created build system.
Firefly 可能是最大的 Rockchip SoM 和开发板制造商，专注于实际的嵌入式系统开发。🛠️ 他们的 SDK 看起来很依赖于 Rockchip 内部创建的构建系统。🔧
Remember that these products were originally designed to go into Android devices, so the ecosystem is set up for trusted platform bootloaders with OTA updates, user-specific partitions, and recovery boot modes — it’s quite complicated compared to other platforms, but I must admit that it’s amazing how much firmware update work is basically done for you if you use their products and SDKs.
请记住，这些产品最初是为 Android 设备设计的，因此生态系统为受信任的平台引导程序、OTA 更新、用户特定分区和恢复引导模式进行了设置——与其他平台相比，这复杂得多，但我必须承认，如果您使用他们的产品和 SDK，固件更新的工作基本上是为您完成的，这真是令人惊叹。🚀

Either way, the Firefly RK3308 SDK internally uses Buildroot to create the rootfs, but they use their internal scripts to cross-compile the kernel and U-Boot, and then use other tools to create the appropriate recovery / OTA update packages ((Buildroot’s genimage tool doesn’t support the GPT partition scheme that appears necessary for newer Rockchip parts to boot)).
无论哪种方式，Firefly RK3308 SDK 内部使用 Buildroot 创建根文件系统，但他们使用内部脚本交叉编译内核和 U-Boot，然后使用其他工具创建适当的恢复/OTA 更新包（（Buildroot 的 genimage 工具不支持新款 Rockchip 组件启动所需的 GPT 分区方案））。🚀
Their SDK for the RK3308 doesn’t appear to support creating images that can be written to MicroSD cards, unfortunately.
很遗憾，他们针对 RK3308 的 SDK 似乎不支持创建可以写入 MicroSD 卡的镜像。🛠️

There’s also a meta-rockchip Yocto layer available that doesn’t seem to have reliance on external build tools, but to get going a bit more quickly, I grabbed the Debian image that the Radxa threw together for the Rock Pi S folks threw together, tested it a bit, and then wiped out the rootfs and replaced it with a rootfs generated from Buildroot.
还有一个元 Rockchip Yocto 层可用，它似乎不依赖于外部构建工具，但为了更快开始，我抓取了 Radxa 为 Rock Pi S 用户准备的 Debian 映像，测试了一下，然后清除了 rootfs，并用 Buildroot 生成的 rootfs 替换了它。🛠️

Benchmarks 基准测试 📊

I didn’t do nearly as much benchmarking as I expected to do, mostly because as I got into this project, I realized these parts are so very different from each other, and would end up getting used for such different types of projects.
我进行的基准测试远没有我预期的多，主要是因为当我深入这个项目时，我意识到这些部件彼此之间差异如此之大，最终会被用于截然不同类型的项目。📊
However, I’ve got some basic performance and power measurements that should help you roughly compare these parts; if you have a specific CPU-bound workload running on one of these chips, and you want to quickly guess what it would look like on a different chip, this should help get you started.
然而，我有一些基本的性能和功耗测量，应该能帮助你大致比较这些元件；如果你在这些芯片之一上运行了特定的 CPU 密集型工作负载，并且你想快速猜测在另一种芯片上的表现，这应该能帮助你开始。💻

Dhrystone Benchmarks DHRYSTONE 基准测试 🖥️

Dhrystone is a small integer benchmark program that usually runs entirely in CPU cache; indeed, in my tests, changing SDRAM operating frequencies had no effect on the Dhrystone score.
Dhrystone 是一个小型整数基准程序，通常完全在 CPU 缓存中运行；实际上，在我的测试中，更改 SDRAM 工作频率对 Dhrystone 分数没有影响。🖥️
The Dhrystone benchmark reports its results in Dhrystones/sec, but we usually divide this number by 1757 (the number of Dhrystones per second obtained on a VAX 11 — a 1 MIPS machine) to compute the Dhrystone MIPS (DMIPS) score.
Dhrystone 基准测试以 Dhrystones/秒的形式报告其结果，但我们通常将这个数字除以 1757（在 VAX 11 上的每秒 Dhrystones 数量——一个 1 MIPS 的机器）来计算 Dhrystone MIPS（DMIPS）分数。📊

I ran this benchmark on all processors reviewed — most of which are single-core. On the dual-core STM32MP1 and quad-core A33 / RK3308, I ran multiple copies of the benchmark and added their scores. 
我在所有评测过的处理器上运行了这个基准测试——其中大多数是单核的。在双核的 STM32MP1 和四核的 A33 / RK3308 上，我运行了多个基准测试副本，并将它们的分数相加。📊

Since all of these processors have bog-standard off-the-shelf Arm core implementations, this benchmark is somewhat silly to do, as you should be able to simply compute the DMIPS score based on the core design and clock speed.
由于所有这些处理器都采用了标准的现成 Arm 核心实现，因此进行这个基准测试有些无聊，因为你应该能够根据核心设计和时钟速度简单地计算出 DMIPS 分数。📊
Yet, there are actually some variations in the data that come from different Linux versions  (why is the 900 MHz i.MX8ULL faster than the 1000 MHz AM335x and V3s?) and possibly some over-aggressive thermal throttling on the RK3308 (the single-core DMIPS score is much higher than everyone else’s — as you’d expect from a 1.3 GHz Cortex-A35 — yet the all-core speed is much less than 4x the single-core speed).((By the way, I’d love to have an operating systems/architecture guru explain to me in the comments why an 216 MHz STM32F746 advertises itself at 462 DMIPS —a score that the i.MX 6UL’s 528 MHz Cortex-A7 can just barely hit.
然而，不同 Linux 版本的数据实际上存在一些差异（为什么 900 MHz 的 i.MX8ULL 比 1000 MHz 的 AM335x 和 V3s 快？）以及 RK3308 可能存在一些过于激进的热限制（单核 DMIPS 得分远高于其他所有人——正如你从 1.3 GHz 的 Cortex-A35 所期待的——但所有核心的速度却远低于单核速度的 4 倍）。🤔（顺便说一下，我希望能有操作系统/架构专家在评论中向我解释一下，为什么一个 216 MHz 的 STM32F746 自我宣传为 462 DMIPS——这个得分是 i.MX 6UL 的 528 MHz Cortex-A7 刚好能达到的。）😲
I know that running a Linux kernel in the background introduces overhead, but why do the dual- and quad-core chips scale linearly?
我知道在后台运行 Linux 内核会引入额外开销，但为什么双核和四核芯片的扩展性是线性的呢？🤔
You’d think their single-core performance would be higher than the multi-core, since the kernel could essentially dedicate a second core to running the benchmark and keep everything else on the first core.))
你会认为它们的单核性能会高于多核，因为内核可以基本上将第二个核心专用于运行基准测试，而将其他所有任务保持在第一个核心上。💻

There’s obviously a huge performance disparity between a 300 MHz ARM9 and a quad-core 1.5 GHz Cortex-A53, but the bigger takeaway is that there are serious performance increases from simply migrating from ARM9 to Cortex-A5 to Cortex-A7 to Cortex-A35 (it’s not just marketing hype).
在 300 MHz 的 ARM9 和 1.5 GHz 的四核 Cortex-A53 之间显然存在巨大的性能差异，但更重要的是，从 ARM9 迁移到 Cortex-A5，再到 Cortex-A7，最后到 Cortex-A35，性能增长是非常显著的（这不仅仅是营销噱头）。💡
The SAMA5 scored 1.75 times the score that the SAM9X60 did, while only running at 83% the clock speed. Meanwhile, the 528 MHz Cortex-A7 inside the i.MX 6UL is clocked only 6% faster than the 500 MHz Cortex-A5-equipped SAMA5, yet was 43% faster.
SAMA5 的得分是 SAM9X60 的 1.75 倍，而其时钟速度仅为后者的 83%。⚙️与此同时，i.MX 6UL 内的 528 MHz Cortex-A7 的时钟速度仅比 500 MHz Cortex-A5 的 SAMA5 快 6%，但性能却快了 43%。🚀
And if you’ve got a floating-point workload, these differences would only magnify.
如果你有浮点工作负载，这些差异只会更加明显。💻

Power Consumption 功耗 ⚡️

To add a bit more context to the Dhrystone benchmark, I took some current measurements of each board under load. 
为了给 Dhrystone 基准测试增添一些背景信息，我对每块电路板在负载下进行了当前测量。⚡

My current consumption measurements are pretty haphazard; I was mostly just interested to see when LDOs were appropriate for core supplies.
我目前的功耗测量相当随意；我主要是想看看在什么时候线性稳压器（LDO）适合用于核心供电。🔍
For the boards with LDOs, I simply report the measured current flowing into the 5V rail (which goes through the regulators into the core, the memory, the IO, the flash storage device, and some quiescent current into the regulator itself).
对于带有 LDO 的电路板，我只是报告流入 5V 轨的测量电流（该电流经过稳压器进入核心、内存、IO、闪存设备，以及稳压器本身的一些静态电流）。🔌
The theory is that under a Dhrystone benchmark, the amount of current consumed by the core is going to overwhelm the others.
理论是，在 Dhrystone 基准测试下，核心消耗的电流将会超过其他核心。⚡

For the boards with buck converters on the core supplies, I’m even more devious: I measured the total 5V current, then divided by the conversion ratio and multiplied by 90% (the estimated efficiency of the converter).
对于那些核心供电上有降压转换器的电路板，我的方法更加巧妙：我测量了总的 5V 电流，然后除以转换比，再乘以 90%（转换器的估计效率）。🔧
You’d be surprised how close I get to datasheet numbers using this ridiculously-inaccurate approach. Basically, all of these numbers are going to be high — I’d bet if I were actually measure core supply rails, I’d see a 10-20 mA reduction across the board.
你会惊讶于我用这种荒谬不准确的方法与数据手册上的数字有多接近。📊 基本上，这些数字都会偏高——如果我真的测量核心供电轨，我敢打赌我会发现整体减少 10-20 毫安。⚡️

Looking at the data you’ll see a solid increase in power consumption as you increase clock speed and/or core count (obviously), but there are some more nuanced things going on:
查看数据时，您会发现随着时钟速度和/或核心数量的增加，功耗稳步上升（显而易见），但还有一些更微妙的情况发生：⚡️

• The F1C100s has strikingly good power figures — matching the 528-MHz Cortex-A7-endowed i.MX 6UL in terms of efficiency (though certainly not performance). Its 40 nm process appears to be a smaller technology node than what the NUC980, SAM9X60, and SAMA5D27 use.
  F1C100s 的功率数据非常出色 — 在效率上与配备 528MHz Cortex-A7 的 i.MX 6UL 相匹配（尽管性能上则不然）。它的 40 nm 工艺似乎比 NUC980、SAM9X60 和 SAMA5D27 使用的工艺节点要小。⚡️
• I wouldn’t trust these AM335x power figures — I was too lazy to hook up a separate VDD_CORE supply, so I’m slaving it off the 1.35V CDD_MPU / DDR rail. A sycophantic engineer using a TI-approved PMIC would likely see much better numbers.
  我不相信这些 AM335x 的功耗数据——我太懒了，没有连接一个单独的 VDD_CORE 电源，所以我只是把它从 1.35V 的 CDD_MPU / DDR 导线引过来。一个使用 TI 批准的 PMIC 的谄媚工程师可能会看到更好的数据。💡
• When you move up to the Cortex-A7 or Cortex-A35, you don’t necessarily get any more MHz/mA — instead, you get more DMIPS/MHz, so they consequently perform more DMIPS/mA, too.
  当你升级到 Cortex-A7 或 Cortex-A35 时，你并不一定会获得更多的 MHz/mA——相反，你会获得更多的 DMIPS/MHz，因此它们也会体现出更高的 DMIPS/mA。⚡
• Are LDOs reasonable choices to power any of these cores? Assuming 180 K/W thermal resistance of a SOT25 LDO and an allowable 125K delta, you want to stay under 700 mW of dissipation, maximum.
  使用 LDO 为这些核心供电是否合理？假设 SOT25 LDO 的热阻为 180 K/W，并且允许的温升为 125K，那么您希望功耗保持在 700 mW 以下，最大值。💡
  That’s about 180 mA maximum output current if regulating from 5V to 1.2V. The NUC980, SAM9X60 and SAMA5D27 are getting pretty close, though again, these estimates are high.
  这是在 5V 降至 1.2V 时的最大输出电流约为 180mA。NUC980、SAM9X60 和 SAMA5D27 的表现非常接近，不过这些估算仍然偏高。⚡

Node.js Express benchmark
Node.js Express 基准测试 🚀

Typically, these sorts of processors would end up in devices that make behind-the-scenes requests to cloud-based systems using lightweight protocols like MQTT— they would not be directly handling user requests.
通常，这类处理器会出现在使用轻量级协议如 MQTT 向云系统发起后台请求的设备中——它们不会直接处理用户请求。💻
But with growing interest in decentralizing smart devices, I wondered if the connected gadgets around our homes could self-host rich web applications that we could use to directly interact with them. I used the Polymer Project’s sample e-commerce PWA, called Shop, to test things out. This isn’t your typical WiFi router config page — rather, it’s a modern Node.js-based web application that weighs in at almost 600 MB once all the dependencies are installed((These aren’t all used at runtime.)).
随着对去中心化智能设备的兴趣日益增长，我在想我们家周围的连接设备是否可以自托管丰富的 веб 应用程序，以便我们能够直接与它们互动。💭 我使用了 Polymer 项目的示例电子商务 PWA，名为 Shop，来进行测试。🛍️ 这不是典型的 WiFi 路由器配置页面——相反，这是一款现代的基于 Node.js 的 веб 应用程序，安装所有依赖项后重量接近 600 MB （这些在运行时并不是全部使用）。💻

Using an aggressive test case like this helps to magnify differences between these platforms — in practice, you would likely build out a much slimmer application.
使用这样的激进测试案例有助于放大这些平台之间的差异——实际上，你可能会构建一个更简洁的应用程序。📊
I recorded the time it took to start up the app, along with the time it took to fully load the home page of the app in two cases: initial start (the first time the homepage is requested), and a warm reload (reloading the homepage after the server has already cached the data).
我记录了启动应用程序所需的时间，以及在两种情况下完全加载应用程序主页所需的时间：首次启动（第一次请求主页）和热重载（在服务器已经缓存数据后重新加载主页）。⏳
I cleared the browser cache to make sure the warm reload was actually hitting the server.
我清除了浏览器缓存，以确保温暖重载确实发送到了服务器。🌐

This benchmark was a bit clunky to perform accurately, and there’s really no reason to test a whole field of different Cortex-A7s, so I only picked a few processors from this round-up for the benchmark.
这个基准测试的实施有点笨拙，实际上没有必要测试一整批不同的 Cortex-A7，因此我只从这次汇总中挑选了几个处理器进行基准测试。💻
Node.js dropped support for ARM9 several years ago, so the Atmel SAMA5D27 was the lowest-end processor I could perform this benchmark on.
Node.js 几年前停止了对 ARM9 的支持，因此 Atmel SAMA5D27 是我能在上面进行此基准测试的最低端处理器。🖥️
I also selected the 900-MHz i.MX 6ULL, along with the Rockchip RK3308 and the Allwinner A33 — the latter was tested at both DDR3-800 and DDR3-1600 speeds.
我还选择了 900 MHz 的 i.MX 6ULL，以及 Rockchip RK3308 和 Allwinner A33——后者在 DDR3-800 和 DDR3-1600 速度下进行了测试。📡

On the quad-core A7 part running at DDR3-1600 memory (Allwinner A3), I noticed CPU usage maxed out at 38%, which indicates the workload is lightly threaded.
在运行 DDR3-1600 内存的四核 A7 部件（全志 A3）上，我注意到 CPU 使用率达到了 38%，这表明工作负载是轻线程的。🔍

Every part except the Atmel part had ample RAM (512-2048 MB), and the Atmel part had 128 MB with most if it free (there were no reserved memory segments in the kernel configuration).
除了 Atmel 部分之外，其他部分都有充足的 RAM（512-2048 MB），而 Atmel 部分有 128 MB，大部分是空闲的（内核配置中没有预留的内存段）。💾
The performance differences seem to reflect CPU and I/O bandwidth, not paging / caching issues from having limited RAM.
性能差异似乎反映了 CPU 和 I/O 带宽，而不是因有限的 RAM 导致的分页/缓存问题。💻

As you can see, the first load is where these processors struggle the most, sometimes taking more than three and a half minutes (!!!) to load the page.
正如您所见，第一个负载是这些处理器最有困难的地方，有时需要花费超过三分半钟（!!!）才能加载页面。⏳
The good news is that if you can periodically preload the page (with a cron job or something), warm reloads can get down to the sub-2-second range on nicer parts, even with a web application as large as this one.
好消息是，如果你能定期预加载页面（通过定时任务或其他方式），即使像这样的大型 Web 应用，暖启动的时间也能缩短到不到 2 秒的范围。⏰

I’m glad I threw in different memory speeds: you can clearly see that the faster RAM helps load pages more quickly, but the faster RK3308 (with slower DDR3-1066 memory), is still noticeably faster than the A33 running at DDR3-1600 when starting up (where the initial application is JIT compiled).
我很高兴我添加了不同的内存速度：你可以清楚地看到，更快的 RAM 帮助更快速地加载页面，但更快的 RK3308（搭载较慢的 DDR3-1066 内存）在启动时仍然明显比运行 DDR3-1600 的 A33 快（在此过程中，初始应用程序是即时编译的）。✨

Many of you are looking at the Ethernet PHY on the 1 GHz V3s and wondering about using it as a web server. Would it have similar performance to the i.MX 6? I restarted the i.MX 6 with mem=64M to simulate what it would be like to run this on something like a V3s and it….
许多人在关注 1 GHz V3s 上的以太网 PHY，并想知道是否可以将其用作 Web 服务器。它的性能会与 i.MX 6 相似吗？我重启了 i.MX 6，设置 mem=64M，以模拟在
well, wasn’t great. 嗯，感觉不太好。😕
I waited around for more than 20 minutes for the app to start-up before I gave up((This is obviously way more complicated than I’m letting on, since I realized the i.MX 6 defconfig for the kernel reserved 32M of memory for CMA and the kernel image itself was quite large.)). Bumping it up to 128MB helped a bit, but moving up to 256M seemed to enable me to duplicate the original results I got.
我等了超过 20 分钟才等到应用程序启动，最后放弃了😩（这显然比我展示的要复杂得多，因为我意识到 i.MX 6 的内核默认配置为 CMA 保留了 32M 的内存，而内核镜像本身相当大。）💻把内存提升到 128MB 有点帮助，但升级到 256M 似乎让我能够重复我之前获得的原始结果。📈

Discussion 讨论 🗣️

Nuvoton NUC980 新唐科技 NUC980💻

This SIP was easier to design hardware around than every other part reviewed here, requiring the fewest (and cheapest) external components and using an easy-to-pencil-solder 0.65mm-pitch 64-pin QFP package and SPI NOR flash chip.
这个 SIP 在硬件设计上比这里评审的其他每个部件都更简单，所需的外部组件最少（且成本最低），并采用了易于手工焊接的 0.65mm 间距的 64 引脚 QFP 封装和 SPI NOR 闪存芯片。🛠️
Without mainline Linux / Buildroot / U-Boot support, you’re left to follow Nuvoton’s carefully-written BSP manual and pull sources from their GitHub page.
没有主线 Linux / Buildroot / U-Boot 支持，你只能遵循 Nuvoton 精心编写的 BSP 手册，并从他们的 GitHub 页面获取源代码。📚
Because the out-of-the-box configuration targets an initrd rootfs, it’s a pain to use for development, so plan to spend some time switching things over to an actual persistent filesystem.
因为开箱即用的配置是针对 initrd 根文件系统的，使用起来开发上非常麻烦，所以请计划花一些时间将其切换到一个真正的持久文件系统。🛠️

Because of all this, I think this chip is great for embedded Linux firmware developers who might be less comfortable with hardware and want to get their hands dirty with some basic PCB design and prototyping.
因为这些原因，我认为这款芯片非常适合对硬件不太自信的嵌入式 Linux 固件开发者，他们想要在一些基础的 PCB 设计和原型制作中亲自动手。🛠️
I think the larger versions of the NUC980 are less interesting, and mostly overlap territory held by the SAM9X60, which is almost as easy to design hardware around, has similar pricing, and runs twice the speed while offering a more generalist peripheral set (like an LCD controller) as well as the secure boot capabilities most IoT product specifications call for these days.
我认为 NUC980 的大型版本不太有趣，主要与 SAM9X60 的领域重叠，而后者在硬件设计上几乎同样简单，价格相似，并且运行速度是其两倍，同时提供更通用的外设（如 LCD 控制器）以及如今大多数物联网产品规格所要求的安全启动能力。💻

There are definitely corner-cases for the NUC980, though: I hate ultra-fine 0.4mm-pitch QFPs, but many seem to prefer them over BGAs. The NUC also has tons of USB host ports, plus a better collection of communication peripherals than most other parts reviewed here.
NUC980 确实有一些特殊情况：我讨厌超细的 0.4mm 引脚 QFP，但很多人似乎更喜欢它们而不是 BGA。😅 NUC 还有许多 USB 主机端口，此外，它的通信外设总数比这里审查的其他大部分部件要好得多。📡
Just keep in mind that the NUC980’s slow ARM9 core is really designed for basic C/C++ IoT gateway-type projects, potentially with some industrial I/O and control-oriented tasks.
请记住，NUC980 的慢速 ARM9 核心实际上是为基本的 C/C++物联网网关类型项目设计的，可能还涉及一些工业输入/输出和控制导向的任务。🛠️

Allwinner F1C200s 全志 F1C200s 🖥️

This is a tiny, cheap SIP that’s easy to design hardware around, slightly harder to get booted, and definitely fun to play with. It’s far from a general-purpose do-anything part.
这是一个微型、廉价的 SIP，设计周边硬件很简单，启动稍微有些困难，但绝对很有趣。它远不是一个通用的多功能元件。🎉
With only one MMC port (that you’ll likely tie up with a WiFi module), it’s limited to SPI flash booting. It can’t decode video (yet), so using it for multimedia is out of the question.
只有一个 MMC 端口（你可能会用它连接 WiFi 模块），因此它只能通过 SPI 闪存引导。它目前无法解码视频，所以用于多媒体是不可能的。📉

While you might want to grab it for a basic HMI project, the sunxi-fel USB loader software can only access the first 16MB of your SPI flash, which limits the size of your rootfs — Qt development is essentially impossible, so you’ll need to use much tinier graphics libraries.
虽然你可能想要将其用于一个基本的 HMI 项目，但 sunxi-fel USB 加载程序软件只能访问你的 SPI 闪存的前 16MB，这限制了你的 rootfs 的大小——因此 Qt 开发实际上是不可能的，所以你需要使用更小的图形库。💻
Plus, the F1C200s lacks controls-oriented peripherals (no timers and just a single ADC input). All this, together, really limits the types of projects you can do with it.
此外，F1C200s 缺乏面向控制的外设（没有计时器，仅有一个 ADC 输入）。这些因素共同限制了您可以用它完成的项目类型。💡

Having said all that, if your application is light on peripherals and requirements, this low-cost part is worth considering — as long as you don’t mind ordering from Taobao and other Chinese vendors, as U.S.-based availability is completely nonexistent.
说了这些，如果你的应用对外设和要求没有太多需求，这款低成本的器件是值得考虑的——只要你不介意从淘宝和其他中国供应商下单，因为在美国根本没有现货。🛒

Microchip SAM9X60 微芯科技 SAM9X60 🖥️

With a normal DTS-based workflow, default SD-card booting, mainline Linux/U-Boot/Buildroot support in the works, good U.S. distributor availability, and an exceptionally easy package to design around, this SIP is the first part I’d feel comfortable recommending to a general audience of people new to embedded Linux firmware development but who also want easy-to-design hardware.
在正常的基于 DTS 的工作流程中，默认 SD 卡启动，目前正在支持主线 Linux/U-Boot/Buildroot，良好的美国分销商可用性，以及一个异常易于设计的封装，这款 SIP 是我会感到舒适推荐给那些新接触嵌入式 Linux 固件开发但也希望有易于设计硬件的一般受众的第一款产品。🛠️

More advanced users will want to plot out their system architecture first and make sure this is really the right chip for the job — popular runtimes like Node.js and .NET Core simply will not run on an ARM9 processor, and at $8, it’s roughly the same price as an i.MX 6ULL + DDR, which is 5 times faster than the SAM9X60.
更高级的用户会想首先绘制出他们的系统架构，并确保这个芯片确实适合这个工作——像 Node.js 和.NET Core 这样的流行运行时根本无法在 ARM9 处理器上运行，而价格为 8 美元，基本上和 i.MX 6ULL + DDR 相同，而后者的速度是 SAM9X60 的 5 倍。💻
This is also the lowest-end part I’d recommend doing modern GUI work in.
这是我推荐用于现代图形用户界面工作的最低端部件。🖥️

But for beginners, it’s reasonably good at running Python (and of course C/C++ code), there’s plenty of peripherals to dork around with, and the well-documented Secure Boot capabilities should help you get some practice with IoT security.
但对于初学者来说，它在运行 Python（当然还有 C/C++代码）方面表现相当不错，还有很多外设可以随意玩弄，完善的安全启动功能文档应该能帮助你在物联网安全方面获得一些实践经验。😊

Microchip SAMA5D27 微芯科技 SAMA5D27 🖥️

This is the highest-performing SIP available from U.S.-based vendors, so if you’re still nervous about taking the DDR plunge, this is about as good as it gets. It’s been around long enough to have good Linux support for all its peripherals and a decent ecosystem of documentation.
这是美国厂商提供的性能最强的 SIP，因此如果你还对 DDR 跃入感到不安，这就是最佳选择。它已经存在足够长的时间，支持所有外设的 Linux 驱动良好，且有相当不错的文档生态系统。🚀

Having said that, I found it clunkier to design around (and get booted) than the SAM9X60.
不过，我发现它在设计上（并且启动）比 SAM9X60 更笨重。🤖
While it’s faster than the 9X60, it’s not stunningly so, and the low-cost Cortex-A7s like the i.MX 6ULL are cheaper and much more performant, while only being marginally more difficult to design around.
虽然它比 9X60 快，但并没有特别惊人，并且像 i.MX 6ULL 这样的低成本 Cortex-A7 在价格上更便宜，性能也更强，设计起来只是稍微困难一些。📈

All told, the SAMA5D27 is sort of stuck in the middle of two different camps of processors — while offering middling performance and value.
总体来说，SAMA5D27 处于两种不同处理器阵营的中间，虽然提供了中等的性能和价值。🖥️
I still think it’s a reasonable entry into embedded Linux development, and one of the easiest-to-use parts I’d consider for an IoT-based application if I needed TrustZone / Secure Boot capability.
我仍然认为这是一种合理的嵌入式 Linux 开发入门，如果我需要 TrustZone / 安全启动功能， 这是我考虑用于基于物联网应用程序的最易于使用的组件之一。🔒

Allwinner V3s 全志 V3s 🖥️

The V3s is a specialty chip to pull out of your back pocket when the time arises. Hobbyists will find the LQFP package of the V3s a welcome sight, but I found the chip much more challenging to solder than the 0.8mm (or even 0.65mm) BGAs, so I can’t recommend it on those grounds.
V3s 是一款特殊的芯片，适合在需要的时候从口袋里拿出来。😊 爱好者们会发现 V3s 的 LQFP 封装十分让人愉悦，但我发现这个芯片的焊接难度比 0.8mm（甚至 0.65mm）BGA 要大得多，因此我不能在这一点上推荐它。😅

The 64MB on-chip SDRAM is spacious enough for uClibc-based systems running C/C++ programs and simple Python scripts, but the memory restrictions impose a low ceiling when compared to the other Cortex-A-series parts in this round-up that will limit your ability to run large JIT-compiled applications written in frameworks like .NET Core or Node.js. Though, in my testing, basic Qt 5 apps — even written in QML — performed without issues.
片上 64MB 的 SDRAM 对于运行基于 uClibc 系统的 C/C++程序和简单 Python 脚本来说空间足够大，但与本次总结中的其他 Cortex-A 系列产品相比，内存限制设定了一个较低的上限，这将限制您运行像.NET Core 或 Node.js 这样的框架编写的大型 JIT 编译应用程序的能力。尽管如此，在我的测试中，基本的 Qt 5 应用程序——即使是用 QML 编写的——也运行得毫无问题。✨

With a built-in audio codec and ethernet PHY, this would be a great processor for use in a basic Internet-connected audio system.
内置音频编码解码器和以太网 PHY，这将是用于基本互联网连接音频系统的理想处理器。🎵
Just keep in mind that, like all the Allwinner parts, availability in the U.S. is spotty, and the (community-written) Linux drivers tend to be a tad bit buggier than usual.
请记住，像所有 Allwinner 的组件一样， 在美国的供货情况不稳定，而且（社区编写的）Linux 驱动程序往往比平常稍微多一点 bug。🐞

NXP i.MX 6ULL NXP i.MX 6ULL🖥️

If you reject the premise of this blog post and instead want to commit to learning a single part family that you can reuse on a wide variety of projects, the i.MX 6ULL (and 6ULZ) should probably be at the top of your list. These generalist parts have a competent set of peripherals good for networked gadgets, industrial automation, and basic LCD interfacing, and also has secure-boot capabilities, plus support for TrustZone and OP-TEE.
如果你拒绝这篇博客文章的前提，而是想致力于学习一个可以在多种项目中重复使用的单一系列，那么 i.MX 6ULL（和 6ULZ）应该位于你列表的顶端。🌟 这些通用型部件配备了一套出色的外设，适合网络设备、工业自动化和基本的 LCD 接口，并且具备安全启动功能，还支持 TrustZone 和 OP-TEE。🔧

Needing only two supply voltages and few external components, the i.MX 6 was the easiest discrete-DRAM part to design around in the round-up. The 0.8mm-pitch BGA offers 106 I/O in a small-but-not-too-small package.
只需要两个供电电压和少量外部组件，i.MX 6 是本次评测中最容易设计的离散 DRAM 元件。⚡ 0.8mm 间距的 BGA 在小巧但又不算太小的封装中提供了 106 个 I/O 接口。📦

In terms of software, with a few minor U-Boot hacks, you can get going quickly and forgo fuse-blowing and GPIO boot pin selection. These parts have been around forever, so they have good mainline support in U-Boot, Linux, and Buildroot for all their peripherals.
在软件方面，只需进行一些小的 U-Boot 修改，就可以快速启动而无需烧熔保险丝和选择 GPIO 启动引脚。🔧 这些器件已经存在很久，因此在 U-Boot、Linux 和 Buildroot 中对它们的所有外设都有良好的主线支持。📦

Starting at $2.68 for the ULZ, they’re also the cheapest application processors you can buy outside of China.
ULZ 的起价为 2.68 美元，它们也是您在中国以外可以购买的最便宜的应用处理器。💰
Obtaining design help from NXP is relatively easy, and with wide availability from U.S., European, and Chinese vendors, managing production of an i.MX6-based design is trivial.
从 NXP 获得设计帮助相对容易，且美国、欧洲和中国的供应商广泛可用，管理基于 i.MX6 的设计生产非常简单。😊

Allwinner A33 全志 A33 🌟

The A33 is a powerhouse part fighting with the newer RK3308 for the top-dog spot in the benchmarks. It’s also relatively straightforward to get working.
A33 是一款强大的部件，与更新的 RK3308 在基准测试中争夺顶尖位置。💪 它的使用相对简单。🔧
There’s good mainline Linux support for most of the peripherals (but do your homework to verify they work properly), and U-Boot and Buildroot are both extremely easy to get going on this part.
大部分外设都有良好的主线 Linux 支持（但请提前做好功课以验证它们是否正常工作），而 U-Boot 和 Buildroot 在这方面都非常容易上手。 😊

But like the other two Allwinner chips reviewed, its peripheral set has huge gaps that reflect its pedigree as a tablet processor. It has a built-in audio codec, but no ADCs; RGB and MIPI DSI support, but no PWM outputs; three SDMMC ports, but no Ethernet MAC. You get the idea.
但与其他两款评测过的全志芯片一样，它的外设配置存在很大的缺陷，反映了它作为平板处理器的血统。它配备了内置音频编码器，但没有模拟到数字转换器（ADC）；支持 RGB 和 MIPI DSI，但没有 PWM 输出；有三个 SDMMC 端口，但没有以太网 MAC。你明白我的意思了。😊

Having said that, some of the peripherals it does have go almost unmatched, like that MIPI DSI interface. MIPI DSI-interfaced LCDs are the standard today — if you’re stuck with a parallel RGB interface, it’s getting tougher to find high-quality IPS LCDs and basically impossible to find OLEDs.
不过，它所具备的一些外设几乎无人能敌，比如那个 MIPI DSI 接口。今天，MIPI DSI 接口的液晶显示屏成为标准——如果你只能用并行 RGB 接口，现在找到高质量的 IPS 液晶显示屏越来越困难，寻找 OLED 几乎是不可能的。📱
This is making most of the parts in this review irrelevant for modern consumer electronics development, as buyers are looking for better and better image quality from all their devices.
这使得本次评测中的大部分内容对现代消费电子产品开发变得无关紧要，因为买家希望从他们的所有设备中获得越来越好的图像质量。📱

The usual supplier availability issues with Allwinner come into play; you’ll be buying samples off Taobao (or through horrendously-overpriced AliExpress / eBay listings).
常见的 Allwinner 供应商可用性问题出现了；你将不得不在淘宝上购买样品（或者通过价格极其高昂的 AliExpress / eBay 列表）。🛒
Chinese CMs shouldn’t have any issue obtaining parts once you go into production, though, and while these are older designs, Allwinner shows no signs of discontinuing them soon.
一旦进入生产阶段，中国的 CM 应该不会遇到获取零部件的问题，虽然这些设计较旧，但全志似乎没有很快停产的迹象。🔧

Texas Instruments AM335x 德州仪器 AM335x 📦

I was excited to try this part, since I see it in lots of gadgets. It has good U.S. availability, carries a reasonable price tag, and has similar features as other Cortex-A7 parts reviewed.
我很兴奋能尝试这个部件，因为我在很多小工具中都看到过它。😊它在美国的可用性很好，价格合理，且具有与其他评测过的 Cortex-A7 部件相似的功能。🔧

Unfortunately, at no point did I enjoy using this part.
不幸的是，我在使用这个部件的过程中没有感到任何乐趣。😔
I ran into roadblock after roadblock, and most of them would have been completely eliminated if TI would have simplified their U-Boot codebase, enabled obvious defaults (like earlyprintk and printf support), and reworked the chip to simplify board design and reduce the fragility of the platform.
我遇到了一个又一个的障碍，如果德州仪器能够简化他们的 U-Boot 代码库，启用明显的默认设置（例如早期打印和 printf 支持），并重新设计芯片以简化电路板设计、降低平台的脆弱性，绝大部分障碍就可以完全消除。🚧

Once I finally did get everything working, it felt like a Pyrrhic victory: I had invested a ton of time and effort, all for a single-core Cortex-A7 that has some gaping holes in its feature set: no secure boot, no TrustZone, and not even a simple parallel camera interface.
一旦我终于让一切运作起来，这感觉像是一场得不偿失的胜利：我投入了大量的时间和精力，只是为了一个有许多功能缺失的单核 Cortex-A7：没有安全启动，没 TrustZone，甚至连一个简单的并行摄像头接口都没有。😞
This part has its place in niche applications: if I were building out an industrial robot with EtherCAT support, this would be at the top of my list.
这一部分在特定应用中占有一席之地：如果我在构建一个支持 EtherCAT 的工业机器人，这将是我首选的内容。🤖

If you’re an obedient, studious engineer that will carefully follow datasheet guidelines and copy reference designs precisely, you will have no problem getting an AM335x-based design going.
如果你是一位遵守规则、勤奋好学的工程师，认真遵循数据手册的指导，并精确复制参考设计，那么你在进行基于 AM335x 的设计时将毫无问题。📘
And since these parts are made by Texas Instruments, there’s always good technical support available via their E2E Forums and direct support connections while you’re working through design issues.
这些部件是由德州仪器制造的，因此在您解决设计问题时，总能通过他们的 E2E 论坛和直接支持连接获得良好的技术支持。🔧

STMicroelectronics STM32MP157D
STMicroelectronics STM32MP157D 🎉

Introduced in 2019, the STM32MP1 is one of the newest parts in this review.
2019 年推出的 STM32MP1 是本次评估中最新的组件之一。🎉
With prices ranging from $8 to $17, these parts are quite a bit more expensive than some of the other parts I looked at, but they have some killer features that are hard to find anywhere else: an integrated Cortex-M4 microcontroller, a full set of microcontroller peripherals that looks to be ripped straight off an STM32H7-series processor, good interfacing options, and a dual-core 800 MHz architecture that makes it the third-fastest part in the round-up.
这些零件的价格在 8 到 17 美元之间，确实比我查看的其他一些零件贵了不少，但它们具备一些很难在其他地方找到的强大特点：集成的 Cortex-M4 微控制器，整套看起来直接来自 STM32H7 系列处理器的微控制器外设，良好的接口选项，以及双核 800 MHz 架构，使其成为此次评测中第三快的零件。💰

With all these features, this would be an excellent controls-oriented processor to look at if you have some prior embedded Linux experience and don’t mind working through some BSP kinks.
考虑到这些特性，如果您有一些嵌入式 Linux 的经验，并且不介意解决一些 BSP 的问题，那么这将是一个出色的控制导向处理器。💻
They’re extremely easy to design hardware around and widely available; in time, these parts could become the Swiss Army Knife of embedded Linux development.
它们非常容易用于硬件设计，并且广泛可用；随着时间的推移，这些组件可能会成为嵌入式 Linux 开发的瑞士军刀。🛠️

But until the software and documentation become a bit more stable, I think newbies should look elsewhere for their first embedded Linux project.
但在软件和文档变得更加稳定之前，我认为新手应该在其他地方寻找他们的第一个嵌入式 Linux 项目。💻

Rockchip RK3308 瑞芯微 RK3308 🎉

This part’s Cortex-A35 design puts it well above the rest of the field in terms of raw computing capability and overall efficiency.
这一部分的 Cortex-A35 设计使其在原始计算能力和整体效率方面远超其他产品。💻
It may seem unfair to compare a part that came out in 2018 with parts that trace back to 2012 or 2013, but that’s the fault of these other vendors, who have largely focused their recent efforts on higher-end processors.
将 2018 年发布的部件与 2012 年或 2013 年发布的部件进行比较可能看起来不公平，但这主要是这些其他供应商的错，他们最近的努力大多集中在高端处理器上。 🛠️
NXP and Texas Instruments both make modern processors: the i.MX 8 and AM6x, but both are seriously expensive parts that you’re not going to find in entry-level gadgets.
NXP 和德州仪器都生产现代处理器：i.MX 8 和 AM6x，但这两款都是非常昂贵的部件，您不会在入门级设备中找到它们。💻

The RK3308 is a good entry into their ecosystem. There’s no PMIC required (even their reference designs don’t use one), and the control signals are straightforward.
RK3308 是他们生态系统的一个不错的入门选择。😊 没有 PMIC 的要求（甚至他们的参考设计也不使用 PMIC），控制信号也很简单。📡
It’s a 0.65mm-pitch part — a step below the 0.8mm-pitch BGAs everyone else in this round-up used — but I didn’t run into any problems during hand-placing.
它是一个 0.65 毫米间距的元件——比这一轮评测中其他人使用的 0.8 毫米间距 BGA 低一个级别——但我在手工放置时没有遇到任何问题。🛠️

But this is still not a part for the faint of heart: you’ll need 4 or 5 voltage supplies, fanning out the BGA is tedious, and you’ll be pushing your board house’s specs — they need to be able to hit 0.09mm trace/space and 0.2mm drill sizes.
但这仍然不是胆小者的选择：你需要 4 或 5 个电压源，展开 BGA 是非常繁琐的，而且你将挑战你的电路板厂的规格——他们需要能够达到 0.09mm 的走线/间距和 0.2mm 的钻孔尺寸。🔧

On the software side, there’s no mainline Buildroot support for it (only Yocto support), and you’re not going to find a lot of English-language resources online in tutorial format (though the datasheet, TRM and example schematics are readily available).
在软件方面，它没有主流的 Buildroot 支持（只有 Yocto 支持），而且你在网上很难找到大量的英文教程资源（尽管数据表、TRM 和示例原理图都很容易获得）。📘
You’ll want to have some prior experience so you can read between the lines when necessary.
你会希望有一些之前的经验，这样在必要时就能窥探到字里行间的意思。🔍

Honorable Mentions 荣誉提名 🌟

While working on this, I looked at (and even played around with) some other parts that should be on your radar.
在这个过程中，我查看了（甚至玩了一些）其他一些应该引起你注意的部分。🔍

Azure Sphere MediaTek MT3620
Azure Sphere 媒体 Tek MT3620 🌐

The AI-Link WF-M620-RSC1 module from Seeed Studio uses the MediaTek MT3620
来自 Seeed Studio 的 AI-Link WF-M620-RSC1 模块使用了 MediaTek MT3620。📡

This is a highly-secure, preconfigured embedded Linux SOM (System On Module) that is designed for IoT applications.
这是一款高度安全、预配置的嵌入式 Linux 系统模块（SOM），旨在用于物联网应用。🔒
While other platforms support TrustZone and security measures to protect against reverse engineering, cloning, and firmware alterations, this is the only platform I’ve seen that ships with all these security features activated and preconfigured, and doesn’t allow them to be disabled.
虽然其他平台支持 TrustZone 和安全措施以防止逆向工程、克隆和固件修改，但这是我见过的唯一一个默认启用并预配置所有这些安全功能的平台，且不允许禁用它们。🔒
Before being able to deploy firmware, new devices must be provisioned — linked permanently to an Active Directory identity — which is stored in one-time-programmable memory. If you lose access to that AD identity, all your devices turn into paperweights. This is serious stuff.
在能够部署固件之前，新设备必须进行配置——永久链接到一个存储在一次性可编程内存中的活动目录身份。如果您失去对该活动目录身份的访问，所有设备将变成摆件。这是非常严重的事情。📜

Under the hood, this device is running Linux, but your application runs in a sandbox with custom secure APIs to the underlying hardware.
在底层，这个设备运行着 Linux，但你的应用程序在一个沙箱中运行，并通过定制的安全 API 访问底层硬件。🐧
From what I can tell, there’s no mechanism for writing kernel modules, so all device drivers execute within the context of your userspace application.
根据我所了解，没有编写内核模块的机制，因此所有设备驱动程序都在用户空间应用程序的上下文中执行。🖥️
Azure automatically delivers updates to the underlying Linux system, and you can push updates to your application to end devices through Azure as well.
Azure 自动将更新推送到基础的 Linux 系统，同时您也可以通过 Azure 将更新推送到终端设备上的应用程序。🌐

I’ve played with this platform a bit and I’m perplexed I haven’t seen more buzz about it. Developing on it is dead-simple: after a few clicks, you’re connected to your WiFi network. A few more clicks, and you’re remotely debugging your code over WiFi.
我稍微玩过这个平台，感到困惑的是我没有看到更多关于它的讨论。😕 在上面开发非常简单：只需几次点击，您就可以连接到您的 WiFi 网络。💻 再点击几下，您就可以通过 WiFi 远程调试代码了。🌐
I found the custom userspace APIs for GPIO and communications interfaces are much less clunky to use than the standard Linux APIs.
我发现自定义用户空间的 GPIO 和通信接口 API 使用起来比标准 Linux API 顺畅得多。😊

Still, the biggest feature is that you get to write embedded Linux apps — with threads and memory management and all the good stuff — without having to screw around with setting up an embedded Linux system.
尽管如此，最大的特点是你可以编写嵌入式 Linux 应用程序——包含线程、内存管理以及所有这些优秀的功能——而无需麻烦地设置嵌入式 Linux 系统。🖥️
It’s like getting your dessert without being forced to eat your peas and carrots first.
就像在没有强迫你先吃豌豆和胡萝卜的情况下就得到了甜点一样。🍰

Oh, the hardware: it’s a 500 MHz Cortex-A7 with two 200-MHz Cortex-M4 real-time processors, built-in WiFi, and 5 MB of built-in SRAM (so it should actually have quite good sleep-mode power consumption compared to DRAM-based designs).
哦，硬件：它是一款 500 MHz 的 Cortex-A7，配备两个 200 MHz 的 Cortex-M4 实时处理器，内置 WiFi，以及 5 MB 的内置 SRAM（因此与基于 DRAM 的设计相比，它在睡眠模式下的功耗应该相当不错）。💻
It comes in a 12x12mm 164-pin dual-row QFN — likely only available in relatively high volumes directly from MediaTek. For low-volume work, Seeed Studio and Avnet make FCC-certified SOMs that are surprisingly inexpensive.
它采用 12x12mm 的 164 引脚双排 QFN 封装——很可能仅在相对大批量时可以直接从联发科技获取。对于小批量工作，Seeed Studio 和 Avnet 提供 FCC 认证的系统模块，价格出奇的便宜。💼

Renesas RZ/A 瑞萨 RZ/A 🌟

Renesas makes the RZ/A line of 400 MHz Cortex-A9 application processors that have on-chip integrated SRAM (yes, SRAM) of up to 10 MB with a 128-bit-wide interface. They have a special XIP (execute-in-place) Linux kernel that allows these parts to start up quickly. I imagine they would have excellent suspend-to-RAM current consumption, too. These come in monster 28x28mm QFP and more-reasonable BGA packages.
瑞萨电子推出了 RZ/A 系列的 400 MHz Cortex-A9 应用处理器，具有高达 10 MB 的片上集成 SRAM（是的，SRAM）和 128 位宽接口。💻它们配备了特殊的 XIP（就地执行）Linux 内核，使这些部件可以快速启动。⚡我想它们在待机到 RAM 时的电流消耗也会非常出色。🔋这些处理器提供了巨大的 28x28mm QFP 封装和更为合理的 BGA 封装。📦

MediaTek MT7688AN (et al.)
联发科技 MT7688AN (等) 📱

MediaTek and Atheros make a ton of low-cost app processors that are designed for network appliances (typically routers). These are generally available in QFN, QFP, or coarse-pitch BGA packages targetting low-cost 4-layer PCB technology.
联发科技和 Atheros 制造了大量低成本的应用处理器，专为网络设备（通常是路由器）设计。🛠️ 这些处理器一般采用 QFN、QFP 或粗间距 BGA 封装，针对低成本的 4 层 PCB 技术。📡

Because these processors integrate WiFi into them, you’ll see them used for IoT gadgets from companies like Belkin and TP-Link.
因为这些处理器将 WiFi 集成在内，所以你会看到它们被用于来自 Belkin 和 TP-Link 等公司的物联网设备。📡

I actually bought some MediaTek MT7688AN chips, designed up a board, and built it up — intending to review the part for this review — but really struggled to get the hardware soldered up.
我实际上购买了一些 MediaTek MT7688AN 芯片，设计了一块板子并搭建起来——打算为这篇评测评审这个部分——但在焊接硬件时真的很挣扎。🔧
The 0.5mm-pitch dual-row QFN was awful to work with, and after spending an entire afternoon hot-airing, removing, replacing, nudging, and resoldering, I gave up.
这个 0.5mm 间距的双排 QFN 非常难以处理，经过一个下午的热风焊接、拆卸、替换、微调和重新焊接后，我终于放弃了。😩
The firmware situation is also a bit weird — I couldn’t find a Buildroot environment for this part, since these are usually developed in DD-WRT/OpenWRT, and it looked like the binaries these produced didn’t include a boot sector.
固件情况也有点奇怪——我找不到这个部分的 Buildroot 环境，因为这些通常是在 DD-WRT/OpenWRT 中开发的，而看起来这些生成的二进制文件并不包括引导扇区。🔧
I know that many of these devices have a “factory” area that stores calibration parameters, but I couldn’t figure out if this was one of those parts. I downloaded a pre-built OpenWRT build for the MT7688AN, which is the .bin file I used.
我知道这些设备中有很多都有一个“工厂”区域来存储校准参数，但我无法确定这是否是其中的一部分。🔍 我下载了适用于 MT7688AN 的预构建 OpenWRT 版本，这就是我使用的.bin 文件。💾
These parts don’t appear to have a USB bootloader or any mechanism like that, so I had to manually attack to the SPI flash chip with my J-Link to program it. It wasn’t fun.
这些零件似乎没有 USB 引导程序或类似的机制，因此我不得不手动连接到 SPI 闪存芯片，并使用 J-Link 进行编程。这并不好玩。💻

Anyway, I don’t think most people design PCBs around these raw parts anyway — the off-the-shelf SOMs are so ridiculously cheap (even ones that plausibly are FCC certified) that even relatively high-volume products I’ve seen in the wild use the solder-down modules (unless they’re space-constrained like the smart plugs mentioned above).
不过，我认为大多数人在设计 PCB 时并不会围绕这些原材料进行设计——现成的系统模块价格非常便宜（即使是那些看起来有 FCC 认证的模块），以至于我在实际中见过的相对高产量产品都使用了焊接模块（除非它们像上面提到的智能插头那样受限于空间）。💰
These SOMs come with a factory image already burned into the chip, and once you boot it up, you can easily load different images.
这些 SOM 已经在芯片中烧录了工厂镜像，一旦启动，您可以轻松加载不同的镜像。🔧

Conclusions 结论 🌟

This post was a lot of fun to put together. I went into this project with some previous experience with a couple of these processors — a bit over-confident with what I thought I knew — and ended up learning a ton.
这篇帖子制作起来非常有趣。😊 我在这个项目中带着一些之前与这些处理器的经验进入 —— 对我认为我所知道的有点过于自信 —— 最后学到了很多。📚

I’ve blabbered on enough about Linux and these chips, so I wanted to leave you with a different thought entirely: This project re-affirmed the importance of practicing engineering (versus doing engineering). When you force yourself to get away from interesting domain-specific problem-solving and focus on the low-level mechanics of design work, in a repeated fashion, you end up building up muscle memory for things you thought you’d always have to think about.
我已经关于 Linux 和这些芯片喋喋不休了，所以我想给你留下一种完全不同的想法：这个项目重申了工程实践的重要性（与做工程相对）。💡 当你强迫自己离开有趣的领域特定问题解决，专注于设计工作的低级机制，反复进行时，你最终会建立起对那些你认为自己永远需要思考的事情的肌肉记忆。🔧

By the time I got to the end of this project, working on the Rockchip RK3308, I was flying through things.
当我完成这个项目时，关于 Rockchip RK3308 的工作让我如鱼得水。✈️
I spent two hours researching, 20 minutes drawing the 355-pin schematic symbol, an hour routing the DDR3 bus, three hours fanning out the rest of the signals and routing power, and 30 minutes cleaning everything up.
我花了两个小时进行研究，🕒 花了 20 分钟绘制 355 脚的原理图符号，✏️ 花了一个小时布线 DDR3 总线，⏳ 花了三个小时扩展其余信号并布置电源，🔌 最后花了 30 分钟整理一切。🧹

When the boards came back, I put on some music, pasted them up, hand-placed everything, threw it on a hot plate, flipped it over to do the back side, and less than an hour later, I was booted up on a command prompt, sitting in front of a quad-core 1.3 GHz computer I made from $10 worth of parts, mounted on a $20 PCB.
当电路板回来时，我放上音乐，粘贴它们，手动放置每个组件，把它放在热板上，翻转过来处理背面，不到一个小时后，我在命令提示符下启动，坐在我用 10 美元的零件和 20 美元的 PCB 制作的四核 1.3 GHz 电脑前。🎶

That’s a far cry from where I was when I started doing this stuff years ago — cowering over my DDR layouts for days on end, wrapping my head around power plane designs, and constantly re-reading the datasheets, unsure of whether I had connected control lines properly.
这与我开始做这些事情时的状态大相径庭——我连续几天蜷缩在 DDR 布局旁，努力理解电源平面设计，并不断重读数据表，不确定自己是否正确连接了控制线。😅

I think everyone in this community — professional or hobbyist — tends to focus way too much on project outcomes.
我认为这个社区中的每个人——无论是专业人士还是爱好者——都过于关注项目的结果。🔍
I hope that after reading this, you’re going to be tempted to drop one of these parts into your latest project, tossing in a bunch of other circuitry and plotting out tons of software work ahead.
我希望在阅读完这些内容后，你会想要把其中一个部件放入你最新的项目中，添加许多其他电路，并规划出大量的软件工作。🔧

But I also hope you consider practicing a bit first: design a little break-out for your processor, solder it up, and try it out. If you’re running into problems getting things working, consider doing the thing you’re never supposed to do: giving up and trying a different part.
但我也希望你先考虑练习一下：为你的处理器设计一个小的断路器，把它焊接好，然后试试看。如果在让事情正常运作时遇到问题，可以考虑做你从未想过的事：放弃并尝试不同的元件。💻
Compare and contrast. You’ll see patterns emerge as you get more familiar with how this stuff is done.
比较和对比。当你对这些内容的操作变得更加熟悉时，你会看到一些模式浮现出来。🔍

Continue working on your projects, but never be afraid to roll up your sleeves and commit to some quality practice time!
继续致力于你的项目，但永远不要害怕卷起袖子，投入一些高质量的练习时间！💪