While there is going to be a big ramp in CoWoS capacity, what does help a little is there is slack in Wafer Level Fan-Out packaging capacity (primarily used for smartphone SoCs), and some of these tools can be repurposed some CoWoS process steps. In particular, there are some overlapping processes such as: deposition, plating, back grinding, molding, placement, and RDL formation.

It’s also noteworthy that CoWoS wafer production is quite low, even with it more than doubling to beyond 20k wafers per month (WPM), many steps that are shared in front-end or back-end have very little torque compared to the 100k+ WPM that logic and DRAM processes achieve

Process Control, The Biggest Winner

We believe that of all the toolmakers that are involved here, it is the process control players that are the most torqued to this trend. Onto and Camtek are the leaders in inspection and metrology for advanced packaging and both are seeing business picking up. KLA does not have much share here.

Inspection is especially important in the CoWoS flow as yield loss is very expensive. A GPU package has multiple, very expensive known good die (KGD). The H100 has the GPU logic die and 5 stacks of HBM. The cost of the HBM is actually more than that of the 5nm logic die. This makes for a very expensive package. Having a critical defect during the packaging flow will make all these known good die worthless. Therefore it makes sense to have more thorough process control to prevent these expensive yield losses.

In addition, process control tools are more unique and tailored to each individual package technology so there is less ability to use slack capacity from elsewhere. What is also attractive about inspection and metrology companies in general is that each player general owns the specific niches tools are inserted in which means lower competition. This is in contrast to flip chip bonders (we will discuss this later) where there are multiple competitors inserted into the process due to lack of differentiation and technical complexity.

Israel-based Camtek had ~60% revenue exposure to advanced packaging in 2022 and is now seeing strong orders for packaging. Recently they announced they had received new orders of 42 systems from Tier 1 customers related to HBM and advanced packaging. We believe Samsung and SK Hynix are the big drivers here with both spending aggressively to be the leader.

Strong demand for HBM is why Camtek believes its whole DRAM business to grow because of this, even with DRAM WFE down significantly for the market as whole.

Regarding the DRAM field, customers in the HBM segment account for over 10% of our revenue. If our revenue in Q1, which represents a significant increase over Q1 last year. We see expansion of our DRAM business in spite of the decline in the memory market.

Rafi Amit, Camtek CEO

This is in addition to their May announcement of a 9 system order from a Tier 1 customer for advanced packaging which appears to be logic related. We believe this is CoWoS-related demand for TSMC.

We continue to see solid business, particularly in our main segment, Advanced Packaging, which accounted for 60% of our revenues. In the first quarter, we shipped multiple systems to six tier-1 customers in the Advanced Packaging and Heterogeneous Integration space, contributing more than 40% of quarterly revenues. Among others, we received a strategically important order for nine machines from a tier-1 customer for Advanced Packaging applications, to be delivered in the second and third quarters of this year.

Rafi Amit, Camtek CEO

We believe TSMC will need another ~25 incremental tool orders to satisfy their newest CoWoS expansion plans. With the ASP around $1.5M for this tool, Samsung + TSMC orders should drive Camtek revenue very high. As SK Hynix and Samsung increase HBM, there is much more torque there, which will be more important for Camtek than the logic and packaging side of the equation. The intensity increases with 12 and 16-layer HBM are massive. It also significantly reduces their China exposure which was quite high, meaning there is a rerating that should occur here.

Onto is the other main player in advanced packaging inspection with 44% of revenue dedicated to advanced packaging and specialty devices (LED, MEMS, CIS) and this segment is starting to see activity pickup. In fact they are larger than Camtek for advanced packaging generally.

[W]e do see at least our specialty and advanced packaging markets growing fairly nicely in the second quarter and maintaining that rate of growth or at least a strong growth right through the second half. So that’s really going to carry the strength of the growth we see in the second half.”

Michael Plisinski, Onto CEO

Onto’s other main segment is for Advanced Nodes and that has seen a steep reduction in sales especially driven by memory (NAND and DRAM) weakness in the front end. However, as we’ve written about before, Onto has had wins in the big 3 leading edge logic players nanosheet fabrication inspection which will represent a sizable revenue opportunity ($400mn in 2025) in advanced logic alone. This is new spend for new process technologies and represents share gains from KLA.

With its business exposed to these 2 secular themes of advanced packaging and GAA logic, Onto should comfortably grow above industry WFE growth. Furthermore, they have a huge opportunity with their JetStep litho tool for large format panel-based packaging technologies which will gain significant traction over the next few years as packages grow beyond 100mm x 100mm.

The Misguided – Test

While not strictly for CoWoS, test is another constrained part of the industry. All chips and packages go through testing, but large advanced datacenter products with CoWoS have a much higher testing intensity.

After the chip wafer is fabricated, the wafer is tested during the wafer sort process to identify Known Good Die (KGD). Identifying KGD is even more important for advanced packaging as the package is more valuable. Having faulty die in a package will effectively waste the other good die in that package, so the cost of failing to identify KGD is much higher. Therefore, wafer sorting becomes more thorough for chips that are to be heterogeneously integrated.

A wafer prober and prober solution will send electrical tests to the wafer via a probe card. Probe cards have probe needles that interface with the wafer. The needles will be aligned with the contact pads on the wafer and each probe card is unique to each individual chip design. Probe cards are considered consumables each new chip design will require a new probe card.

Tokyo Electron is the market share leader in wafer probing machines. This does not have much torque at all to the advanced packaging theme.

FormFactor and Technoprobe are the 2 largest suppliers of probe cards but there are smaller suppliers such as: Micronics Japan, Japan Electric Materials, MPI Corporation.

Advanced packaging processes like Foveros and 3D Fabric are increasingly being adopted on these leading-edge Foundry and Logic chips providing an exciting opportunity for FormFactor.

As we’ve noted in the past, these integration schemes drive both higher test intensity, which expands the number of probe cards required per good die out and higher test complexity, which raises the performance requirements for each probe card.

… [The] growth of HBM is an exciting opportunity in the DRAM market as well, as the die stacking advanced packaging process increases both test intensity and test complexity of HBM products compared to standard single-die DRAM architectures. This in turn increases both the number and complexity of probe cards required for good die out.

FormFactor CEO Mike Slessor

However, unfortunately, FormFactor has a higher mix towards memory which we are not as positive on. Furthermore, they seem to dilute a lot despite strong earnings growth. Technoprobe is the primary winner in probe cards for logic, especially at the high-end with firms like AMD and Nvidia. There isn’t much torque here either, despite relatively high ASPs for fine-pitch advanced packaged products.

After the chip is fully packaged, there will be a final test stage usually performed at OSAT houses, and testing is one of the main bottlenecks at the OSATs. Testing is performed by Automatic Test Equipment (‘ATE’).

ATE mostly involves burn-in testing, functional testing, and system-level test (SLT). Burn-in testing subjects the packages to extreme conditions (a combination of both high temperatures and while applying high voltage) for a prolonged period to identify faulty chips that cannot withstand stress and are, therefore more likely to fail early.

Functional testing is where the chip is tested to see if it performs operations as intended. The ATE will perform a collection of tests on the chip by sending signals to the chip and will check if the chip returns the correct output signal to check for circuit errors. ATE machines have several test scripts designed to suit each chip design.

System-level testing (SLT) is where the ATE will boot up and test the chip in an end-use environment. SLT is the most time-intensive of each. One SLT can take as much as 10 minutes per unit as the system needs to boot up which adds to the time required. They can be as low as a couple minutes though.

ATE is effectively a duopoly between Advantest and Teradyne. There are smaller suppliers, too like Chroma ATE that does SLT, which does have some potential torque given SLT test times. However, Advantest has the most AI exposure by dollars. Advantest is the sole source ATE supplier for Nvidia outside of SLT. Teradyne has high smartphone exposure (Apple is their largest customer) and lower AI exposure.

[R]egarding ChatGPT, there are hot discussions in the market. And certainly, on a customer basis, there are — we are capturing almost all of the major players, but direct impact on our revenue would be in the second half of this year or maybe in fiscal year 2024.” 

Yoshiaki Yoshida, President and Group CEO of Advantest

There is a compelling short thesis around Advantest that while it has Nvidia exposure, the impact on Advantest’s orders will not be as significant as the YTD share price run-up implies. The average testing intensity being 2% of chip COGS is cited. But, we want to point out that while test intensity average is around 2% of semiconductor COGS this is only representing the industry average as a whole and for Nvidia we believe test intensity is about 3% on average for CoWoS chips such as H100. A significant portion of the increase is from system-level test being much more complex. We believe Chroma does have some share. In general, due to Nvidia’s insane margins, the COGS is not insane for their shipments.

Also, due to AI dollars cannibalising x86 dollars, testing spend will have other interesting impacts. Given Intel’s test strategy inefficiencies, Intel’s testing times are 2-3x compared to peers, which means Intel over indexes on ATE spend. So less demand for Intel servers would also result in a disproportionately larger reduction in ATE spending.

Overall, Advantest doesn’t benefit as much as the market believes in our opinion.

However, beyond the ATE suppliers, there are suppliers of other components used in the test flow. For example, the test sockets used to interface with the device under test such as Winway and MPI in Taiwan. These test sockets are a strong vector of demand for increasingly complex chips.

Look Elsewhere – Flip Chip Bonders

Our model indicates that the number of die attach steps in the CoWoS process will more than triple from Q2 2023 to Q4 2024 off the back of increased volumes and complexity as the number of chips per package increases with future Nvidia and hyperscaler silicon. We spent a lot of time modeling the number of die attach steps per package per design, the number of CoWoS steps, and the throughput of flip chip bonders.

Various companies supply bonders: BESI is leading, followed by ASM Pacific. Recently Shibaura has started shipping to TSMC for CoWoS-related flip chip. APIC Yamada (a subsidiary) also provides bonders to TSMC. We note that currently, TSMC is using a standard mass reflow process for flip chip bonding, however, in the future, TSMC may also start to incorporate Thermocompression Bonding (TCB) in its CoWoS process flow which may be necessary for finer microbump pitches. When they do, ASM Pacific is best positioned as the winner. K&S and BESI seem like long shots for this socket.

As of now, Intel is the only user of TCB for logic packaging but we note that ASM Pacific has recently shipped an evaluation tool to TSMC. Given TCB tools’ much lower throughput and higher cost compared to traditional flip chip bonders, if TCB is adopted this could be a more significant revenue impact.

Without TCB though, the impact of flipchip bonders is tiny from the massive CoWoS expansion. Even when using production throughput figures instead of inflated figures quoted by tool makers, you still arrive at less than $25 million dollar Capex associated to flip chip bonders for the current CoWoS expansion through the end of the year. This is divvied up among suppliers, albeit with BESI as the leader. It’s quite immaterial.

Lithography

Veeco and Canon are leaders in supplying steppers for back-end lithography used for patterning TSVs, RDLs, etc. ASML and Nikon only have share in the RDL and TSV formation for the passive silicon interposer. There are very few layers here relative to memory and leading-edge logic. The shift to advanced packaging actually reduces ASML’s overall industry litho intensity.

The lithography steppers of Canon and Veeco are not as advanced as ASML’s and Nikon’s but provide higher productivity and better cost. High resolution is not required given TSVs, pillars, and RDLs have pitches measured as low as hundreds of nanometers, but often multi-micron range compared to transistor layers and low metal layers on logic that are measured in tens of nanometers.

Canon expects more unit shipments in FY2023 for semiconductor lithography compared to FY2022. Interestingly, Veeco recently cited weakness in advanced packaging, which contrasts with views elsewhere in the supply chain.

We expect growth in our LSA and EUV mask point product lines to more than offset softness in our advanced packaging lithography and wet processing business due to weak consumer electronic demand. 

William Miller, Veeco CEO

Furthermore, Onto has the JetStep, which will further weaken Veeco’s position in lithography as the high throughput low-cost option. Onto is targeting large format panel-based substrates not wafer-level technologies. Canon and Onto are the ones to look at for the lithography component, even though JetStep X500 isn’t used in CoWoS.

Veeco Phased Out – SK Hynix’s HBM Packaging Innovation

Veeco being is being phased out of the wet process flow by SK Hynix’s new HBM packaging innovation.

Until now, SK Hynix has been using the TC-NCF (Thermocompression – Non-Conductive Film) method for stacking HBM die. This is a chip-on-wafer process. NCF is laminated on a bumped wafer. Then an individual memory chip with NFC applied is bonded onto the wafer using thermocompression bonding. The NCF turns into the underfill between the two layers of memory.

For 12-layer HBM, Hynix has developed a technology called “MR-MUF” which stands for Mass Reflow Molded Underfill for stacking memory. In this process, the memory stacks are bonded together by a mass reflow process which delivers higher throughput as the bonding is not done separately for each die but can be completed in a batch process. Then underfill is applied with liquid Epoxy Molding Compound, which has double the thermal conductivity of NCF, which aids with heat. This method offers higher productivity, better yield, and more performance.

For 16-layer HBM, hybrid bonding will be required to reduce stack distance and keep the total package thin.

Veeco’s WaferStorm wet processing platform was used to clean flux residues in the original NCF process. But with MR-MUF, the flux isn’t cleaned the same way, therefore, Veeco loses out on this socket.

As we went into more detail in the prior CoWoS report, SK Hynix dominates in HBM currently. Samsung and, eventually Micron will be following suit and Veeco will be phased out from HBM entirely which represented over 20% of their revenue in some years.

A Double-Edged Sword – Package Substrates

The substrates used are generally High-Density Interconnect substrates with multiple build-up layers.

There are several suppliers who include: Ibiden, Shinko, Nanya PCB, Unimicron, and Kinsus. Ibiden is Nvidia’s sole supplier and is expanding its capacity to meet growing demand from their customers. Kyocera is also aggressively ramping its substrate capacity. Nanya, Kyocera, and Unimicron are working with Alchip for their AWS projects. AMD is also using these suppliers.

Substrates are “built up” with di-electric insulating film supplied by Ajinomoto (Ajinomoto Build-up Film or “ABF). The substrate is laser drilled and filled with copper wiring. Each chip will have its own requirements for number of build-up layers and how the package should be wired.

While in the short-term substrate suppliers (especially Ibiden) may be winners, CoWoS is a double-edged sword for them. The long-term bull case for substrate suppliers is they sell more substrate content: larger substrates with more layers and smaller pitches, which have lower yields. However, with CoWoS, the interposer takes on more of the routing density, which in-turn reduces the need for substrate density. In this sense, front-end has the advantage.

For example, Nvidia’s H100 uses a “5-2-5” substrate which means there are 5 layers of ABF each on the front and back and then a 2 layer “core” in the middle which is made of copper. This is not as complex of a substrate as an AMD or Intel CPU package that reaches a “9-2-9” configuration. These more complex packages have lower yields, taking up far more ABF substrate capacity. Nvidia currently offloads a lot of their package routing complexity to the CoWoS-S interposer. As such AI cannibalization actually means big weakness in substrate, which correlates with what we see in terms of near term pricing for mid-range ABF substrate pricing.

With more advanced interposers on the horizon such as CoWoS-L which has embedded local silicon interconnects to facilitate die to die communication, this could enable interposers to take on even more of the routing work at the expense of the package substrate. In some cases such as EMIB, the substrate supplier is the one who often places the bridge leading to some intensity increases, but in fanout’s such as FOEB, the packaging house such as ASE will. All CoWoS variants have TSMC placing the bridge.

Wafer Grinding and Dicing

DISCO is the major supplier of grinders and polishers that thin and polish wafers, and the saws that dice each individual die and interposer from wafers.

There is an okay amount of intensity for Disco, but we believe the market has appreciated everything that is happening with them. We explicitly called them 1 year ago and the stock has gone up more than 130% since. As a Japanese firm with good margins, near-monopoly status, a fantastic culture, and a more durable business than the pure packaging equipment providers, it is a great firm, but it is over extended in our opinion. Probably has more to do with in-Japan flows.

A Drop in The Bucket – Etch and Deposition

To form TSVs, RDLs, pads, and bumps: patterns need to be etched into substrates, and copper and other metals need to be deposited. We mentioned TSVs needing a high aspect ratio etch to form deep trenches in the interposer via a Deep Reactive Ion Etch. Chemical Vapor Deposition (CVD), Plasma Enhanced Chemical Vapor Deposition (PECVD), Physical Vapor Deposition (PVD), ECD (Electrochemical Deposition) are all various forms of deposition used. The usual suspects Lam Research and Applied Materials have a big presence here, but unfortunately, this doesn’t move the needle for them.

Lam Research plays a key role as etch and dep supplier for packaging. TSVs are also deep trenches so similar to channel holes for 3D NAND so naturally, Lam also supplies the DRIE systems. However, this is a fraction of Lam’s etching business in NAND, which we think is under threat from TEL.

As you look at a cross-section of one of these AI systems now that incorporates not only the GPU but a tremendous amount of high-bandwidth memory, stacks, a tremendous amount of other DRAM, NAND. All of that is packaged up inside of a 2.5D or 3D advanced package. And so just from Lam’s perspective, where we provide processes like the etch and the deposition for those advanced package steps, we see our SAM doubling in just the next 3 to 4 years because of AI — for advanced packaging — for our advanced packaging SAM…

…[W]e’re seeing increased demand for high-bandwidth memory, related tools for the silicon interposer related tools, everything that’s needed to put all those chips together in an AI system…”

…I mentioned [demand] already starting to emerge in things like the advanced packaging, where people realize now I need to add capacity to meet that. That’s a relatively narrow part of our demand profile.

Timothy Archer, Lam Research CEO

This is a drop in the bucket compared to the amount and number of etchs in memory and logic.

The final example is Advanced Packaging. While we are still in the early phases of industry adoption, this inflection is already a great growth area for us. Our packaging revenue has doubled in the past 3 years to over $1 billion. We have strong leadership positions in key enabling technologies, including through-silicon via, microbumping and hybrid bonding. We believe we can double revenues again in the next few years with further adoption of 3D multi-die packaging.

Gary Dickerson, Applied Materials CEO during Q2 2023 earnings call (May 2023)

Applied Materials has more share in hybrid bonding while Lam Research has more in Si Interposer and RDL fan out. As a reminder, Applied Materials gets more dollar share from hybrid bonding than Besi does, but it’s a smaller % of their revenue.

Ultimately, advanced packaging is a nice to have, but too small for these companies to meaningfully inflect on current business. The canabilization of revenue by Nvidia’s margins and huge buildouts for 2025 are for more relevant for Lam Research and Applied Materials.

Nvidia CoWoS Update

Last piece we noted Nvidia was having trouble getting the supply they wanted from TSMC and maybe were double ordering. Our understanding is TSMC is now making the commitment and will get them the capacity to keep Samsung and Amkor/UMC out of the game. While H100 will experience some ASP declines, the refresh should bump it back up, and in general, either Nvidia has over-ordered out the wazoo, or even buy-side consensus for Nvidia bulls is too low…

We have many more thoughts on each of these suppliers and this current expansion, but we wanted to keep this report under 5,000 words (we failed).